lpi2c

package
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 Go to latest Published: Nov 21, 2024 License: BSD-3-Clause Imports: 13 Imported by: 0

Documentation

Overview

Package lpi2c provides a high-level interface to the LPI2C peripheral.

Index

Constants

View Source 
const (
	FEATURE   uint32 = 0xFFFF << 0 //+ Feature Specification Number
	FEATURE_2 uint32 = 0x02 << 0   //  Master only, with standard feature set
	FEATURE_3 uint32 = 0x03 << 0   //  Master and slave, with standard feature set
	MINOR     uint32 = 0xFF << 16  //+ Minor Version Number
	MAJOR     uint32 = 0xFF << 24  //+ Major Version Number
)

VERID

View Source 
const (
	FEATUREn = 0
	MINORn   = 16
	MAJORn   = 24
)
View Source 
const (
	MTXFIFO uint32 = 0x0F << 0 //+ Master Transmit FIFO Size
	MRXFIFO uint32 = 0x0F << 8 //+ Master Receive FIFO Size
)

PARAM

View Source 
const (
	MTXFIFOn = 0
	MRXFIFOn = 8
)
View Source 
const (
	MENn    = 0
	MRSTn   = 1
	MDOZENn = 2
	MDBGENn = 3
	MRTFn   = 8
	MRRFn   = 9
)
View Source 
const (
	MTDFn  = 0
	MRDFn  = 1
	MEPFn  = 8
	MSDFn  = 9
	MNDFn  = 10
	MALFn  = 11
	MFEFn  = 12
	MPLTFn = 13
	MDMFn  = 14
	MBFn   = 24
	MBBFn  = 25
)
View Source 
const (
	HRENn    = 0
	HRPOLn   = 1
	HRSELn   = 2
	CIRFIFOn = 8
	RDMOn    = 9
)
View Source 
const (
	MPRESCALEn = 0
	MAUTOSTOPn = 8
	MIGNACKn   = 9
	MTIMECFGn  = 10
	MATCFGn    = 16
	MPINCFGn   = 24
)
View Source 
const (
	MBUSIDLEn = 0
	MFILTSCLn = 16
	MFILTSDAn = 24
)
View Source 
const (
	MATCH0n = 0
	MATCH1n = 16
)
View Source 
const (
	CLKLOn   = 0
	CLKHIn   = 8
	SETHOLDn = 16
	DATAVDn  = 24
)
View Source 
const (
	TXWATERn = 0
	RXWATERn = 16
)
View Source 
const (
	TXCOUNTn = 0
	RXCOUNTn = 16
)
View Source 
const (
	DATA        int16 = 0xFF << 0 //+ Transmit Data
	CMD         int16 = 0x07 << 8 //+ Command Data
	Send        int16 = 0x00 << 8 //  Transmit DATA[7:0]
	Recv        int16 = 0x01 << 8 //  Receive (DATA[7:0] + 1) bytes
	Stop        int16 = 0x02 << 8 //  Generate STOP condition
	Discard     int16 = 0x03 << 8 //  Receive and discard (DATA[7:0] + 1) bytes
	Start       int16 = 0x04 << 8 //  Generate (repeated) START and transmit address in DATA[7:0]
	StartNACK   int16 = 0x05 << 8 //  Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
	StartHS     int16 = 0x06 << 8 //  Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
	StartHSNACK int16 = 0x07 << 8 //  Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
)
View Source 
const (
	DATAn = 0
	CMDn  = 8
)
View Source 
const (
	SENn     = 0
	SRSTn    = 1
	SFILTENn = 4
	SFILTDZn = 5
	SRTFn    = 8
	SRRFn    = 9
)
View Source 
const (
	STDFn  = 0
	SRDFn  = 1
	SAVFn  = 2
	STAFn  = 3
	SRSFn  = 8
	SSDFn  = 9
	SBEFn  = 10
	SFEFn  = 11
	SAM0Fn = 12
	SAM1Fn = 13
	SGCFn  = 14
	SSARFn = 15
	SBFn   = 24
	SBBFn  = 25
)
View Source 
const (
	TDDEn = 0
	RDDEn = 1
	AVDEn = 2
)
View Source 
const (
	SADRSTALLn = 0
	SRXSTALLn  = 1
	STXDSTALLn = 2
	SACKSTALLn = 3
	SGCENn     = 8
	SSAENn     = 9
	STXCFGn    = 10
	SRXCFGn    = 11
	SIGNACKn   = 12
	SHSMENn    = 13
	SADDRCFGn  = 16
)
View Source 
const (
	SCLKHOLDn = 0
	SDATAVDn  = 8
	SFILTSCLn = 16
	SFILTSDAn = 24
)
View Source 
const (
	ADDR0n = 1
	ADDR1n = 17
)
View Source 
const (
	RADDRn = 0
	ANVn   = 14
)
View Source 
const (
	RXDATAn  = 0
	RXEMPTYn = 14
	SOFn     = 15
)
View Source 
const MasterErrFlags = MNDF | MALF | MFEF | MPLTF
View Source 
const (
	PINLOWn = 8
)
View Source 
const (
	TXNACKn = 0
)

Variables

This section is empty.

Functions

This section is empty.

Types

type DER 

type DER uint32
const (
	TDDE DER = 0x01 << 0 //+ Transmit Data DMA Enable
	RDDE DER = 0x01 << 1 //+ Receive Data DMA Enable
	AVDE DER = 0x01 << 2 //+ Address Valid DMA Enable (slave only)
)

type MCCR 

type MCCR uint32
const (
	CLKLO   MCCR = 0x3F << 0  //+ Clock Low Period
	CLKHI   MCCR = 0x3F << 8  //+ Clock High Period
	SETHOLD MCCR = 0x3F << 16 //+ Setup Hold Delay
	DATAVD  MCCR = 0x3F << 24 //+ Data Valid Delay
)

type MCFGR0 

type MCFGR0 uint32
const (
	HREN    MCFGR0 = 0x01 << 0 //+ Host Request Enable
	HRPOL   MCFGR0 = 0x01 << 1 //+ Host Request Polarity
	HRSEL   MCFGR0 = 0x01 << 2 //+ Host Request Select
	CIRFIFO MCFGR0 = 0x01 << 8 //+ Circular FIFO Enable
	RDMO    MCFGR0 = 0x01 << 9 //+ Receive Data Match Only
)

type MCFGR1 

type MCFGR1 uint32
const (
	MPRESCALE              MCFGR1 = 0x07 << 0  //+ Prescaler
	Div1                   MCFGR1 = 0x00 << 0  //  Divide by 1
	Div2                   MCFGR1 = 0x01 << 0  //  Divide by 2
	Div4                   MCFGR1 = 0x02 << 0  //  Divide by 4
	Div8                   MCFGR1 = 0x03 << 0  //  Divide by 8
	Div16                  MCFGR1 = 0x04 << 0  //  Divide by 16
	Div32                  MCFGR1 = 0x05 << 0  //  Divide by 32
	Div64                  MCFGR1 = 0x06 << 0  //  Divide by 64
	Div128                 MCFGR1 = 0x07 << 0  //  Divide by 128
	MAUTOSTOP              MCFGR1 = 0x01 << 8  //+ Automatic STOP Generation
	MIGNACK                MCFGR1 = 0x01 << 9  //+ IGNACK
	MTIMECFG               MCFGR1 = 0x01 << 10 //+ Timeout Configuration
	MATCFG                 MCFGR1 = 0x07 << 16 //+ Match Configuration
	Disable                MCFGR1 = 0x00 << 16 //  Match is disabled
	D0eqM0_or_D0eqM1       MCFGR1 = 0x02 << 16 //  Match is enabled (1st data word equals MATCH0 OR MATCH1)
	DXeqM0_or_DXeqM1       MCFGR1 = 0x03 << 16 //  Match is enabled (any data word equals MATCH0 OR MATCH1)
	D0D1_eq_M0M1           MCFGR1 = 0x04 << 16 //  Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
	DXDX1_eq_M0M1          MCFGR1 = 0x05 << 16 //  Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
	D0andM0_eq_M0andM1     MCFGR1 = 0x06 << 16 //  Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
	DXandM0_eq_M0andM1     MCFGR1 = 0x07 << 16 //  Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
	MPINCFG                MCFGR1 = 0x07 << 24 //+ Pin Configuration
	OpenDrain2pin          MCFGR1 = 0x00 << 24 //  2-pin open drain mode
	OutputOnly2pin         MCFGR1 = 0x01 << 24 //  2-pin output only mode (ultra-fast mode)
	PushPull2pin           MCFGR1 = 0x02 << 24 //  2-pin push-pull mode
	PushPull4pin           MCFGR1 = 0x03 << 24 //  4-pin push-pull mode
	OpenDrain2pinSepSlave  MCFGR1 = 0x04 << 24 //  2-pin open drain mode with separate LPI2C slave
	OutputOnly2pinSepSlave MCFGR1 = 0x05 << 24 //  2-pin output only mode (ultra-fast mode) with separate LPI2C slave
	PushPull2pinSepSlave   MCFGR1 = 0x06 << 24 //  2-pin push-pull mode with separate LPI2C slave
	PushPull4pinInverted   MCFGR1 = 0x07 << 24 //  4-pin push-pull mode (inverted outputs)
)

type MCFGR2 

type MCFGR2 uint32
const (
	MBUSIDLE MCFGR2 = 0xFFF << 0 //+ Bus Idle Timeout
	MFILTSCL MCFGR2 = 0x0F << 16 //+ Glitch Filter SCL
	MFILTSDA MCFGR2 = 0x0F << 24 //+ Glitch Filter SDA
)

type MCFGR3 

type MCFGR3 uint32
const (
	PINLOW MCFGR3 = 0xFFF << 8 //+ Pin Low Timeout
)

type MCR 

type MCR uint32
const (
	MEN    MCR = 0x01 << 0 //+ Master Enable
	MRST   MCR = 0x01 << 1 //+ Software Reset
	MDOZEN MCR = 0x01 << 2 //+ Doze mode enable
	MDBGEN MCR = 0x01 << 3 //+ Debug Enable
	MRTF   MCR = 0x01 << 8 //+ Reset Transmit FIFO
	MRRF   MCR = 0x01 << 9 //+ Reset Receive FIFO
)

type MDMR 

type MDMR uint32
const (
	MATCH0 MDMR = 0xFF << 0  //+ Match 0 Value
	MATCH1 MDMR = 0xFF << 16 //+ Match 1 Value
)

type MFCR 

type MFCR uint32
const (
	TXWATER MFCR = 0x03 << 0  //+ Transmit FIFO Watermark
	RXWATER MFCR = 0x03 << 16 //+ Receive FIFO Watermark
)

type MFSR 

type MFSR uint32
const (
	TXCOUNT MFSR = 0x07 << 0  //+ Transmit FIFO Count
	RXCOUNT MFSR = 0x07 << 16 //+ Receive FIFO Count
)

type MSR 

type MSR uint32
const (
	MTDF  MSR = 0x01 << 0  //+ Transmit Data Flag
	MRDF  MSR = 0x01 << 1  //+ Receive Data Flag
	MEPF  MSR = 0x01 << 8  //+ End Packet Flag
	MSDF  MSR = 0x01 << 9  //+ STOP Detect Flag
	MNDF  MSR = 0x01 << 10 //+ NACK Detect Flag
	MALF  MSR = 0x01 << 11 //+ Arbitration Lost Flag
	MFEF  MSR = 0x01 << 12 //+ FIFO Error Flag
	MPLTF MSR = 0x01 << 13 //+ Pin Low Timeout Flag
	MDMF  MSR = 0x01 << 14 //+ Data Match Flag
	MBF   MSR = 0x01 << 24 //+ Master Busy Flag
	MBBF  MSR = 0x01 << 25 //+ Bus Busy Flag
)

type Master 

type Master struct {
	sync.Mutex // use with the low-level interface to share the driver
	// contains filtered or unexported fields
}

A Master is a driver for the LPI2C peripheral. It provides two kinds of interfaces to communicate with slave devices on the I2C bus.

The first interface is a low-level one. It provides a set of methods to directly interract with the Data / Command FIFOs of the underlying LPI2C peripheral.

Example: 

d.WriteCmds(
	lpi2c.Start|eepromAddr<<1|wr,
	lpi2c.Send|int16(memAddr),
	lpi2c.Start|eepromAddr<<1|rd,
	lpi2c.Recv|int16(len(buf) - 1),
	lpi2c.Stop,
)
d.Read(buf)
if err := d.Err(true); err != nil {

Write methods in the low-level interface are asynchronous, that is, they may return before all commands/data will be written to the FIFO. Therefore you must not modify the data/command buffer pass to the last write method until the return of the Flush method or another write method.

The read/write methods doesn't return errors. There is an Err method that allow to check and reset the LPI2C error flags at a convenient time. Even if you call Err after every method call the returned error is still asynchronous due to the asynchronous nature of the write methods and the delayed execution of commands by the LPI2C peripheral itself. You can use Wait to synchronise things but it seems that only the MSDF flag (Stop Condition) can be used to to synchronize errors.

The second interface is a connection oriented one that implements the i2cbus.Conn interface.

Example: 

c := d.NewConn(eepromAddr)
c.WriteByte(memAaddr)
c.Read(buf)
err := c.Close()
if err != nil {

Both interfaces may be used concurently by multiple goroutines but in such a case users of the low-level interface must gain an exclusive access to the driver using the embedded mutex and wait for the Stop Condition before unlocking the Master.

func NewMaster 

func NewMaster(p *Periph, dma dma.Channel) *Master

NewMaster returns a new master-mode driver for p. If valid DMA channel is given, the DMA will be used for bigger data transfers.

func (*Master) Clear 

func (d *Master) Clear(flags MSR)

Clear allows to clear the MEPF, MSDF, MDMF in the MSR register. It is intended to be used together with the Wait method to wait for events signaled by these flags.

func (*Master) DMAISR 

func (d *Master) DMAISR()

DMAISR is a DMA interrupt handler for the DMA channel used by Master.

func (*Master) Err 

func (d *Master) Err(clear bool) error

Err returns the content of the MSR register wrapped into the MasterError type if any error flag (see MasterErrFlags) is set. Othewrise it returns nil. If clear is true Err clears the Tx FIFO and the error flags in the MSR register and if the LPI2C peripheral is in the busy state (MSR[MBF] is set) it also releases the bus by writing the Stop command into Tx FIFO.

func (*Master) Flush 

func (d *Master) Flush()

Flush waits for the last command passed to the last WriteCmd call or last data byte passed to the last Write/WriteString call to be written to the Tx FIFO. Return from Flush doesn't mean the written commands/data were or even will be executed/sent.

func (*Master) ID 

func (d *Master) ID() uint8

ID rteturns the Master ID. See SetID for more information.

func (*Master) ISR 

func (d *Master) ISR()

ISR is the interrupt handler for the LPI2C peripheral used by Master.

func (*Master) Name 

func (d *Master) Name() string

Name implements the i2cbus.Master interface. The default name is the name of the underlying peripheral (e.g. "LPI2C1") but can be changed using SetName.

func (*Master) NewConn 

func (d *Master) NewConn(a i2cbus.Addr) i2cbus.Conn

NewConn implements the i2cbus.Master interface.

func (*Master) Periph 

func (d *Master) Periph() *Periph

Periph returns the underlying LPSPI peripheral.

func (*Master) Read 

func (d *Master) Read(p []byte)

Read reads len(p) data bytes from Rx FIFO. The read data is valid if Err returns nil.

func (*Master) ReadByte 

func (d *Master) ReadByte() byte

ReadByte works like Read but reads only one byte from the Rx FIFO.

func (*Master) SetID 

func (d *Master) SetID(id uint8)

SetID sets the Master ID. Its three least significant bits are used for arbitration between competing masters while switching to the High Speed mode.

func (*Master) SetName 

func (d *Master) SetName(s string)

SetName allows to change the default master name (see Name).

func (*Master) Setup 

func (d *Master) Setup(sp Speed)

func (*Master) Status 

func (d *Master) Status() MSR

Status returns the current status of the LPSPI Master. It's intended do to be used with together with the Clear and Wait methods to check which of the events we were waiting for actually took place.

You won't read this in the RM:

In caes of repeated START the detection of NACK causes setting of both MSDF and MEPF flags. Usually MNDF flag is set before MSDF, MEPF but sometimes it happens in the reverse order. After NACK the SDA stays high, the SCL stays low which probably causes that the MBF and MBBF flags are set. The only way to clear MBF,MBBF is to write the Stop command into MTDR or reset the peripheral (disabling and reenabling it doesn't work). After the Stop command SCL is momentarily pulled low to allow releasing SDA and next SCL what corresponds to the Stop Condition on the bus. SM says that MBBF reflets the bus state. But it's not cleare how MBF and MBBF relate to each other.

func (*Master) UsePin 

func (d *Master) UsePin(pin iomux.Pin, sig Signal) bool

UsePin is a helper function that can be used to configure IO pins as required by LPI2C peripheral. It configures the pin as open-drain output with the internal 22 kΩ pull-up resistor enadbled so you can avoid external pull-up resistors for low-capacitance bus and low-speed transfers.

Only certain pins can be used forLPI2C peripheral (see datasheet). UsePin returns true on succes or false if it isn't possible to use a pin as a sig.

func (*Master) Wait 

func (d *Master) Wait(flags MSR)

Wait waits for an event described by the MEPF, MSDF, MDMF, MTDF flags or an error. The MTDF flag allows to wait for an empty Tx FIFO. In most cases you should clear the flag you want to wait for.

func (*Master) Write 

func (d *Master) Write(p []byte)

Write is like WriteCmds but writes only Send commands with the provided data.

func (*Master) WriteCmd 

func (d *Master) WriteCmd(cmd int16)

WriteCmd works like WriteCmds but writes only one command word into the Tx FIFO.

func (*Master) WriteCmds 

func (d *Master) WriteCmds(cmds []int16)

WriteCmds starts writing commands into the Tx FIFO in the background using interrupts and/or DMA. WriteCmd is no-op if len(cmds) == 0.

The LPI2C concept of a combined command and data FIFO greatly simplifies use of the I2C protocol. Thanks to this concept an I2C transaction or even multiple transactions can be prepared in advance as an array of commands and data, including receive transactions if the amount of data is known.

There is, however, a certain weakness of the LPI2C peripheral when it comes to receiving data of an unknown quantity or if the data should be slowly received in chunks of size less than the Rx FIFO. Such transfers may require issuing repeat start conditions after each chunk to avoid MSR[FEF] error. This is because the LPI2C periperal transmits NACK at the end of the Recv command if the Rx FIFO isn't full and there is no next Recv or Discard command in the Tx FIFO. Two or more consecutive Recv commands in the list passed to WriteCmds may also cause the FIFO error because there is no guarantee that they will all get into the Tx FIFO on time.

func (*Master) WriteString 

func (d *Master) WriteString(s string)

WriteString is like Write but writes bytes from string instead of slice.

type MasterError 

type MasterError struct {
	Status MSR // value of the Master Status Register as read by Master.Err
}

MasterError contains value of the Master Status Register with one or more error flags set.

func (*MasterError) Error 

func (e *MasterError) Error() string

type Periph 

type Periph struct {
	VERID mmio.R32[uint32] // Version ID Register
	PARAM mmio.R32[uint32] // Parameter Register

	MCR    mmio.R32[MCR]    // Master Control Register
	MSR    mmio.R32[MSR]    // Master Status Register
	MIER   mmio.R32[MSR]    // Master Interrupt Enable Register
	MDER   mmio.R32[DER]    // Master DMA Enable Register
	MCFGR0 mmio.R32[MCFGR0] // Master Configuration Register 0
	MCFGR1 mmio.R32[MCFGR1] // Master Configuration Register 1
	MCFGR2 mmio.R32[MCFGR2] // Master Configuration Register 2
	MCFGR3 mmio.R32[MCFGR3] // Master Configuration Register 3

	MDMR mmio.R32[MDMR] // Master Data Match Register

	MCCR0 mmio.R32[MCCR] // Master Clock Configuration Register 0

	MCCR1 mmio.R32[MCCR] // Master Clock Configuration Register 1

	MFCR mmio.R32[MFCR]  // Master FIFO Control Register
	MFSR mmio.R32[MFSR]  // Master FIFO Status Register
	MTDR mmio.R16[int16] // Master Transmit Data Register

	MRDR mmio.R32[RDR] // Master Receive Data Register

	SCR  mmio.R32[SCR] // Slave Control Register
	SSR  mmio.R32[SSR] // Slave Status Register
	SIER mmio.R32[SSR] // Slave Interrupt Enable Register
	SDER mmio.R32[DER] // Slave DMA Enable Register

	SCFGR1 mmio.R32[SCFGR1] // Slave Configuration Register 1
	SCFGR2 mmio.R32[SCFGR2] // Slave Configuration Register 2

	SAMR mmio.R32[SAMR] // Slave Address Match Register

	SASR mmio.R32[SASR] // Slave Address Status Register
	STAR mmio.R32[STAR] // Slave Transmit ACK Register

	STDR mmio.R32[uint32] // Slave Transmit Data Register

	SRDR mmio.R32[RDR] // Slave Receive Data Register
	// contains filtered or unexported fields
}

func LPI2C 

func LPI2C(n int) *Periph

LPI2C returns the LPI2Cn peripheral.

func (*Periph) EnableClock 

func (p *Periph) EnableClock(lp bool)

EnableClock enables the clock for the LPI2C peripheral. lp determines whether the clock remains on in low power WAIT mode.

func (*Periph) Pins 

func (p *Periph) Pins(sig Signal) []iomux.Pin

Pins return IO pins that can be used for singal sig.

type RDR 

type RDR uint32
const (
	RXDATA  RDR = 0xFF << 0  //+ Receive Data
	RXEMPTY RDR = 0x01 << 14 //+ RX Empty
	SOF     RDR = 0x01 << 15 //+ Start Of Frame (slave only)
)

type SAMR 

type SAMR uint32
const (
	ADDR0 SAMR = 0x3FF << 1  //+ Address 0 Value
	ADDR1 SAMR = 0x3FF << 17 //+ Address 1 Value
)

type SASR 

type SASR uint32
const (
	RADDR SASR = 0x7FF << 0 //+ Received Address
	ANV   SASR = 0x01 << 14 //+ Address Not Valid
)

type SCFGR1 

type SCFGR1 uint32
const (
	SADRSTALL SCFGR1 = 0x01 << 0  //+ Address SCL Stall
	SRXSTALL  SCFGR1 = 0x01 << 1  //+ RX SCL Stall
	STXDSTALL SCFGR1 = 0x01 << 2  //+ TX Data SCL Stall
	SACKSTALL SCFGR1 = 0x01 << 3  //+ ACK SCL Stall
	SGCEN     SCFGR1 = 0x01 << 8  //+ General Call Enable
	SSAEN     SCFGR1 = 0x01 << 9  //+ SMBus Alert Enable
	STXCFG    SCFGR1 = 0x01 << 10 //+ Transmit Flag Configuration
	SRXCFG    SCFGR1 = 0x01 << 11 //+ Receive Data Configuration
	SIGNACK   SCFGR1 = 0x01 << 12 //+ Ignore NACK
	SHSMEN    SCFGR1 = 0x01 << 13 //+ High Speed Mode Enable
	SADDRCFG  SCFGR1 = 0x07 << 16 //+ Address Configuration
	ADDRCFG_0 SCFGR1 = 0x00 << 16 //  Address match 0 (7-bit)
	ADDRCFG_1 SCFGR1 = 0x01 << 16 //  Address match 0 (10-bit)
	ADDRCFG_2 SCFGR1 = 0x02 << 16 //  Address match 0 (7-bit) or Address match 1 (7-bit)
	ADDRCFG_3 SCFGR1 = 0x03 << 16 //  Address match 0 (10-bit) or Address match 1 (10-bit)
	ADDRCFG_4 SCFGR1 = 0x04 << 16 //  Address match 0 (7-bit) or Address match 1 (10-bit)
	ADDRCFG_5 SCFGR1 = 0x05 << 16 //  Address match 0 (10-bit) or Address match 1 (7-bit)
	ADDRCFG_6 SCFGR1 = 0x06 << 16 //  From Address match 0 (7-bit) to Address match 1 (7-bit)
	ADDRCFG_7 SCFGR1 = 0x07 << 16 //  From Address match 0 (10-bit) to Address match 1 (10-bit)
)

type SCFGR2 

type SCFGR2 uint32
const (
	SCLKHOLD SCFGR2 = 0x0F << 0  //+ Clock Hold Time
	SDATAVD  SCFGR2 = 0x3F << 8  //+ Data Valid Delay
	SFILTSCL SCFGR2 = 0x0F << 16 //+ Glitch Filter SCL
	SFILTSDA SCFGR2 = 0x0F << 24 //+ Glitch Filter SDA
)

type SCR 

type SCR uint32
const (
	SEN     SCR = 0x01 << 0 //+ Slave Enable
	SRST    SCR = 0x01 << 1 //+ Software Reset
	SFILTEN SCR = 0x01 << 4 //+ Filter Enable
	SFILTDZ SCR = 0x01 << 5 //+ Filter Doze Enable
	SRTF    SCR = 0x01 << 8 //+ Reset Transmit FIFO
	SRRF    SCR = 0x01 << 9 //+ Reset Receive FIFO
)

type SSR 

type SSR uint32
const (
	STDF  SSR = 0x01 << 0  //+ Transmit Data Flag
	SRDF  SSR = 0x01 << 1  //+ Receive Data Flag
	SAVF  SSR = 0x01 << 2  //+ Address Valid Flag
	STAF  SSR = 0x01 << 3  //+ Transmit ACK Flag
	SRSF  SSR = 0x01 << 8  //+ Repeated Start Flag
	SSDF  SSR = 0x01 << 9  //+ STOP Detect Flag
	SBEF  SSR = 0x01 << 10 //+ Bit Error Flag
	SFEF  SSR = 0x01 << 11 //+ FIFO Error Flag
	SAM0F SSR = 0x01 << 12 //+ Address Match 0 Flag
	SAM1F SSR = 0x01 << 13 //+ Address Match 1 Flag
	SGCF  SSR = 0x01 << 14 //+ General Call Flag
	SSARF SSR = 0x01 << 15 //+ SMBus Alert Response Flag
	SBF   SSR = 0x01 << 24 //+ Slave Busy Flag
	SBBF  SSR = 0x01 << 25 //+ Bus Busy Flag
)

type STAR 

type STAR uint32
const (
	TXNACK STAR = 0x01 << 0 //+ Transmit NACK
)

type Signal 

type Signal int8
const (
	SCL  Signal = iota // clock
	SDA                // data
	SCLS               // secondary clock (only LPI2C1)
	SDAS               // secondary data (only LPI2C1)
	HREQ               // host request
)

type Speed 

type Speed uint64

Speed encodes the timing configuration that determines the maximum communication speed (the actual speed depends also on the SCL rise time). 

const (
	Slow50k    Speed = timingSlow   //  ≤58 kb/s (slow)     and 0.83 Mb/s HS
	Std100k    Speed = timingStd    // ≤114 kb/s (standard) and 1.65 Mb/s HS
	Fast400k   Speed = timingFast   // ≤400 kb/s (Fast)     and 1.65 Mb/s HS
	FastPlus1M Speed = timingPlus   //   ≤1 Mb/s (Fast+)    and 1.65 Mb/s HS
	FastHS     Speed = timingFastHS // ≤400 kb/s (Fast)     and 3.33 Mb/s HS
	FastPlusHS Speed = timingPlusHS //   ≤1 Mb/s (Fast+)    and 3.33 Mb/s HS
)

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