dma

package
v0.0.9 Latest Latest
Warning

This package is not in the latest version of its module.

 Go to latest Published: Nov 21, 2024 License: BSD-3-Clause Imports: 6 Imported by: 0

Documentation

Overview

Package dma provides interface to the eDMA controller. The interface is based on two main types: Controller and Channel.

Controller represents an instance of eDMA module (DMA engine and TCD memory) together with the corresponding DMAMUX. Each controller provides 32 channels.

Channel represents a DMA+DMAMUX channel together with the corresponding location in TCD memory. You can select a specific channel using the Controller.Channel method but the prefered way to obtain a channel is to use Controller.AllocChannel which arbitrarily allocate an unused one.

When this package is imported it alters the default configuration of all available controllers to use round robin arbitration and to halt on error. The default fixed priority arbitration with its requirement of unique channel prioritiesis does not work well with the Controller.AllocChannel method. Additionally, there is a problem with canceling a transfer in fixed priority mode if channel preemption is enabled.

Index

Constants

View Source 
const (
	MLOFF int32 = 0x0fffff << 10 //+ Sign-extended offset applied to the source or destination address after the minor loop completes.
	DMLOE int32 = 0x01 << 30     //+ Destination Minor Loop Offset enable
	SMLOE int32 = -0x1 << 31     //+ Source Minor Loop Offset Enable

	MLOFFn = 10
	DMLOEn = 30
	SMLOEn = 31
)

ML_NBYTES ML fields

View Source 
const (
	LINKCH int16 = 0x1F << 9  //+ Minor Loop Link Channel Number
	ELINK  int16 = -0x1 << 15 //+ Enable channel-to-channel linking on minor-loop complete

	LINKCHn = 9
	ELINKn  = 15
)

ELINK_CITER, ELINK_BITER ELINK fields

View Source 
const (
	START       CSR = 0x01 << 0  //+ Channel Start
	INTMAJOR    CSR = 0x01 << 1  //+ Enable an interrupt when major iteration count completes
	INTHALF     CSR = 0x01 << 2  //+ Enable an interrupt when major counter is half complete
	DREQ        CSR = 0x01 << 3  //+ Disable Request at the end of major loop.
	ESG         CSR = 0x01 << 4  //+ Enable Scatter/Gather Processing
	MAJORELINK  CSR = 0x01 << 5  //+ Enable channel-to-channel linking on major loop complete
	ACTIVE      CSR = 0x01 << 6  //+ Channel Active
	DONE        CSR = 0x01 << 7  //+ Channel Done
	MAJORLINKCH CSR = 0x1F << 8  //+ Major Loop Link Channel Number
	BWC         CSR = 0x03 << 14 //+ Bandwidth Control
	Stall0c     CSR = 0x00 << 14 //  No eDMA engine stalls
	Stall4c     CSR = 0x02 << 14 //  eDMA engine stalls for 4 cycles after each R/W
	Stall8c     CSR = 0x03 << 14 //  eDMA engine stalls for 8 cycles after each R/W

	STARTn       = 0
	INTMAJORn    = 1
	INTHALFn     = 2
	DREQn        = 3
	ESGn         = 4
	MAJORELINKn  = 5
	ACTIVEn      = 6
	DONEn        = 7
	MAJORLINKCHn = 8
	BWCn         = 14
)
View Source 
const (
	CHPRI  Prio = 0x0F << 0 //+ Arbitration Priority
	GRPPRI Prio = 0x03 << 4 //+ Current Group Priority
	DPA    Prio = 0x01 << 6 //+ Disable Preempt Ability
	ECP    Prio = 0x01 << 7 //+ Enable Channel Preemption

	CHPRIn  = 0
	GRPPRIn = 4
	DPAn    = 6
	ECPn    = 7
)
View Source 
const (
	EDBG    CR = 0x01 << 1  //+ Enable Debug
	ERCA    CR = 0x01 << 2  //+ Enable Round Robin Channel Arbitration
	ERGA    CR = 0x01 << 3  //+ Enable Round Robin Group Arbitration
	HOE     CR = 0x01 << 4  //+ Halt On Error
	HALT    CR = 0x01 << 5  //+ Halt DMA Operations
	CLM     CR = 0x01 << 6  //+ Continuous Link Mode
	EMLM    CR = 0x01 << 7  //+ Enable Minor Loop Mapping
	GRP0PRI CR = 0x01 << 8  //+ Channel Group 0 Priority
	GRP1PRI CR = 0x01 << 10 //+ Channel Group 1 Priority
	ECX     CR = 0x01 << 16 //+ Error Cancel Transfer
	CX      CR = 0x01 << 17 //+ Cancel Transfer
	ACT     CR = 0x01 << 31 //+ DMA Active Status

	EDBGn    = 1
	ERCAn    = 2
	ERGAn    = 3
	HOEn     = 4
	HALTn    = 5
	CLMn     = 6
	EMLMn    = 7
	GRP0PRIn = 8
	GRP1PRIn = 10
	ECXn     = 16
	CXn      = 17
	ACTn     = 31
)
View Source 
const (
	DBE Error = 0x01 << 0  //+ Destination Bus Error
	SBE Error = 0x01 << 1  //+ Source Bus Error
	SGE Error = 0x01 << 2  //+ Scatter/Gather Configuration Error
	NCE Error = 0x01 << 3  //+ NBYTES/CITER Configuration Error
	DOE Error = 0x01 << 4  //+ Destination Offset Error
	DAE Error = 0x01 << 5  //+ Destination Address Error
	SOE Error = 0x01 << 6  //+ Source Offset Error
	SAE Error = 0x01 << 7  //+ Source Address Error
	CNE Error = 0x1F << 8  //+ Error Channel Number or Canceled Channel Number
	CPE Error = 0x01 << 14 //+ Channel Priority Error
	GPE Error = 0x01 << 15 //+ Group Priority Error
	CXE Error = 0x01 << 16 //+ Transfer Canceled
	VLD Error = 0x01 << 31 //+ VLD

	DBEn = 0
	SBEn = 1
	SGEn = 2
	NCEn = 3
	DOEn = 4
	DAEn = 5
	SOEn = 6
	SAEn = 7
	CNEn = 8
	CPEn = 14
	GPEn = 15
	CXEn = 16
	VLDn = 31
)
View Source 
const CacheMaint = true

A CacheMaint indicates whether DMA requires cache maintenance.

View Source 
const MemAlign = cacheLineSize

An MemAlign is the prefered memory alignment for DMA operations. It's always power of 2 and defined in such a way that a fully MemAlign aligned (top and bottom) memory region corresponds to the complete data cache lines.

Variables

This section is empty.

Functions

func AlignOffsets added in v0.0.9 

func AlignOffsets(ptr unsafe.Pointer, size uintptr) (start, end uintptr)

AlignOffsets calculatest the start and end offsets to the MemAlign aligned portion of the memory described by ptr and size.

func MakeSlice added in v0.0.5 

func MakeSlice[T any](len, cap int) (slice []T)

MakeSlice works like make([]T, len, cap) but guarantees that the returned slice has the prefered DMA alignment (see MemAlign).

func New added in v0.0.5 

func New[T any]() (ptr *T)

New works like new(T) but guarantees that the allocated variable has the prefered DMA alignment (see MemAlign).

Types

type ATTR 

type ATTR uint16
const (
	DSIZE  ATTR = 0x07 << 0  //+ Destination data transfer size
	D8b    ATTR = 0x00 << 0  //  8-bit
	D16b   ATTR = 0x01 << 0  //  16-bit
	D32b   ATTR = 0x02 << 0  //  32-bit
	D64b   ATTR = 0x03 << 8  //  64-bit
	D4x64b ATTR = 0x05 << 8  //  32-byte burst (4 beats of 64 bits)
	DMOD   ATTR = 0x1F << 3  //+ Destination Address Modulo
	SSIZE  ATTR = 0x07 << 8  //+ Source data transfer size
	S8b    ATTR = 0x00 << 8  //  8-bit
	S16b   ATTR = 0x01 << 8  //  16-bit
	S32b   ATTR = 0x02 << 8  //  32-bit
	S64b   ATTR = 0x03 << 8  //  64-bit
	S4x64b ATTR = 0x05 << 8  //  32-byte burst (4 beats of 64 bits)
	SMOD   ATTR = 0x1F << 11 //+ Source Address Modulo

	DSIZEn = 0
	DMODn  = 3
	SSIZEn = 8
	SMODn  = 11
)

type CR 

type CR uint32

type CSR 

type CSR uint16

type Channel 

type Channel struct {
	// contains filtered or unexported fields
}

A Channel represents a DMA+DMAMUX channel together with the corresponding location in TCD memory.

func (Channel) ClearDone 

func (c Channel) ClearDone()

func (Channel) ClearErr 

func (c Channel) ClearErr()

func (Channel) ClearInt 

func (c Channel) ClearInt()

func (Channel) Contr added in v0.0.5 

func (c Channel) Contr() *Controller

func (Channel) DisableErrInt 

func (c Channel) DisableErrInt()

func (Channel) DisableReq 

func (c Channel) DisableReq()

func (Channel) EnableErrInt 

func (c Channel) EnableErrInt()

func (Channel) EnableReq 

func (c Channel) EnableReq()

func (Channel) ErrIntEnabled 

func (c Channel) ErrIntEnabled() bool

func (Channel) Free 

func (c Channel) Free()

Free frees the channel so the Controller.AllocChannel can allocate it next time.

func (Channel) IsErr 

func (c Channel) IsErr() bool

func (Channel) IsInt 

func (c Channel) IsInt() bool

func (Channel) IsReq 

func (c Channel) IsReq() bool

func (Channel) IsValid 

func (c Channel) IsValid() bool

func (Channel) Mux 

func (c Channel) Mux() Mux

func (Channel) Num added in v0.0.5 

func (c Channel) Num() int

func (Channel) Prio 

func (c Channel) Prio() Prio

Prio returns the current channel priority.

func (Channel) ReadTCD 

func (c Channel) ReadTCD(tcd *TCD)

ReadTCD reads a transfer controll descriptor from TCD memory.

func (Channel) ReqEnabled 

func (c Channel) ReqEnabled() bool

func (Channel) SetMux 

func (c Channel) SetMux(mux Mux)

func (Channel) SetPrio 

func (c Channel) SetPrio(prio Prio)

SetPrio sets the channel priority.

func (Channel) Start 

func (c Channel) Start()

func (Channel) TCD 

func (c Channel) TCD() *TCDIO

TCD returns the pointer to the corresponding TCD memory. You can use it to alter TCD fields in place.

func (Channel) WriteTCD 

func (c Channel) WriteTCD(tcd *TCD)

WriteTCD writes a transfer controll descriptor to the TCD memory. The eDMA memory controller probably informs the eDMA engine if the CSR[START] bit is set so the engine can start channel immediately.

type Controller 

type Controller struct {
	CR mmio.R32[CR]
	// contains filtered or unexported fields
}

A Controller represents an eDMA module together with the corresponding DMAMUX. TODO: expose all registers

func DMA 

func DMA(n int) *Controller

func (*Controller) AllocChannel 

func (d *Controller) AllocChannel(pit bool) Channel

AllocChannel allocates a free channel in the controller. If pit is true the channel must have a periodic triggering capability. AllocChannel returns invalid channel if there is no free channel to be allocated. Use Channel.Free to free an unused channel.

func (*Controller) Channel 

func (d *Controller) Channel(n int) Channel

Channel returns n-th channel of the controller. If you wont to obtain a free channel use AllocChannel.

func (*Controller) DisableClock 

func (d *Controller) DisableClock()

DisableClock disables clock for DMA controller.

func (*Controller) EnableClock 

func (d *Controller) EnableClock(lp bool)

EnableClock enables clock for DMA controller. lp determines whether the clock remains on in low power WAIT mode.

func (*Controller) Err 

func (d *Controller) Err() Error

type Error 

type Error uint32

func (Error) Error 

func (e Error) Error() string

type Mux 

type Mux uint32

A Mux represents a configuration of DMAMUX for a DMA channel. 

const (
	Src Mux = 0x7F << 0  //+ DMA Channel Source (Slot Number)
	AE  Mux = 0x01 << 29 //+ DMA Channel Always Enable
	PIT Mux = 0x01 << 30 //+ DMA Channel Trigger Enable
	En  Mux = 0x01 << 31 //+ DMA Mux Channel Enable

	// Sources (slots)
	FLEXIO1_REQ01     Mux = 0
	FLEXIO2_REQ01     Mux = 1
	LPUART1_TX        Mux = 2
	LPUART1_RX        Mux = 3
	LPUART3_TX        Mux = 4
	LPUART3_RX        Mux = 5
	LPUART5_TX        Mux = 6
	LPUART5_RX        Mux = 7
	LPUART7_TX        Mux = 8
	LPUART7_RX        Mux = 9
	FLEXCAN3          Mux = 11
	CSI               Mux = 12
	LPSPI1_RX         Mux = 13
	LPSPI1_TX         Mux = 14
	LPSPI3_RX         Mux = 15
	LPSPI3_TX         Mux = 16
	LPI2C1            Mux = 17
	LPI2C3            Mux = 18
	SAI1_RX           Mux = 19
	SAI1_TX           Mux = 20
	SAI2_RX           Mux = 21
	SAI2_TX           Mux = 22
	ADC_ETC           Mux = 23
	ADC1              Mux = 24
	ACMP              Mux = 25
	Reserved          Mux = 27
	FLEXSPI_RX        Mux = 28
	FLEXSPI_TX        Mux = 29
	XBAR1_REQ0        Mux = 30
	XBAR1_REQ1        Mux = 31
	FLEXPWM1_CAPT0    Mux = 32
	FLEXPWM1_CAPT1    Mux = 33
	FLEXPWM1_CAPT2    Mux = 34
	FLEXPWM1_CAPT3    Mux = 35
	FLEXPWM1_VAL0     Mux = 36
	FLEXPWM1_VAL1     Mux = 37
	FLEXPWM1_VAL2     Mux = 38
	FLEXPWM1_VAL3     Mux = 39
	FLEXPWM3_CAPT0    Mux = 40
	FLEXPWM3_CAPT1    Mux = 41
	FLEXPWM3_CAPT2    Mux = 42
	FLEXPWM3_CAPT3    Mux = 43
	FLEXPWM3_VAL0     Mux = 44
	FLEXPWM3_VAL1     Mux = 45
	FLEXPWM3_VAL2     Mux = 46
	FLEXPWM3_VAL3     Mux = 47
	QTIMER1_T0_CAPT   Mux = 48
	QTIMER1_T1_CAPT   Mux = 49
	QTIMER1_T2_CAPT   Mux = 50
	QTIMER1_T3_CAPT   Mux = 51
	QTIMER1_T0_CMPLD1 Mux = 52
	QTIMER1_T1_CMPLD2 Mux = 52
	QTIMER1_T1_CMPLD1 Mux = 53
	QTIMER1_T0_CMPLD2 Mux = 53
	QTIMER1_T2_CMPLD1 Mux = 54
	QTIMER1_T3_CMPLD2 Mux = 54
	QTIMER1_T3_CMPLD1 Mux = 55
	QTIMER1_T2_CMPLD2 Mux = 55
	QTIMER3_T0_CAPT   Mux = 56
	QTIMER3_T0_CMPLD1 Mux = 56
	QTIMER3_T1_CMPLD2 Mux = 56
	QTIMER3_T1_CAPT   Mux = 57
	QTIMER3_T1_CMPLD1 Mux = 57
	QTIMER3_T0_CMPLD2 Mux = 57
	QTIMER3_T2_CAPT   Mux = 58
	QTIMER3_T2_CMPLD1 Mux = 58
	QTIMER3_T3_CMPLD2 Mux = 58
	QTIMER3_T3_CAPT   Mux = 59
	QTIMER3_T3_CMPLD1 Mux = 59
	QTIMER3_T2_CMPLD2 Mux = 59
	FLEXSPI2_RX       Mux = 60
	FLEXSPI2_TX       Mux = 61
	FLEXIO1_REQ23     Mux = 64
	FLEXIO2_REQ23     Mux = 65
	LPUART2_TX        Mux = 66
	LPUART2_RX        Mux = 67
	LPUART4_TX        Mux = 68
	LPUART4_RX        Mux = 69
	LPUART6_TX        Mux = 70
	LPUART6_RX        Mux = 71
	LPUART8_TX        Mux = 72
	LPUART8_RX        Mux = 73
	PXP               Mux = 75
	LCDIF             Mux = 76
	LPSPI2_RX         Mux = 77
	LPSPI2_TX         Mux = 78
	LPSPI4_RX         Mux = 79
	LPSPI4_TX         Mux = 80
	LPI2C2            Mux = 81
	LPI2C4            Mux = 82
	SAI3_RX           Mux = 83
	SAI3_TX           Mux = 84
	SPDIF_RX          Mux = 85
	SPDIF_TX          Mux = 86
	ADC2              Mux = 88
	ACMP2             Mux = 89
	ACMP4             Mux = 90
	ENET_T0           Mux = 92
	ENET_T1           Mux = 93
	XBAR1_REQ2        Mux = 94
	XBAR1_REQ3        Mux = 95
	FLEXPWM2_CAPT0    Mux = 96
	FLEXPWM2_CAPT1    Mux = 97
	FLEXPWM2_CAPT2    Mux = 98
	FLEXPWM2_CAPT3    Mux = 99
	FLEXPWM2_VAL0     Mux = 100
	FLEXPWM2_VAL1     Mux = 101
	FLEXPWM2_VAL2     Mux = 102
	FLEXPWM2_VAL3     Mux = 103
	FLEXPWM4_CAPT0    Mux = 104
	FLEXPWM4_CAPT1    Mux = 105
	FLEXPWM4_CAPT2    Mux = 106
	FLEXPWM4_CAPT3    Mux = 107
	FLEXPWM4_VAL0     Mux = 108
	FLEXPWM4_VAL1     Mux = 109
	FLEXPWM4_VAL2     Mux = 110
	FLEXPWM4_VAL3     Mux = 111
	QTIMER2_T0_CAPT   Mux = 112
	QTIMER2_T1_CAPT   Mux = 113
	QTIMER2_T2_CAPT   Mux = 114
	QTIMER2_T3_CAPT   Mux = 115
	QTIMER2_T0_CMPLD1 Mux = 116
	QTIMER2_T1_CMPLD2 Mux = 116
	QTIMER2_T1_CMPLD1 Mux = 117
	QTIMER2_T0_CMPLD2 Mux = 117
	QTIMER2_T2_CMPLD1 Mux = 118
	QTIMER2_T3_CMPLD2 Mux = 118
	QTIMER2_T3_CMPLD1 Mux = 119
	QTIMER2_T2_CMPLD2 Mux = 119
	QTIMER4_T0_CAPT   Mux = 120
	QTIMER4_T0_CMPLD1 Mux = 120
	QTIMER4_T1_CMPLD2 Mux = 120
	QTIMER4_T1_CAPT   Mux = 121
	QTIMER4_T1_CMPLD1 Mux = 121
	QTIMER4_T0_CMPLD2 Mux = 121
	QTIMER4_T2_CAPT   Mux = 122
	QTIMER4_T2_CMPLD1 Mux = 122
	QTIMER4_T3_CMPLD2 Mux = 122
	QTIMER4_T3_CAPT   Mux = 123
	QTIMER4_T3_CMPLD1 Mux = 123
	QTIMER4_T2_CMPLD2 Mux = 123
	ENET2_T0          Mux = 124
	ENET2_T1          Mux = 125
)

type Prio 

type Prio uint8

A Prio contains channel priority and some additional flags used in fixed-priority arbitration mode.

type TCD 

type TCD struct {
	SADDR       unsafe.Pointer // source address
	SOFF        int16          // added to SADDR after each read
	ATTR        ATTR           // transfer attributes
	ML_NBYTES   uint32         // bytes per request (minor loop) or ML config
	SLAST       int32          // added to SADDR at tranrfer end
	DADDR       unsafe.Pointer // destination address
	DOFF        int16          // added to DADDR after each read
	ELINK_CITER int16          // current major loop iter. count, chan. linking
	DLAST_SGA   int32          // added to DADDR at transfer end or next TCD
	CSR         CSR            // controll and status
	ELINK_BITER int16          // starting major loop iteration count
}

A TCD represents a Transfer Control Descriptor

type TCDIO 

type TCDIO struct {
	SADDR       mmio.P32
	SOFF        mmio.R16[int16]
	ATTR        mmio.R16[ATTR]
	ML_NBYTES   mmio.R32[uint32]
	SLAST       mmio.R32[int32]
	DADDR       mmio.P32
	DOFF        mmio.R16[int16]
	ELINK_CITER mmio.R16[int16]
	DLAST_SGA   mmio.R32[int32]
	CSR         mmio.R16[CSR]
	ELINK_BITER mmio.R16[int16]
}

TCDIO represents a location in TCD memory as set of MMIO registers.

Source Files

View all Source files

Directories

Path Synopsis

Jump to

Keyboard shortcuts

? : This menu
/ : Search site
f or F : Jump to
y or Y : Canonical URL
go.dev uses cookies from Google to deliver and enhance the quality of its services and to analyze traffic. Learn more.