Versions in this module Expand all Collapse all v0 v0.0.9 Nov 21, 2024 Changes in this version + const CacheMaint + const MemAlign + func AlignOffsets(ptr unsafe.Pointer, size uintptr) (start, end uintptr) v0.0.8 Aug 5, 2024 v0.0.7 Mar 28, 2024 v0.0.6 Dec 31, 2023 v0.0.5 Dec 24, 2023 Changes in this version + func MakeSlice[T any](len, cap int) (slice []T) + func New[T any]() (ptr *T) type Channel + func (c Channel) Contr() *Controller + func (c Channel) Num() int v0.0.4 Sep 5, 2022 Changes in this version + const ACT + const ACTIVE + const ACTIVEn + const ACTn + const BWC + const BWCn + const CHPRI + const CHPRIn + const CLM + const CLMn + const CNE + const CNEn + const CPE + const CPEn + const CX + const CXE + const CXEn + const CXn + const CacheLineSize + const DAE + const DAEn + const DBE + const DBEn + const DMLOE + const DMLOEn + const DOE + const DOEn + const DONE + const DONEn + const DPA + const DPAn + const DREQ + const DREQn + const ECP + const ECPn + const ECX + const ECXn + const EDBG + const EDBGn + const ELINK + const ELINKn + const EMLM + const EMLMn + const ERCA + const ERCAn + const ERGA + const ERGAn + const ESG + const ESGn + const GPE + const GPEn + const GRP0PRI + const GRP0PRIn + const GRP1PRI + const GRP1PRIn + const GRPPRI + const GRPPRIn + const HALT + const HALTn + const HOE + const HOEn + const INTHALF + const INTHALFn + const INTMAJOR + const INTMAJORn + const LINKCH + const LINKCHn + const MAJORELINK + const MAJORELINKn + const MAJORLINKCH + const MAJORLINKCHn + const MLOFF + const MLOFFn + const NCE + const NCEn + const SAE + const SAEn + const SBE + const SBEn + const SGE + const SGEn + const SMLOE + const SMLOEn + const SOE + const SOEn + const START + const STARTn + const Stall0c + const Stall4c + const Stall8c + const VLD + const VLDn + func Alloc(n int) (cacheAligned []T) + type ATTR uint16 + const D16b + const D32b + const D4x64b + const D64b + const D8b + const DMOD + const DMODn + const DSIZE + const DSIZEn + const S16b + const S32b + const S4x64b + const S64b + const S8b + const SMOD + const SMODn + const SSIZE + const SSIZEn + type CR uint32 + type CSR uint16 + type Channel struct + func (c Channel) ClearDone() + func (c Channel) ClearErr() + func (c Channel) ClearInt() + func (c Channel) DisableErrInt() + func (c Channel) DisableReq() + func (c Channel) EnableErrInt() + func (c Channel) EnableReq() + func (c Channel) ErrIntEnabled() bool + func (c Channel) Free() + func (c Channel) IsErr() bool + func (c Channel) IsInt() bool + func (c Channel) IsReq() bool + func (c Channel) IsValid() bool + func (c Channel) Mux() Mux + func (c Channel) Prio() Prio + func (c Channel) ReadTCD(tcd *TCD) + func (c Channel) ReqEnabled() bool + func (c Channel) SetMux(mux Mux) + func (c Channel) SetPrio(prio Prio) + func (c Channel) Start() + func (c Channel) TCD() *TCDIO + func (c Channel) WriteTCD(tcd *TCD) + type Controller struct + CR mmio.R32[CR] + func DMA(n int) *Controller + func (d *Controller) AllocChannel(pit bool) Channel + func (d *Controller) Channel(n int) Channel + func (d *Controller) DisableClock() + func (d *Controller) EnableClock(lp bool) + func (d *Controller) Err() Error + type Error uint32 + func (e Error) Error() string + type Mux uint32 + const ACMP + const ACMP2 + const ACMP4 + const ADC1 + const ADC2 + const ADC_ETC + const AE + const CSI + const ENET2_T0 + const ENET2_T1 + const ENET_T0 + const ENET_T1 + const En + const FLEXCAN3 + const FLEXIO1_REQ01 + const FLEXIO1_REQ23 + const FLEXIO2_REQ01 + const FLEXIO2_REQ23 + const FLEXPWM1_CAPT0 + const FLEXPWM1_CAPT1 + const FLEXPWM1_CAPT2 + const FLEXPWM1_CAPT3 + const FLEXPWM1_VAL0 + const FLEXPWM1_VAL1 + const FLEXPWM1_VAL2 + const FLEXPWM1_VAL3 + const FLEXPWM2_CAPT0 + const FLEXPWM2_CAPT1 + const FLEXPWM2_CAPT2 + const FLEXPWM2_CAPT3 + const FLEXPWM2_VAL0 + const FLEXPWM2_VAL1 + const FLEXPWM2_VAL2 + const FLEXPWM2_VAL3 + const FLEXPWM3_CAPT0 + const FLEXPWM3_CAPT1 + const FLEXPWM3_CAPT2 + const FLEXPWM3_CAPT3 + const FLEXPWM3_VAL0 + const FLEXPWM3_VAL1 + const FLEXPWM3_VAL2 + const FLEXPWM3_VAL3 + const FLEXPWM4_CAPT0 + const FLEXPWM4_CAPT1 + const FLEXPWM4_CAPT2 + const FLEXPWM4_CAPT3 + const FLEXPWM4_VAL0 + const FLEXPWM4_VAL1 + const FLEXPWM4_VAL2 + const FLEXPWM4_VAL3 + const FLEXSPI2_RX + const FLEXSPI2_TX + const FLEXSPI_RX + const FLEXSPI_TX + const LCDIF + const LPI2C1 + const LPI2C2 + const LPI2C3 + const LPI2C4 + const LPSPI1_RX + const LPSPI1_TX + const LPSPI2_RX + const LPSPI2_TX + const LPSPI3_RX + const LPSPI3_TX + const LPSPI4_RX + const LPSPI4_TX + const LPUART1_RX + const LPUART1_TX + const LPUART2_RX + const LPUART2_TX + const LPUART3_RX + const LPUART3_TX + const LPUART4_RX + const LPUART4_TX + const LPUART5_RX + const LPUART5_TX + const LPUART6_RX + const LPUART6_TX + const LPUART7_RX + const LPUART7_TX + const LPUART8_RX + const LPUART8_TX + const PIT + const PXP + const QTIMER1_T0_CAPT + const QTIMER1_T0_CMPLD1 + const QTIMER1_T0_CMPLD2 + const QTIMER1_T1_CAPT + const QTIMER1_T1_CMPLD1 + const QTIMER1_T1_CMPLD2 + const QTIMER1_T2_CAPT + const QTIMER1_T2_CMPLD1 + const QTIMER1_T2_CMPLD2 + const QTIMER1_T3_CAPT + const QTIMER1_T3_CMPLD1 + const QTIMER1_T3_CMPLD2 + const QTIMER2_T0_CAPT + const QTIMER2_T0_CMPLD1 + const QTIMER2_T0_CMPLD2 + const QTIMER2_T1_CAPT + const QTIMER2_T1_CMPLD1 + const QTIMER2_T1_CMPLD2 + const QTIMER2_T2_CAPT + const QTIMER2_T2_CMPLD1 + const QTIMER2_T2_CMPLD2 + const QTIMER2_T3_CAPT + const QTIMER2_T3_CMPLD1 + const QTIMER2_T3_CMPLD2 + const QTIMER3_T0_CAPT + const QTIMER3_T0_CMPLD1 + const QTIMER3_T0_CMPLD2 + const QTIMER3_T1_CAPT + const QTIMER3_T1_CMPLD1 + const QTIMER3_T1_CMPLD2 + const QTIMER3_T2_CAPT + const QTIMER3_T2_CMPLD1 + const QTIMER3_T2_CMPLD2 + const QTIMER3_T3_CAPT + const QTIMER3_T3_CMPLD1 + const QTIMER3_T3_CMPLD2 + const QTIMER4_T0_CAPT + const QTIMER4_T0_CMPLD1 + const QTIMER4_T0_CMPLD2 + const QTIMER4_T1_CAPT + const QTIMER4_T1_CMPLD1 + const QTIMER4_T1_CMPLD2 + const QTIMER4_T2_CAPT + const QTIMER4_T2_CMPLD1 + const QTIMER4_T2_CMPLD2 + const QTIMER4_T3_CAPT + const QTIMER4_T3_CMPLD1 + const QTIMER4_T3_CMPLD2 + const Reserved + const SAI1_RX + const SAI1_TX + const SAI2_RX + const SAI2_TX + const SAI3_RX + const SAI3_TX + const SPDIF_RX + const SPDIF_TX + const Src + const XBAR1_REQ0 + const XBAR1_REQ1 + const XBAR1_REQ2 + const XBAR1_REQ3 + type Prio uint8 + type TCD struct + ATTR ATTR + CSR CSR + DADDR unsafe.Pointer + DLAST_SGA int + DOFF int16 + ELINK_BITER uint16 + ELINK_CITER uint16 + ML_NBYTES int + SADDR unsafe.Pointer + SLAST int + SOFF int16 + type TCDIO struct + ATTR mmio.R16[ATTR] + CSR mmio.R16[CSR] + DADDR mmio.P32 + DLAST_SGA mmio.R32[int32] + DOFF mmio.R16[int16] + ELINK_BITER mmio.R16[uint16] + ELINK_CITER mmio.R16[uint16] + ML_NBYTES mmio.R32[int32] + SADDR mmio.P32 + SLAST mmio.R32[int32] + SOFF mmio.R16[int16] v0.0.3 Sep 4, 2022 v0.0.2 Aug 30, 2022
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