Documentation
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Index ¶
Constants ¶
This section is empty.
Variables ¶
This section is empty.
Functions ¶
func GNUSyntax ¶
GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. This form typically matches the syntax defined in the Loong64 Reference Manual. See https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
func GoSyntax ¶
GoSyntax returns the Go assembler syntax for the instruction. The syntax was originally defined by Plan 9. The pc is the program counter of the instruction, used for expanding PC-relative addresses into absolute ones. The symname function queries the symbol table for the program being disassembled. Given a target address it returns the name and base address of the symbol containing the target, if any; otherwise it returns "", 0.
Types ¶
type Args ¶
type Args [5]Arg
An Args holds the instruction arguments. If an instruction has fewer than 5 arguments, the final elements in the array are nil.
type Inst ¶
type Inst struct {
Op Op // Opcode mnemonic
Enc uint32 // Raw encoding bits.
Args Args // Instruction arguments, in Loong64 manual order.
}
An Inst is a single instruction.
type OffsetSimm ¶
func (OffsetSimm) String ¶
func (o OffsetSimm) String() string
type Op ¶
type Op uint16
An Op is an Loong64 opcode.
const ( ADDI_D Op ADDI_W ADDU16I_D ADD_D ADD_W ALSL_D ALSL_W ALSL_WU AMADD_B AMADD_D AMADD_DB_B AMADD_DB_D AMADD_DB_H AMADD_DB_W AMADD_H AMADD_W AMAND_D AMAND_DB_D AMAND_DB_W AMAND_W AMCAS_B AMCAS_D AMCAS_DB_B AMCAS_DB_D AMCAS_DB_H AMCAS_DB_W AMCAS_H AMCAS_W AMMAX_D AMMAX_DB_D AMMAX_DB_DU AMMAX_DB_W AMMAX_DB_WU AMMAX_DU AMMAX_W AMMAX_WU AMMIN_D AMMIN_DB_D AMMIN_DB_DU AMMIN_DB_W AMMIN_DB_WU AMMIN_DU AMMIN_W AMMIN_WU AMOR_D AMOR_DB_D AMOR_DB_W AMOR_W AMSWAP_B AMSWAP_D AMSWAP_DB_B AMSWAP_DB_D AMSWAP_DB_H AMSWAP_DB_W AMSWAP_H AMSWAP_W AMXOR_D AMXOR_DB_D AMXOR_DB_W AMXOR_W AND ANDI ANDN ASRTGT_D ASRTLE_D B BCEQZ BCNEZ BEQ BEQZ BGE BGEU BITREV_4B BITREV_8B BITREV_D BITREV_W BL BLT BLTU BNE BNEZ BREAK BSTRINS_D BSTRINS_W BSTRPICK_D BSTRPICK_W BYTEPICK_D BYTEPICK_W CACOP CLO_D CLO_W CLZ_D CLZ_W CPUCFG CRCC_W_B_W CRCC_W_D_W CRCC_W_H_W CRCC_W_W_W CRC_W_B_W CRC_W_D_W CRC_W_H_W CRC_W_W_W CSRRD CSRWR CSRXCHG CTO_D CTO_W CTZ_D CTZ_W DBAR DBCL DIV_D DIV_DU DIV_W DIV_WU ERTN EXT_W_B EXT_W_H FABS_D FABS_S FADD_D FADD_S FCLASS_D FCLASS_S FCMP_CAF_D FCMP_CAF_S FCMP_CEQ_D FCMP_CEQ_S FCMP_CLE_D FCMP_CLE_S FCMP_CLT_D FCMP_CLT_S FCMP_CNE_D FCMP_CNE_S FCMP_COR_D FCMP_COR_S FCMP_CUEQ_D FCMP_CUEQ_S FCMP_CULE_D FCMP_CULE_S FCMP_CULT_D FCMP_CULT_S FCMP_CUNE_D FCMP_CUNE_S FCMP_CUN_D FCMP_CUN_S FCMP_SAF_D FCMP_SAF_S FCMP_SEQ_D FCMP_SEQ_S FCMP_SLE_D FCMP_SLE_S FCMP_SLT_D FCMP_SLT_S FCMP_SNE_D FCMP_SNE_S FCMP_SOR_D FCMP_SOR_S FCMP_SUEQ_D FCMP_SUEQ_S FCMP_SULE_D FCMP_SULE_S FCMP_SULT_D FCMP_SULT_S FCMP_SUNE_D FCMP_SUNE_S FCMP_SUN_D FCMP_SUN_S FCOPYSIGN_D FCOPYSIGN_S FCVT_D_S FCVT_S_D FDIV_D FDIV_S FFINT_D_L FFINT_D_W FFINT_S_L FFINT_S_W FLDGT_D FLDGT_S FLDLE_D FLDLE_S FLDX_D FLDX_S FLD_D FLD_S FLOGB_D FLOGB_S FMADD_D FMADD_S FMAXA_D FMAXA_S FMAX_D FMAX_S FMINA_D FMINA_S FMIN_D FMIN_S FMOV_D FMOV_S FMSUB_D FMSUB_S FMUL_D FMUL_S FNEG_D FNEG_S FNMADD_D FNMADD_S FNMSUB_D FNMSUB_S FRECIPE_D FRECIPE_S FRECIP_D FRECIP_S FRINT_D FRINT_S FRSQRTE_D FRSQRTE_S FRSQRT_D FRSQRT_S FSCALEB_D FSCALEB_S FSEL FSQRT_D FSQRT_S FSTGT_D FSTGT_S FSTLE_D FSTLE_S FSTX_D FSTX_S FST_D FST_S FSUB_D FSUB_S FTINTRM_L_D FTINTRM_L_S FTINTRM_W_D FTINTRM_W_S FTINTRNE_L_D FTINTRNE_L_S FTINTRNE_W_D FTINTRNE_W_S FTINTRP_L_D FTINTRP_L_S FTINTRP_W_D FTINTRP_W_S FTINTRZ_L_D FTINTRZ_L_S FTINTRZ_W_D FTINTRZ_W_S FTINT_L_D FTINT_L_S FTINT_W_D FTINT_W_S IBAR IDLE INVTLB IOCSRRD_B IOCSRRD_D IOCSRRD_H IOCSRRD_W IOCSRWR_B IOCSRWR_D IOCSRWR_H IOCSRWR_W JIRL LDDIR LDGT_B LDGT_D LDGT_H LDGT_W LDLE_B LDLE_D LDLE_H LDLE_W LDPTE LDPTR_D LDPTR_W LDX_B LDX_BU LDX_D LDX_H LDX_HU LDX_W LDX_WU LD_B LD_BU LD_D LD_H LD_HU LD_W LD_WU LLACQ_D LLACQ_W LL_D LL_W LU12I_W LU32I_D LU52I_D MASKEQZ MASKNEZ MOD_D MOD_DU MOD_W MOD_WU MOVCF2FR MOVCF2GR MOVFCSR2GR MOVFR2CF MOVFR2GR_D MOVFR2GR_S MOVFRH2GR_S MOVGR2CF MOVGR2FCSR MOVGR2FRH_W MOVGR2FR_D MOVGR2FR_W MULH_D MULH_DU MULH_W MULH_WU MULW_D_W MULW_D_WU MUL_D MUL_W NOR OR ORI ORN PCADDI PCADDU12I PCADDU18I PCALAU12I PRELD PRELDX RDTIMEH_W RDTIMEL_W RDTIME_D REVB_2H REVB_2W REVB_4H REVB_D REVH_2W REVH_D ROTRI_D ROTRI_W ROTR_D ROTR_W SCREL_D SCREL_W SC_D SC_Q SC_W SLLI_D SLLI_W SLL_D SLL_W SLT SLTI SLTU SLTUI SRAI_D SRAI_W SRA_D SRA_W SRLI_D SRLI_W SRL_D SRL_W STGT_B STGT_D STGT_H STGT_W STLE_B STLE_D STLE_H STLE_W STPTR_D STPTR_W STX_B STX_D STX_H STX_W ST_B ST_D ST_H ST_W SUB_D SUB_W SYSCALL TLBCLR TLBFILL TLBFLUSH TLBRD TLBSRCH TLBWR XOR XORI )
type Reg ¶
type Reg uint16
A Reg is a single register. The zero value denotes R0, not the absence of a register.
const ( // General-purpose register R0 Reg = iota R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 // Float point register F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 )
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