The highest tagged major version is
README
¶
Akita Memory Model
This repository contains the definition and the implementation for memory system components.
Please check here For detailed documentation.
Documentation
¶
Index ¶
Constants ¶
const ( KB uint64 = 1 << (10 * iota) MB GB TB )
For capacity
Variables ¶
This section is empty.
Functions ¶
This section is empty.
Types ¶
type AccessReq ¶
AccessReq abstracts read and write requests that are sent to the cache modules or memory controllers.
type AddressConverter ¶
type AddressConverter interface {
ConvertExternalToInternal(external uint64) uint64
ConvertInternalToExternal(internal uint64) uint64
}
AddressConverter can translate the address between two domains
type DataReadyRsp ¶
type DataReadyRsp struct {
*akita.ReqBase
RespondTo string // The ID of the request it replies
Data []byte
}
A DataReadyRsp is the respond sent from the lower module to the higher module that carries the data loaded.
func NewDataReadyRsp ¶
func NewDataReadyRsp( time akita.VTimeInSec, src, dst akita.Port, respondTo string, ) *DataReadyRsp
NewDataReadyRsp creates a new DataReadyRsp
func (*DataReadyRsp) ByteSize ¶
func (r *DataReadyRsp) ByteSize() int
func (*DataReadyRsp) GetRespondTo ¶
func (r *DataReadyRsp) GetRespondTo() string
type DoneRsp ¶
A DoneRsp is a respond sent from the lower module to the higher module to mark a previous requests is completed successfully.
func NewDoneRsp ¶
NewDoneRsp creates a new DoneRsp
func (*DoneRsp) GetRespondTo ¶
type IdealMemController ¶
type IdealMemController struct {
*akita.ComponentBase
Storage *Storage
Freq akita.Freq
Latency int
Engine akita.Engine
AddressConverter AddressConverter
ToTop akita.Port
}
An IdealMemController is an Akita component that allows read and write
An IdealMemController always respond to the request in a fixed number of cycles. There is no limitation on the concurrency of this unit.
func NewIdealMemController ¶
func NewIdealMemController( name string, engine akita.Engine, capacity uint64, ) *IdealMemController
NewIdealMemController creates a new IdealMemController
func (*IdealMemController) Handle ¶
func (c *IdealMemController) Handle(e akita.Event) error
Handle defines how the IdealMemController handles event
func (*IdealMemController) NotifyPortFree ¶
func (c *IdealMemController) NotifyPortFree(now akita.VTimeInSec, port akita.Port)
NotifyPortFree of an IdealMemController does not do anything
func (*IdealMemController) NotifyRecv ¶
func (c *IdealMemController) NotifyRecv(now akita.VTimeInSec, port akita.Port)
NotifyRecv triggers the IdealMemController to retrieve requests from the port.
type InterleavingConverter ¶
type InterleavingConverter struct {
InterleavingSize uint64
TotalNumOfElements int
CurrentElementIndex int
Offset uint64
}
InterleavingConverter is an address converter that can converts the address from an continuous address space to interleaved addresses.
For example, DRAM is divided into multiple banks, the internal address of each bank starts from 0, while the global address is continuous. In this case, we can use the InterleavingConverter to convert the external addresses from/ to internal addresses.
func (InterleavingConverter) ConvertExternalToInternal ¶
func (c InterleavingConverter) ConvertExternalToInternal(external uint64) uint64
ConvertExternalToInternal converts from external address to internal address
func (InterleavingConverter) ConvertInternalToExternal ¶
func (c InterleavingConverter) ConvertInternalToExternal(internal uint64) uint64
ConvertInternalToExternal converts from internal address to external address
type InvalidDoneRsp ¶
func NewInvalidDoneRsp ¶
func NewInvalidDoneRsp( time akita.VTimeInSec, src, dst akita.Port, respondTo string, ) *InvalidDoneRsp
type InvalidReq ¶
func NewInvalidReq ¶
func NewInvalidReq( time akita.VTimeInSec, src, dst akita.Port, ) *InvalidReq
type ReadReq ¶
type ReadReq struct {
*akita.ReqBase
Address uint64
MemByteSize uint64
PID ca.PID
IsLastInWave bool
}
A ReadReq is a request sent to a memory controller to fetch data
func NewReadReq ¶
func NewReadReq( time akita.VTimeInSec, src, dst akita.Port, address uint64, byteSize uint64, ) *ReadReq
NewReadReq creates a ReadReq
func (*ReadReq) GetAddress ¶
GetAddress returns the address that the request is accessing
func (*ReadReq) GetByteSize ¶
type Storage ¶
A Storage keeps the data of the guest system.
A storage is an abstraction of all different type of storage including registers, main memory, and hard drives.
The storage implementation manages the storage in units. The unit can is similar to the concept of page in mmemory management. For the units that it not touched by Read and Write function, no memory will be allocated.
func NewStorage ¶
NewStorage creates a storage object with the specified capacity
type TraceInfo ¶
type TraceInfo struct {
Req akita.Req
When akita.VTimeInSec
What string
Where string
Address uint64
ByteSize uint64
Data []byte
}
TraceInfo stores the information to be potentially captured by memory trace
type WriteBuffer ¶ added in v1.1.6
type WriteBuffer interface {
Tick(now akita.VTimeInSec) bool
CanEnqueue() bool
Enqueue(write *WriteReq)
Query(read *ReadReq) *WriteReq
SetWriteCombineGranularity(size uint64)
}
WriteBuffer is a place where the write can be transferred in a later time.
func NewWriteBuffer ¶ added in v1.1.6
func NewWriteBuffer(capacity int, port akita.Port) WriteBuffer
NewWriteBuffer creates and returns a default write buffer
type WriteReq ¶
type WriteReq struct {
*akita.ReqBase
Address uint64
Data []byte
DirtyMask []bool
PID ca.PID
IsLastInWave bool
}
A WriteReq is a request sent to a memory controller to fetch data
func NewWriteReq ¶
NewWriteReq creates a new WriteReq
func (*WriteReq) GetAddress ¶
GetAddress returns the address that the request is accessing
func (*WriteReq) GetByteSize ¶
Source Files
¶
Directories
¶
| Path | Synopsis |
|---|---|
|
Package vm provides the models for address translations
|
Package vm provides the models for address translations |