dram

Documentation

Overview

Package dram defines detailed DRAM modeling.

Index

• type Builder
  • func MakeBuilder() Builder
  • func (b Builder) Build(name string) *MemController
  • func (b Builder) WithAdditionalTracer(t tracing.Tracer) Builder
  • func (b Builder) WithBurstLength(n int) Builder
  • func (b Builder) WithBusWidth(n int) Builder
  • func (b Builder) WithCommandQueueSize(n int) Builder
  • func (b Builder) WithDeviceWidth(n int) Builder
  • func (b Builder) WithEngine(engine sim.Engine) Builder
  • func (b Builder) WithFreq(freq sim.Freq) Builder
  • func (b Builder) WithGlobalStorage(s *mem.Storage) Builder
  • func (b Builder) WithInterleavingAddrConversion(interleaveGranularity uint64, numTotalUnit, currentUnitIndex int, ...) Builder
  • func (b Builder) WithNumBank(n int) Builder
  • func (b Builder) WithNumBankGroup(n int) Builder
  • func (b Builder) WithNumChannel(n int) Builder
  • func (b Builder) WithNumCol(n int) Builder
  • func (b Builder) WithNumRank(n int) Builder
  • func (b Builder) WithNumRow(n int) Builder
  • func (b Builder) WithProtocol(protocol Protocol) Builder
  • func (b Builder) WithRFC(cycle int) Builder
  • func (b Builder) WithRFCb(cycle int) Builder
  • func (b Builder) WithTAL(cycle int) Builder
  • func (b Builder) WithTCCDL(cycle int) Builder
  • func (b Builder) WithTCCDS(cycle int) Builder
  • func (b Builder) WithTCL(cycle int) Builder
  • func (b Builder) WithTCWL(cycle int) Builder
  • func (b Builder) WithTPPD(cycle int) Builder
  • func (b Builder) WithTRAS(cycle int) Builder
  • func (b Builder) WithTRCD(cycle int) Builder
  • func (b Builder) WithTRCDRD(cycle int) Builder
  • func (b Builder) WithTRCDWR(cycle int) Builder
  • func (b Builder) WithTREFI(cycle int) Builder
  • func (b Builder) WithTRP(cycle int) Builder
  • func (b Builder) WithTRRDL(cycle int) Builder
  • func (b Builder) WithTRRDS(cycle int) Builder
  • func (b Builder) WithTRTP(cycle int) Builder
  • func (b Builder) WithTRTRS(cycle int) Builder
  • func (b Builder) WithTWR(cycle int) Builder
  • func (b Builder) WithTWTRL(cycle int) Builder
  • func (b Builder) WithTWTRS(cycle int) Builder
  • func (b Builder) WithTransactionQueueSize(n int) Builder
• type MemController
  • func (c *MemController) Tick(now sim.VTimeInSec) (madeProgress bool)
• type Protocol

Types

type Builder

type Builder struct {
	// contains filtered or unexported fields
}

Builder can build new memory controllers.

func MakeBuilder

func MakeBuilder() Builder

MakeBuilder creates a builder with default configuration.

func (Builder) Build

func (b Builder) Build(name string) *MemController

Build builds a new MemController.

func (Builder) WithAdditionalTracer

func (b Builder) WithAdditionalTracer(t tracing.Tracer) Builder

WithAdditionalTracer adds one tracer to the memory controller and all the banks.

func (Builder) WithBurstLength

func (b Builder) WithBurstLength(n int) Builder

WithBurstLength sets the number of access (each access manipulates the amount of data that equals the bus width) that takes place as one group.

func (Builder) WithBusWidth

func (b Builder) WithBusWidth(n int) Builder

WithBusWidth sets the number of bits can be transferred out of the banks at the same time.

func (Builder) WithCommandQueueSize

func (b Builder) WithCommandQueueSize(n int) Builder

WithCommandQueueSize sets the number of command that each command queue can hold.

func (Builder) WithDeviceWidth

func (b Builder) WithDeviceWidth(n int) Builder

WithDeviceWidth sets the number of bit that a bank can deliver at the same time.

func (Builder) WithEngine

func (b Builder) WithEngine(engine sim.Engine) Builder

WithEngine sets the engine that the builder uses.

func (Builder) WithFreq

func (b Builder) WithFreq(freq sim.Freq) Builder

WithFreq sets the frequency of the builder.

func (Builder) WithGlobalStorage

func (b Builder) WithGlobalStorage(s *mem.Storage) Builder

WithGlobalStorage asks the DRAM to use a global storage instead of a local storage. Use this when you want to provide a unified storage for your whole simulation. The address of the storage is the global physical address.

func (Builder) WithInterleavingAddrConversion

func (b Builder) WithInterleavingAddrConversion(
	interleaveGranularity uint64,
	numTotalUnit, currentUnitIndex int,
	lowerBound, upperBound uint64,
) Builder

WithInterleavingAddrConversion sets the rule to convert the global physical address to the internal physical address.

For example, in a GPU that has 8 memory controllers. The addresses are interleaved across all the memory controllers at the page granularity. The current DRAM is the 3rd in the array of 8 memory controller. Also, there are 4 GPUs in total and each GPU has 4GB memory. The CPU also has 4GB memory, occupying the physical address from 0-4GB. The current GPU is the 2nd GPU. So the address range is from 8GB - 12GB. In this case, the use should call this function as `WithAddrConversion(4096, 8, 3, 8*mem.GB, 12*mem.GB)`.

If there is only cone memory controller in your simulation, this function should not be called and the global physical address is equivalent to the DRAM controller's internal physical address.

func (Builder) WithNumBank

func (b Builder) WithNumBank(n int) Builder

WithNumBank sets the number of banks in each bank group.

func (Builder) WithNumBankGroup

func (b Builder) WithNumBankGroup(n int) Builder

WithNumBankGroup sets the number of bank groups in each rank.

func (Builder) WithNumChannel

func (b Builder) WithNumChannel(n int) Builder

WithNumChannel sets the channels that the memory controller controls.

func (Builder) WithNumCol

func (b Builder) WithNumCol(n int) Builder

WithNumCol sets the number of columns in each DRAM array.

func (Builder) WithNumRank

func (b Builder) WithNumRank(n int) Builder

WithNumRank sets the number of ranks in each channel. Number of ranks is typically the last parameter to determine. Here is how you can calculate the number of ranks. Suppose your total memory capacity is B_{ctrl}, channel count N_{chn}, row count N_{row}, column count N_col, bus width W_b, device width W_d. You can calculate the bank size as B_b with B_b = N_{col} * N_{row} * W_d. The rank size can be calculated with B_r = B_b * N_b * N_{device_per_rank}, where N_{device_per_rank} can be calculated with N_{device_per_rank} = W_b/W_d. Finally, the number of ranks is N_r = B_{ctrl} / N_{chn} / B_r.

func (Builder) WithNumRow

func (b Builder) WithNumRow(n int) Builder

WithNumRow sets the number of rows in each DRAM array.

func (Builder) WithProtocol

func (b Builder) WithProtocol(protocol Protocol) Builder

WithProtocol sets the protocol of the memory controller.

func (Builder) WithRFC

func (b Builder) WithRFC(cycle int) Builder

WithRFC sets the refresh cycle time in cycles.

func (Builder) WithRFCb

func (b Builder) WithRFCb(cycle int) Builder

WithRFCb sets the refresh to activate bank latency in cycles.

func (Builder) WithTAL

func (b Builder) WithTAL(cycle int) Builder

WithTAL sets the additional latency to column access in cycles.

func (Builder) WithTCCDL

func (b Builder) WithTCCDL(cycle int) Builder

WithTCCDL sets the long column-to-column delay in cycles. The long delay describes accesses to banks in the same bank group.

func (Builder) WithTCCDS

func (b Builder) WithTCCDS(cycle int) Builder

WithTCCDS sets the short column-to-column delay in cycles. The long delay describes accesses to banks from different bank groups.

func (Builder) WithTCL

func (b Builder) WithTCL(cycle int) Builder

WithTCL sets the column access strobe latency in cycles

func (Builder) WithTCWL

func (b Builder) WithTCWL(cycle int) Builder

WithTCWL sets the column write strobe latency in cycles

func (Builder) WithTPPD

func (b Builder) WithTPPD(cycle int) Builder

WithTPPD sets the precharge to precharge delay in cycles.

func (Builder) WithTRAS

func (b Builder) WithTRAS(cycle int) Builder

WithTRAS sets the row access strobe latency in cycles.

func (Builder) WithTRCD

func (b Builder) WithTRCD(cycle int) Builder

WithTRCD sets the row-to-column delay in cycles.

func (Builder) WithTRCDRD

func (b Builder) WithTRCDRD(cycle int) Builder

WithTRCDRD sets the activate to read latency in cycles. It only works for GDDR DRAMs.

func (Builder) WithTRCDWR

func (b Builder) WithTRCDWR(cycle int) Builder

WithTRCDWR sets the activate to write latency in cycles. It only works for GDDR DRAMs.

func (Builder) WithTREFI

func (b Builder) WithTREFI(cycle int) Builder

WithTREFI sets the refresh interval in cycles.

func (Builder) WithTRP

func (b Builder) WithTRP(cycle int) Builder

WithTRP sets the row precharge latency in cycles.

func (Builder) WithTRRDL

func (b Builder) WithTRRDL(cycle int) Builder

WithTRRDL sets the long activate to activate latency in cycles. The long latency describes activating different banks from the same bank group.

func (Builder) WithTRRDS

func (b Builder) WithTRRDS(cycle int) Builder

WithTRRDS sets the short activate to activate latency in cycles. The short latency describes activating different banks from different bank groups.

func (Builder) WithTRTP

func (b Builder) WithTRTP(cycle int) Builder

WithTRTP sets the row-to-precharge latency in cycles.

func (Builder) WithTRTRS

func (b Builder) WithTRTRS(cycle int) Builder

WithTRTRS sets the rank-to-rank switching latency.

func (Builder) WithTWR

func (b Builder) WithTWR(cycle int) Builder

WithTWR sets the write recovery time in cycles.

func (Builder) WithTWTRL

func (b Builder) WithTWTRL(cycle int) Builder

WithTWTRL sets the long write-to-read latency in cycles. The long latency describes write and read to banks from the same bank group.

func (Builder) WithTWTRS

func (b Builder) WithTWTRS(cycle int) Builder

WithTWTRS sets the short write-to-read latency in cycles. The short latency describes write and read to banks from different bank groups.

func (Builder) WithTransactionQueueSize

func (b Builder) WithTransactionQueueSize(n int) Builder

WithTransactionQueueSize sets the number of transactions can be buffered before converting them into commands. Note that accesses that touches multiple access units (BusWidth/8*BurstLength bytes) may need to be split into multiple transactions.

type MemController

type MemController struct {
	*sim.TickingComponent
	// contains filtered or unexported fields
}

A MemController handles read and write requests.

func (*MemController) Tick

func (c *MemController) Tick(now sim.VTimeInSec) (madeProgress bool)

Tick updates memory controller's internal state.

type Protocol

type Protocol int

Protocol defines the category of the memory controller.

const (
	DDR3 Protocol = iota
	DDR4
	GDDR5
	GDDR5X
	GDDR6
	LPDDR
	LPDDR3
	LPDDR4
	HBM
	HBM2
	HMC
)

A list of all supported DRAM protocols.