mmap

Documentation

Overview

Package mmap provides base memory adresses for all peripherals.

Index

• Constants

Constants

const (
	FLASH_BASE     uintptr = 0x08000000 // FLASH(up to 1 MB) base address
	SRAM1_BASE     uintptr = 0x20000000 // SRAM1(up to 96 KB) base address
	PERIPH_BASE    uintptr = 0x40000000 // Peripheral base address
	FMC_BASE       uintptr = 0x60000000 // FMC base address
	SRAM2_BASE     uintptr = 0x10000000 // SRAM2(32 KB) base address
	QSPI_BASE      uintptr = 0x90000000 // QSPI memories accessible over AHB base address
	FMC_R_BASE     uintptr = 0xA0000000 // FMC  control registers base address
	QSPI_R_BASE    uintptr = 0xA0001000 // QUADSPI control registers base address
	SRAM1_BB_BASE  uintptr = 0x22000000 // SRAM1(96 KB) base address in the bit-band region
	PERIPH_BB_BASE uintptr = 0x42000000 // Peripheral base address in the bit-band region
	SRAM2_BB_BASE  uintptr = 0x12000000 // SRAM2(32 KB) base address in the bit-band region
	SRAM_BASE      uintptr = SRAM1_BASE
	SRAM_BB_BASE   uintptr = SRAM1_BB_BASE
	SRAM1_SIZE_MAX uintptr = 0x00018000 // maximum SRAM1 size (up to 96 KBytes)
	SRAM2_SIZE     uintptr = 0x00008000 // SRAM2 size (32 KBytes)
)

const (
	APB1PERIPH_BASE uintptr = PERIPH_BASE
	APB2PERIPH_BASE uintptr = PERIPH_BASE + 0x00010000
	AHB1PERIPH_BASE uintptr = PERIPH_BASE + 0x00020000
	AHB2PERIPH_BASE uintptr = PERIPH_BASE + 0x08000000
	FMC_BANK1       uintptr = FMC_BASE
	FMC_BANK1_1     uintptr = FMC_BANK1
	FMC_BANK1_2     uintptr = FMC_BANK1 + 0x04000000
	FMC_BANK1_3     uintptr = FMC_BANK1 + 0x08000000
	FMC_BANK1_4     uintptr = FMC_BANK1 + 0x0C000000
	FMC_BANK3       uintptr = FMC_BASE + 0x20000000
)

Peripheral memory map

const (
	TIM2_BASE    uintptr = APB1PERIPH_BASE + 0x0000
	TIM3_BASE    uintptr = APB1PERIPH_BASE + 0x0400
	TIM4_BASE    uintptr = APB1PERIPH_BASE + 0x0800
	TIM5_BASE    uintptr = APB1PERIPH_BASE + 0x0C00
	TIM6_BASE    uintptr = APB1PERIPH_BASE + 0x1000
	TIM7_BASE    uintptr = APB1PERIPH_BASE + 0x1400
	LCD_BASE     uintptr = APB1PERIPH_BASE + 0x2400
	RTC_BASE     uintptr = APB1PERIPH_BASE + 0x2800
	WWDG_BASE    uintptr = APB1PERIPH_BASE + 0x2C00
	IWDG_BASE    uintptr = APB1PERIPH_BASE + 0x3000
	SPI2_BASE    uintptr = APB1PERIPH_BASE + 0x3800
	SPI3_BASE    uintptr = APB1PERIPH_BASE + 0x3C00
	USART2_BASE  uintptr = APB1PERIPH_BASE + 0x4400
	USART3_BASE  uintptr = APB1PERIPH_BASE + 0x4800
	UART4_BASE   uintptr = APB1PERIPH_BASE + 0x4C00
	UART5_BASE   uintptr = APB1PERIPH_BASE + 0x5000
	I2C1_BASE    uintptr = APB1PERIPH_BASE + 0x5400
	I2C2_BASE    uintptr = APB1PERIPH_BASE + 0x5800
	I2C3_BASE    uintptr = APB1PERIPH_BASE + 0x5C00
	CAN1_BASE    uintptr = APB1PERIPH_BASE + 0x6400
	PWR_BASE     uintptr = APB1PERIPH_BASE + 0x7000
	DAC_BASE     uintptr = APB1PERIPH_BASE + 0x7400
	DAC1_BASE    uintptr = APB1PERIPH_BASE + 0x7400
	OPAMP_BASE   uintptr = APB1PERIPH_BASE + 0x7800
	OPAMP1_BASE  uintptr = APB1PERIPH_BASE + 0x7800
	OPAMP2_BASE  uintptr = APB1PERIPH_BASE + 0x7810
	LPTIM1_BASE  uintptr = APB1PERIPH_BASE + 0x7C00
	LPUART1_BASE uintptr = APB1PERIPH_BASE + 0x8000
	SWPMI1_BASE  uintptr = APB1PERIPH_BASE + 0x8800
	LPTIM2_BASE  uintptr = APB1PERIPH_BASE + 0x9400
)

APB1 peripherals

const (
	SYSCFG_BASE          uintptr = APB2PERIPH_BASE + 0x0000
	VREFBUF_BASE         uintptr = APB2PERIPH_BASE + 0x0030
	COMP1_BASE           uintptr = APB2PERIPH_BASE + 0x0200
	COMP2_BASE           uintptr = APB2PERIPH_BASE + 0x0204
	EXTI_BASE            uintptr = APB2PERIPH_BASE + 0x0400
	FIREWALL_BASE        uintptr = APB2PERIPH_BASE + 0x1C00
	SDMMC1_BASE          uintptr = APB2PERIPH_BASE + 0x2800
	TIM1_BASE            uintptr = APB2PERIPH_BASE + 0x2C00
	SPI1_BASE            uintptr = APB2PERIPH_BASE + 0x3000
	TIM8_BASE            uintptr = APB2PERIPH_BASE + 0x3400
	USART1_BASE          uintptr = APB2PERIPH_BASE + 0x3800
	TIM15_BASE           uintptr = APB2PERIPH_BASE + 0x4000
	TIM16_BASE           uintptr = APB2PERIPH_BASE + 0x4400
	TIM17_BASE           uintptr = APB2PERIPH_BASE + 0x4800
	SAI1_BASE            uintptr = APB2PERIPH_BASE + 0x5400
	SAI1_Block_A_BASE    uintptr = SAI1_BASE + 0x004
	SAI1_Block_B_BASE    uintptr = SAI1_BASE + 0x024
	SAI2_BASE            uintptr = APB2PERIPH_BASE + 0x5800
	SAI2_Block_A_BASE    uintptr = SAI2_BASE + 0x004
	SAI2_Block_B_BASE    uintptr = SAI2_BASE + 0x024
	DFSDM1_BASE          uintptr = APB2PERIPH_BASE + 0x6000
	DFSDM1_Channel0_BASE uintptr = DFSDM1_BASE + 0x00
	DFSDM1_Channel1_BASE uintptr = DFSDM1_BASE + 0x20
	DFSDM1_Channel2_BASE uintptr = DFSDM1_BASE + 0x40
	DFSDM1_Channel3_BASE uintptr = DFSDM1_BASE + 0x60
	DFSDM1_Channel4_BASE uintptr = DFSDM1_BASE + 0x80
	DFSDM1_Channel5_BASE uintptr = DFSDM1_BASE + 0xA0
	DFSDM1_Channel6_BASE uintptr = DFSDM1_BASE + 0xC0
	DFSDM1_Channel7_BASE uintptr = DFSDM1_BASE + 0xE0
	DFSDM1_Filter0_BASE  uintptr = DFSDM1_BASE + 0x100
	DFSDM1_Filter1_BASE  uintptr = DFSDM1_BASE + 0x180
	DFSDM1_Filter2_BASE  uintptr = DFSDM1_BASE + 0x200
	DFSDM1_Filter3_BASE  uintptr = DFSDM1_BASE + 0x280
)

APB2 peripherals

const (
	DMA1_BASE          uintptr = AHB1PERIPH_BASE
	DMA2_BASE          uintptr = AHB1PERIPH_BASE + 0x0400
	RCC_BASE           uintptr = AHB1PERIPH_BASE + 0x1000
	FLASH_R_BASE       uintptr = AHB1PERIPH_BASE + 0x2000
	CRC_BASE           uintptr = AHB1PERIPH_BASE + 0x3000
	TSC_BASE           uintptr = AHB1PERIPH_BASE + 0x4000
	DMA1_Channel1_BASE uintptr = DMA1_BASE + 0x0008
	DMA1_Channel2_BASE uintptr = DMA1_BASE + 0x001C
	DMA1_Channel3_BASE uintptr = DMA1_BASE + 0x0030
	DMA1_Channel4_BASE uintptr = DMA1_BASE + 0x0044
	DMA1_Channel5_BASE uintptr = DMA1_BASE + 0x0058
	DMA1_Channel6_BASE uintptr = DMA1_BASE + 0x006C
	DMA1_Channel7_BASE uintptr = DMA1_BASE + 0x0080
	DMA1_CSELR_BASE    uintptr = DMA1_BASE + 0x00A8
	DMA2_Channel1_BASE uintptr = DMA2_BASE + 0x0008
	DMA2_Channel2_BASE uintptr = DMA2_BASE + 0x001C
	DMA2_Channel3_BASE uintptr = DMA2_BASE + 0x0030
	DMA2_Channel4_BASE uintptr = DMA2_BASE + 0x0044
	DMA2_Channel5_BASE uintptr = DMA2_BASE + 0x0058
	DMA2_Channel6_BASE uintptr = DMA2_BASE + 0x006C
	DMA2_Channel7_BASE uintptr = DMA2_BASE + 0x0080
	DMA2_CSELR_BASE    uintptr = DMA2_BASE + 0x00A8
)

AHB1 peripherals

const (
	GPIOA_BASE         uintptr = AHB2PERIPH_BASE + 0x0000
	GPIOB_BASE         uintptr = AHB2PERIPH_BASE + 0x0400
	GPIOC_BASE         uintptr = AHB2PERIPH_BASE + 0x0800
	GPIOD_BASE         uintptr = AHB2PERIPH_BASE + 0x0C00
	GPIOE_BASE         uintptr = AHB2PERIPH_BASE + 0x1000
	GPIOF_BASE         uintptr = AHB2PERIPH_BASE + 0x1400
	GPIOG_BASE         uintptr = AHB2PERIPH_BASE + 0x1800
	GPIOH_BASE         uintptr = AHB2PERIPH_BASE + 0x1C00
	USBOTG_BASE        uintptr = AHB2PERIPH_BASE + 0x08000000
	ADC1_BASE          uintptr = AHB2PERIPH_BASE + 0x08040000
	ADC2_BASE          uintptr = AHB2PERIPH_BASE + 0x08040100
	ADC3_BASE          uintptr = AHB2PERIPH_BASE + 0x08040200
	ADC123_COMMON_BASE uintptr = AHB2PERIPH_BASE + 0x08040300
	RNG_BASE           uintptr = AHB2PERIPH_BASE + 0x08060800
)

AHB2 peripherals

const (
	FMC_Bank1_R_BASE  uintptr = FMC_R_BASE + 0x0000
	FMC_Bank1E_R_BASE uintptr = FMC_R_BASE + 0x0104
	FMC_Bank3_R_BASE  uintptr = FMC_R_BASE + 0x0080
	DBGMCU_BASE       uintptr = 0xE0042000
)

FMC Banks registers base address

const (
	USB_OTG_FS_PERIPH_BASE    uintptr = 0x50000000
	USB_OTG_GLOBAL_BASE       uintptr = 0x00000000
	USB_OTG_DEVICE_BASE       uintptr = 0x00000800
	USB_OTG_IN_ENDPOINT_BASE  uintptr = 0x00000900
	USB_OTG_OUT_ENDPOINT_BASE uintptr = 0x00000B00
	USB_OTG_EP_REG_SIZE       uintptr = 0x00000020
	USB_OTG_HOST_BASE         uintptr = 0x00000400
	USB_OTG_HOST_PORT_BASE    uintptr = 0x00000440
	USB_OTG_HOST_CHANNEL_BASE uintptr = 0x00000500
	USB_OTG_HOST_CHANNEL_SIZE uintptr = 0x00000020
	USB_OTG_PCGCCTL_BASE      uintptr = 0x00000E00
	USB_OTG_FIFO_BASE         uintptr = 0x00001000
	USB_OTG_FIFO_SIZE         uintptr = 0x00001000
	PACKAGE_BASE              uintptr = 0x1FFF7500 // Package data register base address
	UID_BASE                  uintptr = 0x1FFF7590 // Unique device ID register base address
	FLASHSIZE_BASE            uintptr = 0x1FFF75E0 // Flash size data register base address
)

USB registers base address