pwr

package
v0.0.0-...-168ccc2 Latest Latest
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This package is not in the latest version of its module.

 Go to latest Published: Dec 5, 2021 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package pwr provides interface to Power Control.

Peripheral: PWR_Periph Power Control. Instances: 

PWR  mmap.PWR_BASE

Registers: 

0x00 32  CR1  Power control register 1.
0x04 32  CSR1 Power control/status register 2.
0x08 32  CR2  Power control register 2.
0x0C 32  CSR2 Power control/status register 2.

Import: 

stm32/o/f746xx/mmap

Index

Constants

View Source 
const (
	LPDSn   = 0
	PDDSn   = 1
	CSBFn   = 3
	PVDEn   = 4
	PLSn    = 5
	DBPn    = 8
	FPDSn   = 9
	LPUDSn  = 10
	MRUDSn  = 11
	ADCDC1n = 13
	VOSn    = 14
	ODENn   = 16
	ODSWENn = 17
	UDENn   = 18
)
View Source 
const (
	WUIFn    = 0
	SBFn     = 1
	PVDOn    = 2
	BRRn     = 3
	EIWUPn   = 8
	BREn     = 9
	VOSRDYn  = 14
	ODRDYn   = 16
	ODSWRDYn = 17
	UDRDYn   = 18
)
View Source 
const (
	CWUPF1n = 0
	CWUPF2n = 1
	CWUPF3n = 2
	CWUPF4n = 3
	CWUPF5n = 4
	CWUPF6n = 5
	WUPP1n  = 8
	WUPP2n  = 9
	WUPP3n  = 10
	WUPP4n  = 11
	WUPP5n  = 12
	WUPP6n  = 13
)
View Source 
const (
	WUPF1n = 0
	WUPF2n = 1
	WUPF3n = 2
	WUPF4n = 3
	WUPF5n = 4
	WUPF6n = 5
	EWUP1n = 8
	EWUP2n = 9
	EWUP3n = 10
	EWUP4n = 11
	EWUP5n = 12
	EWUP6n = 13
)

Variables

View Source 
var PWR = (*PWR_Periph)(unsafe.Pointer(uintptr(mmap.PWR_BASE)))

Functions

This section is empty.

Types

type CR1 

type CR1 uint32
const (
	LPDS     CR1 = 0x01 << 0  //+ Low-Power Deepsleep.
	PDDS     CR1 = 0x01 << 1  //+ Power Down Deepsleep.
	CSBF     CR1 = 0x01 << 3  //+ Clear Standby Flag.
	PVDE     CR1 = 0x01 << 4  //+ Power Voltage Detector Enable.
	PLS      CR1 = 0x07 << 5  //+ PLS[2:0] bits (PVD Level Selection).
	PLS_0    CR1 = 0x01 << 5  //  Bit 0.
	PLS_1    CR1 = 0x02 << 5  //  Bit 1.
	PLS_2    CR1 = 0x04 << 5  //  Bit 2.
	PLS_LEV0 CR1 = 0x00 << 5  //  PVD level 0.
	PLS_LEV1 CR1 = 0x01 << 5  //  PVD level 1.
	PLS_LEV2 CR1 = 0x02 << 5  //  PVD level 2.
	PLS_LEV3 CR1 = 0x03 << 5  //  PVD level 3.
	PLS_LEV4 CR1 = 0x04 << 5  //  PVD level 4.
	PLS_LEV5 CR1 = 0x05 << 5  //  PVD level 5.
	PLS_LEV6 CR1 = 0x06 << 5  //  PVD level 6.
	PLS_LEV7 CR1 = 0x07 << 5  //  PVD level 7.
	DBP      CR1 = 0x01 << 8  //+ Disable Backup Domain write protection.
	FPDS     CR1 = 0x01 << 9  //+ Flash power down in Stop mode.
	LPUDS    CR1 = 0x01 << 10 //+ Low-power regulator in deepsleep under-drive mode.
	MRUDS    CR1 = 0x01 << 11 //+ Main regulator in deepsleep under-drive mode.
	ADCDC1   CR1 = 0x01 << 13 //+ Refer to AN4073 on how to use this bit.
	VOS      CR1 = 0x03 << 14 //+ VOS[1:0] bits (Regulator voltage scaling output selection).
	VOS_0    CR1 = 0x01 << 14 //  Bit 0.
	VOS_1    CR1 = 0x02 << 14 //  Bit 1.
	ODEN     CR1 = 0x01 << 16 //+ Over Drive enable.
	ODSWEN   CR1 = 0x01 << 17 //+ Over Drive switch enabled.
	UDEN     CR1 = 0x03 << 18 //+ Under Drive enable in stop mode.
	UDEN_0   CR1 = 0x01 << 18 //  Bit 0.
	UDEN_1   CR1 = 0x02 << 18 //  Bit 1.
)

func (CR1) Field 

func (b CR1) Field(mask CR1) int

func (CR1) J 

func (mask CR1) J(v int) CR1

type CR2 

type CR2 uint32
const (
	CWUPF1 CR2 = 0x01 << 0  //+ Clear Wakeup Pin Flag for PA0.
	CWUPF2 CR2 = 0x01 << 1  //+ Clear Wakeup Pin Flag for PA2.
	CWUPF3 CR2 = 0x01 << 2  //+ Clear Wakeup Pin Flag for PC1.
	CWUPF4 CR2 = 0x01 << 3  //+ Clear Wakeup Pin Flag for PC13.
	CWUPF5 CR2 = 0x01 << 4  //+ Clear Wakeup Pin Flag for PI8.
	CWUPF6 CR2 = 0x01 << 5  //+ Clear Wakeup Pin Flag for PI11.
	WUPP1  CR2 = 0x01 << 8  //+ Wakeup Pin Polarity bit for PA0.
	WUPP2  CR2 = 0x01 << 9  //+ Wakeup Pin Polarity bit for PA2.
	WUPP3  CR2 = 0x01 << 10 //+ Wakeup Pin Polarity bit for PC1.
	WUPP4  CR2 = 0x01 << 11 //+ Wakeup Pin Polarity bit for PC13.
	WUPP5  CR2 = 0x01 << 12 //+ Wakeup Pin Polarity bit for PI8.
	WUPP6  CR2 = 0x01 << 13 //+ Wakeup Pin Polarity bit for PI11.
)

func (CR2) Field 

func (b CR2) Field(mask CR2) int

func (CR2) J 

func (mask CR2) J(v int) CR2

type CSR1 

type CSR1 uint32
const (
	WUIF    CSR1 = 0x01 << 0  //+ Wake up internal Flag.
	SBF     CSR1 = 0x01 << 1  //+ Standby Flag.
	PVDO    CSR1 = 0x01 << 2  //+ PVD Output.
	BRR     CSR1 = 0x01 << 3  //+ Backup regulator ready.
	EIWUP   CSR1 = 0x01 << 8  //+ Enable internal wakeup.
	BRE     CSR1 = 0x01 << 9  //+ Backup regulator enable.
	VOSRDY  CSR1 = 0x01 << 14 //+ Regulator voltage scaling output selection ready.
	ODRDY   CSR1 = 0x01 << 16 //+ Over Drive generator ready.
	ODSWRDY CSR1 = 0x01 << 17 //+ Over Drive Switch ready.
	UDRDY   CSR1 = 0x03 << 18 //+ Under Drive ready.
)

func (CSR1) Field 

func (b CSR1) Field(mask CSR1) int

func (CSR1) J 

func (mask CSR1) J(v int) CSR1

type CSR2 

type CSR2 uint32
const (
	WUPF1 CSR2 = 0x01 << 0  //+ Wakeup Pin Flag for PA0.
	WUPF2 CSR2 = 0x01 << 1  //+ Wakeup Pin Flag for PA2.
	WUPF3 CSR2 = 0x01 << 2  //+ Wakeup Pin Flag for PC1.
	WUPF4 CSR2 = 0x01 << 3  //+ Wakeup Pin Flag for PC13.
	WUPF5 CSR2 = 0x01 << 4  //+ Wakeup Pin Flag for PI8.
	WUPF6 CSR2 = 0x01 << 5  //+ Wakeup Pin Flag for PI11.
	EWUP1 CSR2 = 0x01 << 8  //+ Enable Wakeup Pin PA0.
	EWUP2 CSR2 = 0x01 << 9  //+ Enable Wakeup Pin PA2.
	EWUP3 CSR2 = 0x01 << 10 //+ Enable Wakeup Pin PC1.
	EWUP4 CSR2 = 0x01 << 11 //+ Enable Wakeup Pin PC13.
	EWUP5 CSR2 = 0x01 << 12 //+ Enable Wakeup Pin PI8.
	EWUP6 CSR2 = 0x01 << 13 //+ Enable Wakeup Pin PI11.
)

func (CSR2) Field 

func (b CSR2) Field(mask CSR2) int

func (CSR2) J 

func (mask CSR2) J(v int) CSR2

type PWR_Periph 

type PWR_Periph struct {
	CR1  RCR1
	CSR1 RCSR1
	CR2  RCR2
	CSR2 RCSR2
}

func (*PWR_Periph) ADCDC1 

func (p *PWR_Periph) ADCDC1() RMCR1

func (*PWR_Periph) BRE 

func (p *PWR_Periph) BRE() RMCSR1

func (*PWR_Periph) BRR 

func (p *PWR_Periph) BRR() RMCSR1

func (*PWR_Periph) BaseAddr 

func (p *PWR_Periph) BaseAddr() uintptr

func (*PWR_Periph) CSBF 

func (p *PWR_Periph) CSBF() RMCR1

func (*PWR_Periph) CWUPF1 

func (p *PWR_Periph) CWUPF1() RMCR2

func (*PWR_Periph) CWUPF2 

func (p *PWR_Periph) CWUPF2() RMCR2

func (*PWR_Periph) CWUPF3 

func (p *PWR_Periph) CWUPF3() RMCR2

func (*PWR_Periph) CWUPF4 

func (p *PWR_Periph) CWUPF4() RMCR2

func (*PWR_Periph) CWUPF5 

func (p *PWR_Periph) CWUPF5() RMCR2

func (*PWR_Periph) CWUPF6 

func (p *PWR_Periph) CWUPF6() RMCR2

func (*PWR_Periph) DBP 

func (p *PWR_Periph) DBP() RMCR1

func (*PWR_Periph) EIWUP 

func (p *PWR_Periph) EIWUP() RMCSR1

func (*PWR_Periph) EWUP1 

func (p *PWR_Periph) EWUP1() RMCSR2

func (*PWR_Periph) EWUP2 

func (p *PWR_Periph) EWUP2() RMCSR2

func (*PWR_Periph) EWUP3 

func (p *PWR_Periph) EWUP3() RMCSR2

func (*PWR_Periph) EWUP4 

func (p *PWR_Periph) EWUP4() RMCSR2

func (*PWR_Periph) EWUP5 

func (p *PWR_Periph) EWUP5() RMCSR2

func (*PWR_Periph) EWUP6 

func (p *PWR_Periph) EWUP6() RMCSR2

func (*PWR_Periph) FPDS 

func (p *PWR_Periph) FPDS() RMCR1

func (*PWR_Periph) LPDS 

func (p *PWR_Periph) LPDS() RMCR1

func (*PWR_Periph) LPUDS 

func (p *PWR_Periph) LPUDS() RMCR1

func (*PWR_Periph) MRUDS 

func (p *PWR_Periph) MRUDS() RMCR1

func (*PWR_Periph) ODEN 

func (p *PWR_Periph) ODEN() RMCR1

func (*PWR_Periph) ODRDY 

func (p *PWR_Periph) ODRDY() RMCSR1

func (*PWR_Periph) ODSWEN 

func (p *PWR_Periph) ODSWEN() RMCR1

func (*PWR_Periph) ODSWRDY 

func (p *PWR_Periph) ODSWRDY() RMCSR1

func (*PWR_Periph) PDDS 

func (p *PWR_Periph) PDDS() RMCR1

func (*PWR_Periph) PLS 

func (p *PWR_Periph) PLS() RMCR1

func (*PWR_Periph) PVDE 

func (p *PWR_Periph) PVDE() RMCR1

func (*PWR_Periph) PVDO 

func (p *PWR_Periph) PVDO() RMCSR1

func (*PWR_Periph) SBF 

func (p *PWR_Periph) SBF() RMCSR1

func (*PWR_Periph) UDEN 

func (p *PWR_Periph) UDEN() RMCR1

func (*PWR_Periph) UDRDY 

func (p *PWR_Periph) UDRDY() RMCSR1

func (*PWR_Periph) VOS 

func (p *PWR_Periph) VOS() RMCR1

func (*PWR_Periph) VOSRDY 

func (p *PWR_Periph) VOSRDY() RMCSR1

func (*PWR_Periph) WUIF 

func (p *PWR_Periph) WUIF() RMCSR1

func (*PWR_Periph) WUPF1 

func (p *PWR_Periph) WUPF1() RMCSR2

func (*PWR_Periph) WUPF2 

func (p *PWR_Periph) WUPF2() RMCSR2

func (*PWR_Periph) WUPF3 

func (p *PWR_Periph) WUPF3() RMCSR2

func (*PWR_Periph) WUPF4 

func (p *PWR_Periph) WUPF4() RMCSR2

func (*PWR_Periph) WUPF5 

func (p *PWR_Periph) WUPF5() RMCSR2

func (*PWR_Periph) WUPF6 

func (p *PWR_Periph) WUPF6() RMCSR2

func (*PWR_Periph) WUPP1 

func (p *PWR_Periph) WUPP1() RMCR2

func (*PWR_Periph) WUPP2 

func (p *PWR_Periph) WUPP2() RMCR2

func (*PWR_Periph) WUPP3 

func (p *PWR_Periph) WUPP3() RMCR2

func (*PWR_Periph) WUPP4 

func (p *PWR_Periph) WUPP4() RMCR2

func (*PWR_Periph) WUPP5 

func (p *PWR_Periph) WUPP5() RMCR2

func (*PWR_Periph) WUPP6 

func (p *PWR_Periph) WUPP6() RMCR2

type RCR1 

type RCR1 struct{ mmio.U32 }

func (*RCR1) AtomicClearBits 

func (r *RCR1) AtomicClearBits(mask CR1)

func (*RCR1) AtomicSetBits 

func (r *RCR1) AtomicSetBits(mask CR1)

func (*RCR1) AtomicStoreBits 

func (r *RCR1) AtomicStoreBits(mask, b CR1)

func (*RCR1) Bits 

func (r *RCR1) Bits(mask CR1) CR1

func (*RCR1) ClearBits 

func (r *RCR1) ClearBits(mask CR1)

func (*RCR1) Load 

func (r *RCR1) Load() CR1

func (*RCR1) SetBits 

func (r *RCR1) SetBits(mask CR1)

func (*RCR1) Store 

func (r *RCR1) Store(b CR1)

func (*RCR1) StoreBits 

func (r *RCR1) StoreBits(mask, b CR1)

type RCR2 

type RCR2 struct{ mmio.U32 }

func (*RCR2) AtomicClearBits 

func (r *RCR2) AtomicClearBits(mask CR2)

func (*RCR2) AtomicSetBits 

func (r *RCR2) AtomicSetBits(mask CR2)

func (*RCR2) AtomicStoreBits 

func (r *RCR2) AtomicStoreBits(mask, b CR2)

func (*RCR2) Bits 

func (r *RCR2) Bits(mask CR2) CR2

func (*RCR2) ClearBits 

func (r *RCR2) ClearBits(mask CR2)

func (*RCR2) Load 

func (r *RCR2) Load() CR2

func (*RCR2) SetBits 

func (r *RCR2) SetBits(mask CR2)

func (*RCR2) Store 

func (r *RCR2) Store(b CR2)

func (*RCR2) StoreBits 

func (r *RCR2) StoreBits(mask, b CR2)

type RCSR1 

type RCSR1 struct{ mmio.U32 }

func (*RCSR1) AtomicClearBits 

func (r *RCSR1) AtomicClearBits(mask CSR1)

func (*RCSR1) AtomicSetBits 

func (r *RCSR1) AtomicSetBits(mask CSR1)

func (*RCSR1) AtomicStoreBits 

func (r *RCSR1) AtomicStoreBits(mask, b CSR1)

func (*RCSR1) Bits 

func (r *RCSR1) Bits(mask CSR1) CSR1

func (*RCSR1) ClearBits 

func (r *RCSR1) ClearBits(mask CSR1)

func (*RCSR1) Load 

func (r *RCSR1) Load() CSR1

func (*RCSR1) SetBits 

func (r *RCSR1) SetBits(mask CSR1)

func (*RCSR1) Store 

func (r *RCSR1) Store(b CSR1)

func (*RCSR1) StoreBits 

func (r *RCSR1) StoreBits(mask, b CSR1)

type RCSR2 

type RCSR2 struct{ mmio.U32 }

func (*RCSR2) AtomicClearBits 

func (r *RCSR2) AtomicClearBits(mask CSR2)

func (*RCSR2) AtomicSetBits 

func (r *RCSR2) AtomicSetBits(mask CSR2)

func (*RCSR2) AtomicStoreBits 

func (r *RCSR2) AtomicStoreBits(mask, b CSR2)

func (*RCSR2) Bits 

func (r *RCSR2) Bits(mask CSR2) CSR2

func (*RCSR2) ClearBits 

func (r *RCSR2) ClearBits(mask CSR2)

func (*RCSR2) Load 

func (r *RCSR2) Load() CSR2

func (*RCSR2) SetBits 

func (r *RCSR2) SetBits(mask CSR2)

func (*RCSR2) Store 

func (r *RCSR2) Store(b CSR2)

func (*RCSR2) StoreBits 

func (r *RCSR2) StoreBits(mask, b CSR2)

type RMCR1 

type RMCR1 struct{ mmio.UM32 }

func (RMCR1) Load 

func (rm RMCR1) Load() CR1

func (RMCR1) Store 

func (rm RMCR1) Store(b CR1)

type RMCR2 

type RMCR2 struct{ mmio.UM32 }

func (RMCR2) Load 

func (rm RMCR2) Load() CR2

func (RMCR2) Store 

func (rm RMCR2) Store(b CR2)

type RMCSR1 

type RMCSR1 struct{ mmio.UM32 }

func (RMCSR1) Load 

func (rm RMCSR1) Load() CSR1

func (RMCSR1) Store 

func (rm RMCSR1) Store(b CSR1)

type RMCSR2 

type RMCSR2 struct{ mmio.UM32 }

func (RMCSR2) Load 

func (rm RMCSR2) Load() CSR2

func (RMCSR2) Store 

func (rm RMCSR2) Store(b CSR2)

Source Files

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