pwr

package
v0.0.0-...-168ccc2 Latest Latest
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 Go to latest Published: Dec 5, 2021 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package pwr provides interface to Power Control.

Peripheral: PWR_Periph Power Control. Instances: 

PWR  mmap.PWR_BASE

Registers: 

0x00 32  CR  Power control register.
0x04 32  CSR Power control/status register.

Import: 

stm32/o/f411xe/mmap

Index

Constants

View Source 
const (
	LPDSn   = 0
	PDDSn   = 1
	CWUFn   = 2
	CSBFn   = 3
	PVDEn   = 4
	PLSn    = 5
	DBPn    = 8
	FPDSn   = 9
	LPLVDSn = 10
	MRLVDSn = 11
	ADCDC1n = 13
	VOSn    = 14
	FMSSRn  = 20
	FISSRn  = 21
)
View Source 
const (
	WUFn    = 0
	SBFn    = 1
	PVDOn   = 2
	BRRn    = 3
	EWUPn   = 8
	BREn    = 9
	VOSRDYn = 14
)

Variables

View Source 
var PWR = (*PWR_Periph)(unsafe.Pointer(uintptr(mmap.PWR_BASE)))

Functions

This section is empty.

Types

type CR 

type CR uint32
const (
	LPDS     CR = 0x01 << 0  //+ Low-Power Deepsleep.
	PDDS     CR = 0x01 << 1  //+ Power Down Deepsleep.
	CWUF     CR = 0x01 << 2  //+ Clear Wakeup Flag.
	CSBF     CR = 0x01 << 3  //+ Clear Standby Flag.
	PVDE     CR = 0x01 << 4  //+ Power Voltage Detector Enable.
	PLS      CR = 0x07 << 5  //+ PLS[2:0] bits (PVD Level Selection).
	PLS_LEV0 CR = 0x00 << 5  //  PVD level 0.
	PLS_LEV1 CR = 0x01 << 5  //  PVD level 1.
	PLS_LEV2 CR = 0x02 << 5  //  PVD level 2.
	PLS_LEV3 CR = 0x03 << 5  //  PVD level 3.
	PLS_LEV4 CR = 0x04 << 5  //  PVD level 4.
	PLS_LEV5 CR = 0x05 << 5  //  PVD level 5.
	PLS_LEV6 CR = 0x06 << 5  //  PVD level 6.
	PLS_LEV7 CR = 0x07 << 5  //  PVD level 7.
	DBP      CR = 0x01 << 8  //+ Disable Backup Domain write protection.
	FPDS     CR = 0x01 << 9  //+ Flash power down in Stop mode.
	LPLVDS   CR = 0x01 << 10 //+ Low Power Regulator Low Voltage in Deep Sleep mode.
	MRLVDS   CR = 0x01 << 11 //+ Main Regulator Low Voltage in Deep Sleep mode.
	ADCDC1   CR = 0x01 << 13 //+ Refer to AN4073 on how to use this bit.
	VOS      CR = 0x03 << 14 //+ VOS[1:0] bits (Regulator voltage scaling output selection).
	VOS_0    CR = 0x01 << 14 //  Bit 0.
	VOS_1    CR = 0x02 << 14 //  Bit 1.
	FMSSR    CR = 0x01 << 20 //+ Flash Memory Sleep System Run.
	FISSR    CR = 0x01 << 21 //+ Flash Interface Stop while System Run.
)

func (CR) Field 

func (b CR) Field(mask CR) int

func (CR) J 

func (mask CR) J(v int) CR

type CSR 

type CSR uint32
const (
	WUF    CSR = 0x01 << 0  //+ Wakeup Flag.
	SBF    CSR = 0x01 << 1  //+ Standby Flag.
	PVDO   CSR = 0x01 << 2  //+ PVD Output.
	BRR    CSR = 0x01 << 3  //+ Backup regulator ready.
	EWUP   CSR = 0x01 << 8  //+ Enable WKUP pin.
	BRE    CSR = 0x01 << 9  //+ Backup regulator enable.
	VOSRDY CSR = 0x01 << 14 //+ Regulator voltage scaling output selection ready.
)

func (CSR) Field 

func (b CSR) Field(mask CSR) int

func (CSR) J 

func (mask CSR) J(v int) CSR

type PWR_Periph 

type PWR_Periph struct {
	CR  RCR
	CSR RCSR
}

func (*PWR_Periph) ADCDC1 

func (p *PWR_Periph) ADCDC1() RMCR

func (*PWR_Periph) BRE 

func (p *PWR_Periph) BRE() RMCSR

func (*PWR_Periph) BRR 

func (p *PWR_Periph) BRR() RMCSR

func (*PWR_Periph) BaseAddr 

func (p *PWR_Periph) BaseAddr() uintptr

func (*PWR_Periph) CSBF 

func (p *PWR_Periph) CSBF() RMCR

func (*PWR_Periph) CWUF 

func (p *PWR_Periph) CWUF() RMCR

func (*PWR_Periph) DBP 

func (p *PWR_Periph) DBP() RMCR

func (*PWR_Periph) EWUP 

func (p *PWR_Periph) EWUP() RMCSR

func (*PWR_Periph) FISSR 

func (p *PWR_Periph) FISSR() RMCR

func (*PWR_Periph) FMSSR 

func (p *PWR_Periph) FMSSR() RMCR

func (*PWR_Periph) FPDS 

func (p *PWR_Periph) FPDS() RMCR

func (*PWR_Periph) LPDS 

func (p *PWR_Periph) LPDS() RMCR

func (*PWR_Periph) LPLVDS 

func (p *PWR_Periph) LPLVDS() RMCR

func (*PWR_Periph) MRLVDS 

func (p *PWR_Periph) MRLVDS() RMCR

func (*PWR_Periph) PDDS 

func (p *PWR_Periph) PDDS() RMCR

func (*PWR_Periph) PLS 

func (p *PWR_Periph) PLS() RMCR

func (*PWR_Periph) PVDE 

func (p *PWR_Periph) PVDE() RMCR

func (*PWR_Periph) PVDO 

func (p *PWR_Periph) PVDO() RMCSR

func (*PWR_Periph) SBF 

func (p *PWR_Periph) SBF() RMCSR

func (*PWR_Periph) VOS 

func (p *PWR_Periph) VOS() RMCR

func (*PWR_Periph) VOSRDY 

func (p *PWR_Periph) VOSRDY() RMCSR

func (*PWR_Periph) WUF 

func (p *PWR_Periph) WUF() RMCSR

type RCR 

type RCR struct{ mmio.U32 }

func (*RCR) AtomicClearBits 

func (r *RCR) AtomicClearBits(mask CR)

func (*RCR) AtomicSetBits 

func (r *RCR) AtomicSetBits(mask CR)

func (*RCR) AtomicStoreBits 

func (r *RCR) AtomicStoreBits(mask, b CR)

func (*RCR) Bits 

func (r *RCR) Bits(mask CR) CR

func (*RCR) ClearBits 

func (r *RCR) ClearBits(mask CR)

func (*RCR) Load 

func (r *RCR) Load() CR

func (*RCR) SetBits 

func (r *RCR) SetBits(mask CR)

func (*RCR) Store 

func (r *RCR) Store(b CR)

func (*RCR) StoreBits 

func (r *RCR) StoreBits(mask, b CR)

type RCSR 

type RCSR struct{ mmio.U32 }

func (*RCSR) AtomicClearBits 

func (r *RCSR) AtomicClearBits(mask CSR)

func (*RCSR) AtomicSetBits 

func (r *RCSR) AtomicSetBits(mask CSR)

func (*RCSR) AtomicStoreBits 

func (r *RCSR) AtomicStoreBits(mask, b CSR)

func (*RCSR) Bits 

func (r *RCSR) Bits(mask CSR) CSR

func (*RCSR) ClearBits 

func (r *RCSR) ClearBits(mask CSR)

func (*RCSR) Load 

func (r *RCSR) Load() CSR

func (*RCSR) SetBits 

func (r *RCSR) SetBits(mask CSR)

func (*RCSR) Store 

func (r *RCSR) Store(b CSR)

func (*RCSR) StoreBits 

func (r *RCSR) StoreBits(mask, b CSR)

type RMCR 

type RMCR struct{ mmio.UM32 }

func (RMCR) Load 

func (rm RMCR) Load() CR

func (RMCR) Store 

func (rm RMCR) Store(b CR)

type RMCSR 

type RMCSR struct{ mmio.UM32 }

func (RMCSR) Load 

func (rm RMCSR) Load() CSR

func (RMCSR) Store 

func (rm RMCSR) Store(b CSR)

Source Files

View all Source files

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