rcc

package
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 Go to latest Published: Dec 5, 2021 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package rcc provides interface to Reset and Clock Control.

Peripheral: RCC_Periph Reset and Clock Control. Instances: 

RCC  mmap.RCC_BASE

Registers: 

0x00 32  CR       Clock control register.
0x04 32  CFGR     Clock configuration register.
0x08 32  CIR      Clock interrupt register.
0x0C 32  APB2RSTR APB2 peripheral reset register.
0x10 32  APB1RSTR APB1 peripheral reset register.
0x14 32  AHBENR   AHB peripheral clock register.
0x18 32  APB2ENR  APB2 peripheral clock enable register.
0x1C 32  APB1ENR  APB1 peripheral clock enable register.
0x20 32  BDCR     Backup domain control register.
0x24 32  CSR      Clock control & status register.
0x28 32  AHBRSTR  AHB peripheral reset register.
0x2C 32  CFGR2    Clock configuration register 2.
0x30 32  CFGR3    Clock configuration register 3.

Import: 

stm32/o/f303xe/mmap

Index

Constants

View Source 
const (
	HSIONn   = 0
	HSIRDYn  = 1
	HSITRIMn = 3
	HSICALn  = 8
	HSEONn   = 16
	HSERDYn  = 17
	HSEBYPn  = 18
	CSSONn   = 19
	PLLONn   = 24
	PLLRDYn  = 25
)
View Source 
const (
	SWn       = 0
	SWSn      = 2
	HPREn     = 4
	PPRE1n    = 8
	PPRE2n    = 11
	PLLSRCn   = 15
	PLLXTPREn = 17
	PLLMULn   = 18
	USBPREn   = 22
	I2SSRCn   = 23
	MCOn      = 24
	MCOPREn   = 28
	PLLNODIVn = 31
)
View Source 
const (
	LSIRDYFn  = 0
	LSERDYFn  = 1
	HSIRDYFn  = 2
	HSERDYFn  = 3
	PLLRDYFn  = 4
	CSSFn     = 7
	LSIRDYIEn = 8
	LSERDYIEn = 9
	HSIRDYIEn = 10
	HSERDYIEn = 11
	PLLRDYIEn = 12
	LSIRDYCn  = 16
	LSERDYCn  = 17
	HSIRDYCn  = 18
	HSERDYCn  = 19
	PLLRDYCn  = 20
	CSSCn     = 23
)
View Source 
const (
	SYSCFGRSTn = 0
	TIM1RSTn   = 11
	SPI1RSTn   = 12
	TIM8RSTn   = 13
	USART1RSTn = 14
	SPI4RSTn   = 15
	TIM15RSTn  = 16
	TIM16RSTn  = 17
	TIM17RSTn  = 18
	TIM20RSTn  = 20
)
View Source 
const (
	TIM2RSTn   = 0
	TIM3RSTn   = 1
	TIM4RSTn   = 2
	TIM6RSTn   = 4
	TIM7RSTn   = 5
	WWDGRSTn   = 11
	SPI2RSTn   = 14
	SPI3RSTn   = 15
	USART2RSTn = 17
	USART3RSTn = 18
	UART4RSTn  = 19
	UART5RSTn  = 20
	I2C1RSTn   = 21
	I2C2RSTn   = 22
	USBRSTn    = 23
	CANRSTn    = 25
	PWRRSTn    = 28
	DAC1RSTn   = 29
	I2C3RSTn   = 30
)
View Source 
const (
	DMA1ENn  = 0
	DMA2ENn  = 1
	SRAMENn  = 2
	FLITFENn = 4
	FMCENn   = 5
	CRCENn   = 6
	GPIOHENn = 16
	GPIOAENn = 17
	GPIOBENn = 18
	GPIOCENn = 19
	GPIODENn = 20
	GPIOEENn = 21
	GPIOFENn = 22
	GPIOGENn = 23
	TSCENn   = 24
	ADC12ENn = 28
	ADC34ENn = 29
)
View Source 
const (
	SYSCFGENn = 0
	TIM1ENn   = 11
	SPI1ENn   = 12
	TIM8ENn   = 13
	USART1ENn = 14
	SPI4ENn   = 15
	TIM15ENn  = 16
	TIM16ENn  = 17
	TIM17ENn  = 18
	TIM20ENn  = 20
)
View Source 
const (
	TIM2ENn   = 0
	TIM3ENn   = 1
	TIM4ENn   = 2
	TIM6ENn   = 4
	TIM7ENn   = 5
	WWDGENn   = 11
	SPI2ENn   = 14
	SPI3ENn   = 15
	USART2ENn = 17
	USART3ENn = 18
	UART4ENn  = 19
	UART5ENn  = 20
	I2C1ENn   = 21
	I2C2ENn   = 22
	USBENn    = 23
	CANENn    = 25
	PWRENn    = 28
	DAC1ENn   = 29
	I2C3ENn   = 30
)
View Source 
const (
	LSEn    = 0
	LSEDRVn = 3
	RTCSELn = 8
	RTCENn  = 15
	BDRSTn  = 16
)
View Source 
const (
	LSIONn      = 0
	LSIRDYn     = 1
	V18PWRRSTFn = 23
	RMVFn       = 24
	OBLRSTFn    = 25
	PINRSTFn    = 26
	PORRSTFn    = 27
	SFTRSTFn    = 28
	IWDGRSTFn   = 29
	WWDGRSTFn   = 30
	LPWRRSTFn   = 31
)
View Source 
const (
	FMCRSTn   = 5
	GPIOHRSTn = 16
	GPIOARSTn = 17
	GPIOBRSTn = 18
	GPIOCRSTn = 19
	GPIODRSTn = 20
	GPIOERSTn = 21
	GPIOFRSTn = 22
	GPIOGRSTn = 23
	TSCRSTn   = 24
	ADC12RSTn = 28
	ADC34RSTn = 29
)
View Source 
const (
	PREDIVn   = 0
	ADCPRE12n = 4
	ADCPRE34n = 9
)
View Source 
const (
	USART1SWn = 0
	I2CSWn    = 4
	TIMSWn    = 8
	TIM2SWn   = 24
	TIM34SWn  = 25
	USART2SWn = 16
	USART3SWn = 18
	UART4SWn  = 20
	UART5SWn  = 22
)

Variables

View Source 
var RCC = (*RCC_Periph)(unsafe.Pointer(uintptr(mmap.RCC_BASE)))

Functions

This section is empty.

Types

type AHBENR 

type AHBENR uint32
const (
	DMA1EN  AHBENR = 0x01 << 0  //+ DMA1 clock enable.
	DMA2EN  AHBENR = 0x01 << 1  //+ DMA2 clock enable.
	SRAMEN  AHBENR = 0x01 << 2  //+ SRAM interface clock enable.
	FLITFEN AHBENR = 0x01 << 4  //+ FLITF clock enable.
	FMCEN   AHBENR = 0x01 << 5  //+ FMC clock enable.
	CRCEN   AHBENR = 0x01 << 6  //+ CRC clock enable.
	GPIOHEN AHBENR = 0x01 << 16 //+ GPIOH clock enable.
	GPIOAEN AHBENR = 0x01 << 17 //+ GPIOA clock enable.
	GPIOBEN AHBENR = 0x01 << 18 //+ GPIOB clock enable.
	GPIOCEN AHBENR = 0x01 << 19 //+ GPIOC clock enable.
	GPIODEN AHBENR = 0x01 << 20 //+ GPIOD clock enable.
	GPIOEEN AHBENR = 0x01 << 21 //+ GPIOE clock enable.
	GPIOFEN AHBENR = 0x01 << 22 //+ GPIOF clock enable.
	GPIOGEN AHBENR = 0x01 << 23 //+ GPIOG clock enable.
	TSCEN   AHBENR = 0x01 << 24 //+ TS clock enable.
	ADC12EN AHBENR = 0x01 << 28 //+ ADC1/ ADC2 clock enable.
	ADC34EN AHBENR = 0x01 << 29 //+ ADC3/ ADC4 clock enable.
)

func (AHBENR) Field 

func (b AHBENR) Field(mask AHBENR) int

func (AHBENR) J 

func (mask AHBENR) J(v int) AHBENR

type AHBRSTR 

type AHBRSTR uint32
const (
	FMCRST   AHBRSTR = 0x01 << 5  //+ FMC reset.
	GPIOHRST AHBRSTR = 0x01 << 16 //+ GPIOH reset.
	GPIOARST AHBRSTR = 0x01 << 17 //+ GPIOA reset.
	GPIOBRST AHBRSTR = 0x01 << 18 //+ GPIOB reset.
	GPIOCRST AHBRSTR = 0x01 << 19 //+ GPIOC reset.
	GPIODRST AHBRSTR = 0x01 << 20 //+ GPIOD reset.
	GPIOERST AHBRSTR = 0x01 << 21 //+ GPIOE reset.
	GPIOFRST AHBRSTR = 0x01 << 22 //+ GPIOF reset.
	GPIOGRST AHBRSTR = 0x01 << 23 //+ GPIOG reset.
	TSCRST   AHBRSTR = 0x01 << 24 //+ TSC reset.
	ADC12RST AHBRSTR = 0x01 << 28 //+ ADC1 & ADC2 reset.
	ADC34RST AHBRSTR = 0x01 << 29 //+ ADC3 & ADC4 reset.
)

func (AHBRSTR) Field 

func (b AHBRSTR) Field(mask AHBRSTR) int

func (AHBRSTR) J 

func (mask AHBRSTR) J(v int) AHBRSTR

type APB1ENR 

type APB1ENR uint32
const (
	TIM2EN   APB1ENR = 0x01 << 0  //+ Timer 2 clock enable.
	TIM3EN   APB1ENR = 0x01 << 1  //+ Timer 3 clock enable.
	TIM4EN   APB1ENR = 0x01 << 2  //+ Timer 4 clock enable.
	TIM6EN   APB1ENR = 0x01 << 4  //+ Timer 6 clock enable.
	TIM7EN   APB1ENR = 0x01 << 5  //+ Timer 7 clock enable.
	WWDGEN   APB1ENR = 0x01 << 11 //+ Window Watchdog clock enable.
	SPI2EN   APB1ENR = 0x01 << 14 //+ SPI2 clock enable.
	SPI3EN   APB1ENR = 0x01 << 15 //+ SPI3 clock enable.
	USART2EN APB1ENR = 0x01 << 17 //+ USART 2 clock enable.
	USART3EN APB1ENR = 0x01 << 18 //+ USART 3 clock enable.
	UART4EN  APB1ENR = 0x01 << 19 //+ UART 4 clock enable.
	UART5EN  APB1ENR = 0x01 << 20 //+ UART 5 clock enable.
	I2C1EN   APB1ENR = 0x01 << 21 //+ I2C 1 clock enable.
	I2C2EN   APB1ENR = 0x01 << 22 //+ I2C 2 clock enable.
	USBEN    APB1ENR = 0x01 << 23 //+ USB clock enable.
	CANEN    APB1ENR = 0x01 << 25 //+ CAN clock enable.
	PWREN    APB1ENR = 0x01 << 28 //+ PWR clock enable.
	DAC1EN   APB1ENR = 0x01 << 29 //+ DAC 1 clock enable.
	I2C3EN   APB1ENR = 0x01 << 30 //+ I2C 3 clock enable.
)

func (APB1ENR) Field 

func (b APB1ENR) Field(mask APB1ENR) int

func (APB1ENR) J 

func (mask APB1ENR) J(v int) APB1ENR

type APB1RSTR 

type APB1RSTR uint32
const (
	TIM2RST   APB1RSTR = 0x01 << 0  //+ Timer 2 reset.
	TIM3RST   APB1RSTR = 0x01 << 1  //+ Timer 3 reset.
	TIM4RST   APB1RSTR = 0x01 << 2  //+ Timer 4 reset.
	TIM6RST   APB1RSTR = 0x01 << 4  //+ Timer 6 reset.
	TIM7RST   APB1RSTR = 0x01 << 5  //+ Timer 7 reset.
	WWDGRST   APB1RSTR = 0x01 << 11 //+ Window Watchdog reset.
	SPI2RST   APB1RSTR = 0x01 << 14 //+ SPI2 reset.
	SPI3RST   APB1RSTR = 0x01 << 15 //+ SPI3 reset.
	USART2RST APB1RSTR = 0x01 << 17 //+ USART 2 reset.
	USART3RST APB1RSTR = 0x01 << 18 //+ USART 3 reset.
	UART4RST  APB1RSTR = 0x01 << 19 //+ UART 4 reset.
	UART5RST  APB1RSTR = 0x01 << 20 //+ UART 5 reset.
	I2C1RST   APB1RSTR = 0x01 << 21 //+ I2C 1 reset.
	I2C2RST   APB1RSTR = 0x01 << 22 //+ I2C 2 reset.
	USBRST    APB1RSTR = 0x01 << 23 //+ USB reset.
	CANRST    APB1RSTR = 0x01 << 25 //+ CAN reset.
	PWRRST    APB1RSTR = 0x01 << 28 //+ PWR reset.
	DAC1RST   APB1RSTR = 0x01 << 29 //+ DAC 1 reset.
	I2C3RST   APB1RSTR = 0x01 << 30 //+ I2C 3 reset.
)

func (APB1RSTR) Field 

func (b APB1RSTR) Field(mask APB1RSTR) int

func (APB1RSTR) J 

func (mask APB1RSTR) J(v int) APB1RSTR

type APB2ENR 

type APB2ENR uint32
const (
	SYSCFGEN APB2ENR = 0x01 << 0  //+ SYSCFG clock enable.
	TIM1EN   APB2ENR = 0x01 << 11 //+ TIM1 clock enable.
	SPI1EN   APB2ENR = 0x01 << 12 //+ SPI1 clock enable.
	TIM8EN   APB2ENR = 0x01 << 13 //+ TIM8 clock enable.
	USART1EN APB2ENR = 0x01 << 14 //+ USART1 clock enable.
	SPI4EN   APB2ENR = 0x01 << 15 //+ SPI4 clock enable.
	TIM15EN  APB2ENR = 0x01 << 16 //+ TIM15 clock enable.
	TIM16EN  APB2ENR = 0x01 << 17 //+ TIM16 clock enable.
	TIM17EN  APB2ENR = 0x01 << 18 //+ TIM17 clock enable.
	TIM20EN  APB2ENR = 0x01 << 20 //+ TIM20 clock enable.
)

func (APB2ENR) Field 

func (b APB2ENR) Field(mask APB2ENR) int

func (APB2ENR) J 

func (mask APB2ENR) J(v int) APB2ENR

type APB2RSTR 

type APB2RSTR uint32
const (
	SYSCFGRST APB2RSTR = 0x01 << 0  //+ SYSCFG reset.
	TIM1RST   APB2RSTR = 0x01 << 11 //+ TIM1 reset.
	SPI1RST   APB2RSTR = 0x01 << 12 //+ SPI1 reset.
	TIM8RST   APB2RSTR = 0x01 << 13 //+ TIM8 reset.
	USART1RST APB2RSTR = 0x01 << 14 //+ USART1 reset.
	SPI4RST   APB2RSTR = 0x01 << 15 //+ SPI4 reset.
	TIM15RST  APB2RSTR = 0x01 << 16 //+ TIM15 reset.
	TIM16RST  APB2RSTR = 0x01 << 17 //+ TIM16 reset.
	TIM17RST  APB2RSTR = 0x01 << 18 //+ TIM17 reset.
	TIM20RST  APB2RSTR = 0x01 << 20 //+ TIM20 reset.
)

func (APB2RSTR) Field 

func (b APB2RSTR) Field(mask APB2RSTR) int

func (APB2RSTR) J 

func (mask APB2RSTR) J(v int) APB2RSTR

type BDCR 

type BDCR uint32
const (
	LSE            BDCR = 0x07 << 0  //+ External Low Speed oscillator [2:0] bits.
	LSEON          BDCR = 0x01 << 0  //  External Low Speed oscillator enable.
	LSERDY         BDCR = 0x02 << 0  //  External Low Speed oscillator Ready.
	LSEBYP         BDCR = 0x04 << 0  //  External Low Speed oscillator Bypass.
	LSEDRV         BDCR = 0x03 << 3  //+ LSEDRV[1:0] bits (LSE Osc. drive capability).
	RTCSEL         BDCR = 0x03 << 8  //+ RTCSEL[1:0] bits (RTC clock source selection).
	RTCSEL_NOCLOCK BDCR = 0x00 << 8  //  No clock.
	RTCSEL_LSE     BDCR = 0x01 << 8  //  LSE oscillator clock used as RTC clock.
	RTCSEL_LSI     BDCR = 0x02 << 8  //  LSI oscillator clock used as RTC clock.
	RTCSEL_HSE     BDCR = 0x03 << 8  //  HSE oscillator clock divided by 32 used as RTC clock.
	RTCEN          BDCR = 0x01 << 15 //+ RTC clock enable.
	BDRST          BDCR = 0x01 << 16 //+ Backup domain software reset.
)

func (BDCR) Field 

func (b BDCR) Field(mask BDCR) int

func (BDCR) J 

func (mask BDCR) J(v int) BDCR

type CFGR 

type CFGR uint32
const (
	SW                       CFGR = 0x03 << 0  //+ SW[1:0] bits (System clock Switch).
	SW_HSI                   CFGR = 0x00 << 0  //  HSI selected as system clock.
	SW_HSE                   CFGR = 0x01 << 0  //  HSE selected as system clock.
	SW_PLL                   CFGR = 0x02 << 0  //  PLL selected as system clock.
	SWS                      CFGR = 0x03 << 2  //+ SWS[1:0] bits (System Clock Switch Status).
	SWS_HSI                  CFGR = 0x00 << 2  //  HSI oscillator used as system clock.
	SWS_HSE                  CFGR = 0x01 << 2  //  HSE oscillator used as system clock.
	SWS_PLL                  CFGR = 0x02 << 2  //  PLL used as system clock.
	HPRE                     CFGR = 0x0F << 4  //+ HPRE[3:0] bits (AHB prescaler).
	HPRE_DIV1                CFGR = 0x00 << 4  //  SYSCLK not divided.
	HPRE_DIV2                CFGR = 0x08 << 4  //  SYSCLK divided by 2.
	HPRE_DIV4                CFGR = 0x09 << 4  //  SYSCLK divided by 4.
	HPRE_DIV8                CFGR = 0x0A << 4  //  SYSCLK divided by 8.
	HPRE_DIV16               CFGR = 0x0B << 4  //  SYSCLK divided by 16.
	HPRE_DIV64               CFGR = 0x0C << 4  //  SYSCLK divided by 64.
	HPRE_DIV128              CFGR = 0x0D << 4  //  SYSCLK divided by 128.
	HPRE_DIV256              CFGR = 0x0E << 4  //  SYSCLK divided by 256.
	HPRE_DIV512              CFGR = 0x0F << 4  //  SYSCLK divided by 512.
	PPRE1                    CFGR = 0x07 << 8  //+ PRE1[2:0] bits (APB1 prescaler).
	PPRE1_DIV1               CFGR = 0x00 << 8  //  HCLK not divided.
	PPRE1_DIV2               CFGR = 0x04 << 8  //  HCLK divided by 2.
	PPRE1_DIV4               CFGR = 0x05 << 8  //  HCLK divided by 4.
	PPRE1_DIV8               CFGR = 0x06 << 8  //  HCLK divided by 8.
	PPRE1_DIV16              CFGR = 0x07 << 8  //  HCLK divided by 16.
	PPRE2                    CFGR = 0x07 << 11 //+ PRE2[2:0] bits (APB2 prescaler).
	PPRE2_DIV1               CFGR = 0x00 << 11 //  HCLK not divided.
	PPRE2_DIV2               CFGR = 0x04 << 11 //  HCLK divided by 2.
	PPRE2_DIV4               CFGR = 0x05 << 11 //  HCLK divided by 4.
	PPRE2_DIV8               CFGR = 0x06 << 11 //  HCLK divided by 8.
	PPRE2_DIV16              CFGR = 0x07 << 11 //  HCLK divided by 16.
	PLLSRC                   CFGR = 0x03 << 15 //+ PLL entry clock source.
	PLLSRC_HSI_PREDIV        CFGR = 0x01 << 15 //  HSI/PREDIV clock as PLL entry clock source.
	PLLSRC_HSE_PREDIV        CFGR = 0x02 << 15 //  HSE/PREDIV clock selected as PLL entry clock source.
	PLLXTPRE                 CFGR = 0x01 << 17 //+ HSE divider for PLL entry.
	PLLXTPRE_HSE_PREDIV_DIV1 CFGR = 0x00 << 17 //  HSE/PREDIV clock not divided for PLL entry.
	PLLXTPRE_HSE_PREDIV_DIV2 CFGR = 0x01 << 17 //  HSE/PREDIV clock divided by 2 for PLL entry.
	PLLMUL                   CFGR = 0x0F << 18 //+ PLLMUL[3:0] bits (PLL multiplication factor).
	PLLMUL2                  CFGR = 0x00 << 18 //  PLL input clock*2.
	PLLMUL3                  CFGR = 0x01 << 18 //  PLL input clock*3.
	PLLMUL4                  CFGR = 0x02 << 18 //  PLL input clock*4.
	PLLMUL5                  CFGR = 0x03 << 18 //  PLL input clock*5.
	PLLMUL6                  CFGR = 0x04 << 18 //  PLL input clock*6.
	PLLMUL7                  CFGR = 0x05 << 18 //  PLL input clock*7.
	PLLMUL8                  CFGR = 0x06 << 18 //  PLL input clock*8.
	PLLMUL9                  CFGR = 0x07 << 18 //  PLL input clock*9.
	PLLMUL10                 CFGR = 0x08 << 18 //  PLL input clock10.
	PLLMUL11                 CFGR = 0x09 << 18 //  PLL input clock*11.
	PLLMUL12                 CFGR = 0x0A << 18 //  PLL input clock*12.
	PLLMUL13                 CFGR = 0x0B << 18 //  PLL input clock*13.
	PLLMUL14                 CFGR = 0x0C << 18 //  PLL input clock*14.
	PLLMUL15                 CFGR = 0x0D << 18 //  PLL input clock*15.
	PLLMUL16                 CFGR = 0x0E << 18 //  PLL input clock*16.
	USBPRE                   CFGR = 0x01 << 22 //+ USB prescaler.
	USBPRE_DIV1_5            CFGR = 0x00 << 22 //  USB prescaler is PLL clock divided by 1.5.
	USBPRE_DIV1              CFGR = 0x01 << 22 //  USB prescaler is PLL clock divided by 1.
	I2SSRC                   CFGR = 0x01 << 23 //+ I2S external clock source selection.
	I2SSRC_SYSCLK            CFGR = 0x00 << 23 //  System clock selected as I2S clock source.
	I2SSRC_EXT               CFGR = 0x01 << 23 //  External clock selected as I2S clock source.
	MCO                      CFGR = 0x07 << 24 //+ MCO[2:0] bits (Microcontroller Clock Output).
	MCO_NOCLOCK              CFGR = 0x00 << 24 //  No clock.
	MCO_LSI                  CFGR = 0x02 << 24 //  LSI clock selected as MCO source.
	MCO_LSE                  CFGR = 0x03 << 24 //  LSE clock selected as MCO source.
	MCO_SYSCLK               CFGR = 0x04 << 24 //  System clock selected as MCO source.
	MCO_HSI                  CFGR = 0x05 << 24 //  HSI clock selected as MCO source.
	MCO_HSE                  CFGR = 0x06 << 24 //  HSE clock selected as MCO source.
	MCO_PLL                  CFGR = 0x07 << 24 //  PLL clock divided by 2 selected as MCO source.
	MCOPRE                   CFGR = 0x07 << 28 //+ MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler).
	MCOPRE_DIV1              CFGR = 0x00 << 28 //  MCO is divided by 1.
	MCOPRE_DIV2              CFGR = 0x01 << 28 //  MCO is divided by 2.
	MCOPRE_DIV4              CFGR = 0x02 << 28 //  MCO is divided by 4.
	MCOPRE_DIV8              CFGR = 0x03 << 28 //  MCO is divided by 8.
	MCOPRE_DIV16             CFGR = 0x04 << 28 //  MCO is divided by 16.
	MCOPRE_DIV32             CFGR = 0x05 << 28 //  MCO is divided by 32.
	MCOPRE_DIV64             CFGR = 0x06 << 28 //  MCO is divided by 64.
	MCOPRE_DIV128            CFGR = 0x07 << 28 //  MCO is divided by 128.
	PLLNODIV                 CFGR = 0x01 << 31 //+ Do not divide PLL to MCO.
)

func (CFGR) Field 

func (b CFGR) Field(mask CFGR) int

func (CFGR) J 

func (mask CFGR) J(v int) CFGR

type CFGR2 

type CFGR2 uint32
const (
	PREDIV          CFGR2 = 0x0F << 0 //+ PREDIV[3:0] bits.
	PREDIV_DIV1     CFGR2 = 0x00 << 0 //  PREDIV input clock not divided.
	PREDIV_DIV2     CFGR2 = 0x01 << 0 //  PREDIV input clock divided by 2.
	PREDIV_DIV3     CFGR2 = 0x02 << 0 //  PREDIV input clock divided by 3.
	PREDIV_DIV4     CFGR2 = 0x03 << 0 //  PREDIV input clock divided by 4.
	PREDIV_DIV5     CFGR2 = 0x04 << 0 //  PREDIV input clock divided by 5.
	PREDIV_DIV6     CFGR2 = 0x05 << 0 //  PREDIV input clock divided by 6.
	PREDIV_DIV7     CFGR2 = 0x06 << 0 //  PREDIV input clock divided by 7.
	PREDIV_DIV8     CFGR2 = 0x07 << 0 //  PREDIV input clock divided by 8.
	PREDIV_DIV9     CFGR2 = 0x08 << 0 //  PREDIV input clock divided by 9.
	PREDIV_DIV10    CFGR2 = 0x09 << 0 //  PREDIV input clock divided by 10.
	PREDIV_DIV11    CFGR2 = 0x0A << 0 //  PREDIV input clock divided by 11.
	PREDIV_DIV12    CFGR2 = 0x0B << 0 //  PREDIV input clock divided by 12.
	PREDIV_DIV13    CFGR2 = 0x0C << 0 //  PREDIV input clock divided by 13.
	PREDIV_DIV14    CFGR2 = 0x0D << 0 //  PREDIV input clock divided by 14.
	PREDIV_DIV15    CFGR2 = 0x0E << 0 //  PREDIV input clock divided by 15.
	PREDIV_DIV16    CFGR2 = 0x0F << 0 //  PREDIV input clock divided by 16.
	ADCPRE12        CFGR2 = 0x1F << 4 //+ ADCPRE12[8:4] bits.
	ADCPRE12_NO     CFGR2 = 0x00 << 4 //  ADC12 clock disabled, ADC12 can use AHB clock.
	ADCPRE12_DIV1   CFGR2 = 0x10 << 4 //  ADC12 PLL clock divided by 1.
	ADCPRE12_DIV2   CFGR2 = 0x11 << 4 //  ADC12 PLL clock divided by 2.
	ADCPRE12_DIV4   CFGR2 = 0x12 << 4 //  ADC12 PLL clock divided by 4.
	ADCPRE12_DIV6   CFGR2 = 0x13 << 4 //  ADC12 PLL clock divided by 6.
	ADCPRE12_DIV8   CFGR2 = 0x14 << 4 //  ADC12 PLL clock divided by 8.
	ADCPRE12_DIV10  CFGR2 = 0x15 << 4 //  ADC12 PLL clock divided by 10.
	ADCPRE12_DIV12  CFGR2 = 0x16 << 4 //  ADC12 PLL clock divided by 12.
	ADCPRE12_DIV16  CFGR2 = 0x17 << 4 //  ADC12 PLL clock divided by 16.
	ADCPRE12_DIV32  CFGR2 = 0x18 << 4 //  ADC12 PLL clock divided by 32.
	ADCPRE12_DIV64  CFGR2 = 0x19 << 4 //  ADC12 PLL clock divided by 64.
	ADCPRE12_DIV128 CFGR2 = 0x1A << 4 //  ADC12 PLL clock divided by 128.
	ADCPRE12_DIV256 CFGR2 = 0x1B << 4 //  ADC12 PLL clock divided by 256.
	ADCPRE34        CFGR2 = 0x1F << 9 //+ ADCPRE34[13:5] bits.
	ADCPRE34_NO     CFGR2 = 0x00 << 9 //  ADC34 clock disabled, ADC34 can use AHB clock.
	ADCPRE34_DIV1   CFGR2 = 0x10 << 9 //  ADC34 PLL clock divided by 1.
	ADCPRE34_DIV2   CFGR2 = 0x11 << 9 //  ADC34 PLL clock divided by 2.
	ADCPRE34_DIV4   CFGR2 = 0x12 << 9 //  ADC34 PLL clock divided by 4.
	ADCPRE34_DIV6   CFGR2 = 0x13 << 9 //  ADC34 PLL clock divided by 6.
	ADCPRE34_DIV8   CFGR2 = 0x14 << 9 //  ADC34 PLL clock divided by 8.
	ADCPRE34_DIV10  CFGR2 = 0x15 << 9 //  ADC34 PLL clock divided by 10.
	ADCPRE34_DIV12  CFGR2 = 0x16 << 9 //  ADC34 PLL clock divided by 12.
	ADCPRE34_DIV16  CFGR2 = 0x17 << 9 //  ADC34 PLL clock divided by 16.
	ADCPRE34_DIV32  CFGR2 = 0x18 << 9 //  ADC34 PLL clock divided by 32.
	ADCPRE34_DIV64  CFGR2 = 0x19 << 9 //  ADC34 PLL clock divided by 64.
	ADCPRE34_DIV128 CFGR2 = 0x1A << 9 //  ADC34 PLL clock divided by 128.
	ADCPRE34_DIV256 CFGR2 = 0x1B << 9 //  ADC34 PLL clock divided by 256.
)

func (CFGR2) Field 

func (b CFGR2) Field(mask CFGR2) int

func (CFGR2) J 

func (mask CFGR2) J(v int) CFGR2

type CFGR3 

type CFGR3 uint32
const (
	USART1SW        CFGR3 = 0x03 << 0  //+ USART1SW[1:0] bits.
	USART1SW_PCLK2  CFGR3 = 0x00 << 0  //  PCLK2 clock used as USART1 clock source.
	USART1SW_SYSCLK CFGR3 = 0x01 << 0  //  System clock selected as USART1 clock source.
	USART1SW_LSE    CFGR3 = 0x02 << 0  //  LSE oscillator clock used as USART1 clock source.
	USART1SW_HSI    CFGR3 = 0x03 << 0  //  HSI oscillator clock used as USART1 clock source.
	I2CSW           CFGR3 = 0x07 << 4  //+ I2CSW bits.
	I2C1SW          CFGR3 = 0x01 << 4  //  I2C1SW bits.
	I2C2SW          CFGR3 = 0x02 << 4  //  I2C2SW bits.
	I2C3SW          CFGR3 = 0x04 << 4  //  I2C3SW bits.
	I2C1SW_HSI      CFGR3 = 0x00 << 4  //  HSI oscillator clock used as I2C1 clock source.
	I2C1SW_SYSCLK   CFGR3 = 0x01 << 4  //  System clock selected as I2C1 clock source.
	I2C2SW_HSI      CFGR3 = 0x00 << 4  //  HSI oscillator clock used as I2C2 clock source.
	I2C2SW_SYSCLK   CFGR3 = 0x02 << 4  //  System clock selected as I2C2 clock source.
	I2C3SW_HSI      CFGR3 = 0x00 << 4  //  HSI oscillator clock used as I2C3 clock source.
	I2C3SW_SYSCLK   CFGR3 = 0x04 << 4  //  System clock selected as I2C3 clock source.
	TIMSW           CFGR3 = 0xAF << 8  //+ TIMSW bits.
	TIM1SW          CFGR3 = 0x01 << 8  //  TIM1SW bits.
	TIM8SW          CFGR3 = 0x02 << 8  //  TIM8SW bits.
	TIM15SW         CFGR3 = 0x04 << 8  //  TIM15SW bits.
	TIM16SW         CFGR3 = 0x08 << 8  //  TIM16SW bits.
	TIM17SW         CFGR3 = 0x20 << 8  //  TIM17SW bits.
	TIM20SW         CFGR3 = 0x80 << 8  //  TIM20SW bits.
	TIM2SW          CFGR3 = 0x01 << 24 //+ TIM2SW bits.
	TIM34SW         CFGR3 = 0x01 << 25 //+ TIM34SW bits.
	TIM1SW_PCLK2    CFGR3 = 0x00 << 25 //  PCLK2 used as TIM1 clock source.
	TIM1SW_PLL      CFGR3 = 0x01 << 8  //  PLL clock used as TIM1 clock source.
	TIM8SW_PCLK2    CFGR3 = 0x00 << 25 //  PCLK2 used as TIM8 clock source.
	TIM8SW_PLL      CFGR3 = 0x02 << 8  //  PLL clock used as TIM8 clock source.
	TIM15SW_PCLK2   CFGR3 = 0x00 << 25 //  PCLK2 used as TIM15 clock source.
	TIM15SW_PLL     CFGR3 = 0x04 << 8  //  PLL clock used as TIM15 clock source.
	TIM16SW_PCLK2   CFGR3 = 0x00 << 25 //  PCLK2 used as TIM16 clock source.
	TIM16SW_PLL     CFGR3 = 0x08 << 8  //  PLL clock used as TIM16 clock source.
	TIM17SW_PCLK2   CFGR3 = 0x00 << 25 //  PCLK2 used as TIM17 clock source.
	TIM17SW_PLL     CFGR3 = 0x20 << 8  //  PLL clock used as TIM17 clock source.
	TIM20SW_PCLK2   CFGR3 = 0x00 << 25 //  PCLK2 used as TIM20 clock source.
	TIM20SW_PLL     CFGR3 = 0x80 << 8  //  PLL clock used as TIM20 clock source.
	USART2SW        CFGR3 = 0x03 << 16 //+ USART2SW[1:0] bits.
	USART2SW_PCLK   CFGR3 = 0x00 << 16 //  PCLK1 clock used as USART2 clock source.
	USART2SW_SYSCLK CFGR3 = 0x01 << 16 //  System clock selected as USART2 clock source.
	USART2SW_LSE    CFGR3 = 0x02 << 16 //  LSE oscillator clock used as USART2 clock source.
	USART2SW_HSI    CFGR3 = 0x03 << 16 //  HSI oscillator clock used as USART2 clock source.
	USART3SW        CFGR3 = 0x03 << 18 //+ USART3SW[1:0] bits.
	USART3SW_PCLK   CFGR3 = 0x00 << 18 //  PCLK1 clock used as USART3 clock source.
	USART3SW_SYSCLK CFGR3 = 0x01 << 18 //  System clock selected as USART3 clock source.
	USART3SW_LSE    CFGR3 = 0x02 << 18 //  LSE oscillator clock used as USART3 clock source.
	USART3SW_HSI    CFGR3 = 0x03 << 18 //  HSI oscillator clock used as USART3 clock source.
	UART4SW         CFGR3 = 0x03 << 20 //+ UART4SW[1:0] bits.
	UART4SW_PCLK    CFGR3 = 0x00 << 20 //  PCLK1 clock used as UART4 clock source.
	UART4SW_SYSCLK  CFGR3 = 0x01 << 20 //  System clock selected as UART4 clock source.
	UART4SW_LSE     CFGR3 = 0x02 << 20 //  LSE oscillator clock used as UART4 clock source.
	UART4SW_HSI     CFGR3 = 0x03 << 20 //  HSI oscillator clock used as UART4 clock source.
	UART5SW         CFGR3 = 0x03 << 22 //+ UART5SW[1:0] bits.
	UART5SW_PCLK    CFGR3 = 0x00 << 22 //  PCLK1 clock used as UART5 clock source.
	UART5SW_SYSCLK  CFGR3 = 0x01 << 22 //  System clock selected as UART5 clock source.
	UART5SW_LSE     CFGR3 = 0x02 << 22 //  LSE oscillator clock used as UART5 clock source.
	UART5SW_HSI     CFGR3 = 0x03 << 22 //  HSI oscillator clock used as UART5 clock source.
	TIM2SW_PCLK1    CFGR3 = 0x00 << 22 //  PCLK1 used as TIM2 clock source.
	TIM2SW_PLL      CFGR3 = 0x01 << 24 //  PLL clock used as TIM2 clock source.
	TIM34SW_PCLK1   CFGR3 = 0x00 << 22 //  PCLK1 used as TIM3/TIM4 clock source.
	TIM34SW_PLL     CFGR3 = 0x01 << 25 //  PLL clock used as TIM3/TIM4 clock source.
)

func (CFGR3) Field 

func (b CFGR3) Field(mask CFGR3) int

func (CFGR3) J 

func (mask CFGR3) J(v int) CFGR3

type CIR 

type CIR uint32
const (
	LSIRDYF  CIR = 0x01 << 0  //+ LSI Ready Interrupt flag.
	LSERDYF  CIR = 0x01 << 1  //+ LSE Ready Interrupt flag.
	HSIRDYF  CIR = 0x01 << 2  //+ HSI Ready Interrupt flag.
	HSERDYF  CIR = 0x01 << 3  //+ HSE Ready Interrupt flag.
	PLLRDYF  CIR = 0x01 << 4  //+ PLL Ready Interrupt flag.
	CSSF     CIR = 0x01 << 7  //+ Clock Security System Interrupt flag.
	LSIRDYIE CIR = 0x01 << 8  //+ LSI Ready Interrupt Enable.
	LSERDYIE CIR = 0x01 << 9  //+ LSE Ready Interrupt Enable.
	HSIRDYIE CIR = 0x01 << 10 //+ HSI Ready Interrupt Enable.
	HSERDYIE CIR = 0x01 << 11 //+ HSE Ready Interrupt Enable.
	PLLRDYIE CIR = 0x01 << 12 //+ PLL Ready Interrupt Enable.
	LSIRDYC  CIR = 0x01 << 16 //+ LSI Ready Interrupt Clear.
	LSERDYC  CIR = 0x01 << 17 //+ LSE Ready Interrupt Clear.
	HSIRDYC  CIR = 0x01 << 18 //+ HSI Ready Interrupt Clear.
	HSERDYC  CIR = 0x01 << 19 //+ HSE Ready Interrupt Clear.
	PLLRDYC  CIR = 0x01 << 20 //+ PLL Ready Interrupt Clear.
	CSSC     CIR = 0x01 << 23 //+ Clock Security System Interrupt Clear.
)

func (CIR) Field 

func (b CIR) Field(mask CIR) int

func (CIR) J 

func (mask CIR) J(v int) CIR

type CR 

type CR uint32
const (
	HSION   CR = 0x01 << 0  //+
	HSIRDY  CR = 0x01 << 1  //+
	HSITRIM CR = 0x1F << 3  //+
	HSICAL  CR = 0xFF << 8  //+
	HSEON   CR = 0x01 << 16 //+
	HSERDY  CR = 0x01 << 17 //+
	HSEBYP  CR = 0x01 << 18 //+
	CSSON   CR = 0x01 << 19 //+
	PLLON   CR = 0x01 << 24 //+
	PLLRDY  CR = 0x01 << 25 //+
)

func (CR) Field 

func (b CR) Field(mask CR) int

func (CR) J 

func (mask CR) J(v int) CR

type CSR 

type CSR uint32
const (
	LSION      CSR = 0x01 << 0  //+ Internal Low Speed oscillator enable.
	LSIRDY     CSR = 0x01 << 1  //+ Internal Low Speed oscillator Ready.
	V18PWRRSTF CSR = 0x01 << 23 //+ V1.8 power domain reset flag.
	RMVF       CSR = 0x01 << 24 //+ Remove reset flag.
	OBLRSTF    CSR = 0x01 << 25 //+ OBL reset flag.
	PINRSTF    CSR = 0x01 << 26 //+ PIN reset flag.
	PORRSTF    CSR = 0x01 << 27 //+ POR/PDR reset flag.
	SFTRSTF    CSR = 0x01 << 28 //+ Software Reset flag.
	IWDGRSTF   CSR = 0x01 << 29 //+ Independent Watchdog reset flag.
	WWDGRSTF   CSR = 0x01 << 30 //+ Window watchdog reset flag.
	LPWRRSTF   CSR = 0x01 << 31 //+ Low-Power reset flag.
)

func (CSR) Field 

func (b CSR) Field(mask CSR) int

func (CSR) J 

func (mask CSR) J(v int) CSR

type RAHBENR 

type RAHBENR struct{ mmio.U32 }

func (*RAHBENR) AtomicClearBits 

func (r *RAHBENR) AtomicClearBits(mask AHBENR)

func (*RAHBENR) AtomicSetBits 

func (r *RAHBENR) AtomicSetBits(mask AHBENR)

func (*RAHBENR) AtomicStoreBits 

func (r *RAHBENR) AtomicStoreBits(mask, b AHBENR)

func (*RAHBENR) Bits 

func (r *RAHBENR) Bits(mask AHBENR) AHBENR

func (*RAHBENR) ClearBits 

func (r *RAHBENR) ClearBits(mask AHBENR)

func (*RAHBENR) Load 

func (r *RAHBENR) Load() AHBENR

func (*RAHBENR) SetBits 

func (r *RAHBENR) SetBits(mask AHBENR)

func (*RAHBENR) Store 

func (r *RAHBENR) Store(b AHBENR)

func (*RAHBENR) StoreBits 

func (r *RAHBENR) StoreBits(mask, b AHBENR)

type RAHBRSTR 

type RAHBRSTR struct{ mmio.U32 }

func (*RAHBRSTR) AtomicClearBits 

func (r *RAHBRSTR) AtomicClearBits(mask AHBRSTR)

func (*RAHBRSTR) AtomicSetBits 

func (r *RAHBRSTR) AtomicSetBits(mask AHBRSTR)

func (*RAHBRSTR) AtomicStoreBits 

func (r *RAHBRSTR) AtomicStoreBits(mask, b AHBRSTR)

func (*RAHBRSTR) Bits 

func (r *RAHBRSTR) Bits(mask AHBRSTR) AHBRSTR

func (*RAHBRSTR) ClearBits 

func (r *RAHBRSTR) ClearBits(mask AHBRSTR)

func (*RAHBRSTR) Load 

func (r *RAHBRSTR) Load() AHBRSTR

func (*RAHBRSTR) SetBits 

func (r *RAHBRSTR) SetBits(mask AHBRSTR)

func (*RAHBRSTR) Store 

func (r *RAHBRSTR) Store(b AHBRSTR)

func (*RAHBRSTR) StoreBits 

func (r *RAHBRSTR) StoreBits(mask, b AHBRSTR)

type RAPB1ENR 

type RAPB1ENR struct{ mmio.U32 }

func (*RAPB1ENR) AtomicClearBits 

func (r *RAPB1ENR) AtomicClearBits(mask APB1ENR)

func (*RAPB1ENR) AtomicSetBits 

func (r *RAPB1ENR) AtomicSetBits(mask APB1ENR)

func (*RAPB1ENR) AtomicStoreBits 

func (r *RAPB1ENR) AtomicStoreBits(mask, b APB1ENR)

func (*RAPB1ENR) Bits 

func (r *RAPB1ENR) Bits(mask APB1ENR) APB1ENR

func (*RAPB1ENR) ClearBits 

func (r *RAPB1ENR) ClearBits(mask APB1ENR)

func (*RAPB1ENR) Load 

func (r *RAPB1ENR) Load() APB1ENR

func (*RAPB1ENR) SetBits 

func (r *RAPB1ENR) SetBits(mask APB1ENR)

func (*RAPB1ENR) Store 

func (r *RAPB1ENR) Store(b APB1ENR)

func (*RAPB1ENR) StoreBits 

func (r *RAPB1ENR) StoreBits(mask, b APB1ENR)

type RAPB1RSTR 

type RAPB1RSTR struct{ mmio.U32 }

func (*RAPB1RSTR) AtomicClearBits 

func (r *RAPB1RSTR) AtomicClearBits(mask APB1RSTR)

func (*RAPB1RSTR) AtomicSetBits 

func (r *RAPB1RSTR) AtomicSetBits(mask APB1RSTR)

func (*RAPB1RSTR) AtomicStoreBits 

func (r *RAPB1RSTR) AtomicStoreBits(mask, b APB1RSTR)

func (*RAPB1RSTR) Bits 

func (r *RAPB1RSTR) Bits(mask APB1RSTR) APB1RSTR

func (*RAPB1RSTR) ClearBits 

func (r *RAPB1RSTR) ClearBits(mask APB1RSTR)

func (*RAPB1RSTR) Load 

func (r *RAPB1RSTR) Load() APB1RSTR

func (*RAPB1RSTR) SetBits 

func (r *RAPB1RSTR) SetBits(mask APB1RSTR)

func (*RAPB1RSTR) Store 

func (r *RAPB1RSTR) Store(b APB1RSTR)

func (*RAPB1RSTR) StoreBits 

func (r *RAPB1RSTR) StoreBits(mask, b APB1RSTR)

type RAPB2ENR 

type RAPB2ENR struct{ mmio.U32 }

func (*RAPB2ENR) AtomicClearBits 

func (r *RAPB2ENR) AtomicClearBits(mask APB2ENR)

func (*RAPB2ENR) AtomicSetBits 

func (r *RAPB2ENR) AtomicSetBits(mask APB2ENR)

func (*RAPB2ENR) AtomicStoreBits 

func (r *RAPB2ENR) AtomicStoreBits(mask, b APB2ENR)

func (*RAPB2ENR) Bits 

func (r *RAPB2ENR) Bits(mask APB2ENR) APB2ENR

func (*RAPB2ENR) ClearBits 

func (r *RAPB2ENR) ClearBits(mask APB2ENR)

func (*RAPB2ENR) Load 

func (r *RAPB2ENR) Load() APB2ENR

func (*RAPB2ENR) SetBits 

func (r *RAPB2ENR) SetBits(mask APB2ENR)

func (*RAPB2ENR) Store 

func (r *RAPB2ENR) Store(b APB2ENR)

func (*RAPB2ENR) StoreBits 

func (r *RAPB2ENR) StoreBits(mask, b APB2ENR)

type RAPB2RSTR 

type RAPB2RSTR struct{ mmio.U32 }

func (*RAPB2RSTR) AtomicClearBits 

func (r *RAPB2RSTR) AtomicClearBits(mask APB2RSTR)

func (*RAPB2RSTR) AtomicSetBits 

func (r *RAPB2RSTR) AtomicSetBits(mask APB2RSTR)

func (*RAPB2RSTR) AtomicStoreBits 

func (r *RAPB2RSTR) AtomicStoreBits(mask, b APB2RSTR)

func (*RAPB2RSTR) Bits 

func (r *RAPB2RSTR) Bits(mask APB2RSTR) APB2RSTR

func (*RAPB2RSTR) ClearBits 

func (r *RAPB2RSTR) ClearBits(mask APB2RSTR)

func (*RAPB2RSTR) Load 

func (r *RAPB2RSTR) Load() APB2RSTR

func (*RAPB2RSTR) SetBits 

func (r *RAPB2RSTR) SetBits(mask APB2RSTR)

func (*RAPB2RSTR) Store 

func (r *RAPB2RSTR) Store(b APB2RSTR)

func (*RAPB2RSTR) StoreBits 

func (r *RAPB2RSTR) StoreBits(mask, b APB2RSTR)

type RBDCR 

type RBDCR struct{ mmio.U32 }

func (*RBDCR) AtomicClearBits 

func (r *RBDCR) AtomicClearBits(mask BDCR)

func (*RBDCR) AtomicSetBits 

func (r *RBDCR) AtomicSetBits(mask BDCR)

func (*RBDCR) AtomicStoreBits 

func (r *RBDCR) AtomicStoreBits(mask, b BDCR)

func (*RBDCR) Bits 

func (r *RBDCR) Bits(mask BDCR) BDCR

func (*RBDCR) ClearBits 

func (r *RBDCR) ClearBits(mask BDCR)

func (*RBDCR) Load 

func (r *RBDCR) Load() BDCR

func (*RBDCR) SetBits 

func (r *RBDCR) SetBits(mask BDCR)

func (*RBDCR) Store 

func (r *RBDCR) Store(b BDCR)

func (*RBDCR) StoreBits 

func (r *RBDCR) StoreBits(mask, b BDCR)

type RCC_Periph 

type RCC_Periph struct {
	CR       RCR
	CFGR     RCFGR
	CIR      RCIR
	APB2RSTR RAPB2RSTR
	APB1RSTR RAPB1RSTR
	AHBENR   RAHBENR
	APB2ENR  RAPB2ENR
	APB1ENR  RAPB1ENR
	BDCR     RBDCR
	CSR      RCSR
	AHBRSTR  RAHBRSTR
	CFGR2    RCFGR2
	CFGR3    RCFGR3
}

func (*RCC_Periph) ADC12EN 

func (p *RCC_Periph) ADC12EN() RMAHBENR

func (*RCC_Periph) ADC12RST 

func (p *RCC_Periph) ADC12RST() RMAHBRSTR

func (*RCC_Periph) ADC34EN 

func (p *RCC_Periph) ADC34EN() RMAHBENR

func (*RCC_Periph) ADC34RST 

func (p *RCC_Periph) ADC34RST() RMAHBRSTR

func (*RCC_Periph) ADCPRE12 

func (p *RCC_Periph) ADCPRE12() RMCFGR2

func (*RCC_Periph) ADCPRE34 

func (p *RCC_Periph) ADCPRE34() RMCFGR2

func (*RCC_Periph) BDRST 

func (p *RCC_Periph) BDRST() RMBDCR

func (*RCC_Periph) BaseAddr 

func (p *RCC_Periph) BaseAddr() uintptr

func (*RCC_Periph) CANEN 

func (p *RCC_Periph) CANEN() RMAPB1ENR

func (*RCC_Periph) CANRST 

func (p *RCC_Periph) CANRST() RMAPB1RSTR

func (*RCC_Periph) CRCEN 

func (p *RCC_Periph) CRCEN() RMAHBENR

func (*RCC_Periph) CSSC 

func (p *RCC_Periph) CSSC() RMCIR

func (*RCC_Periph) CSSF 

func (p *RCC_Periph) CSSF() RMCIR

func (*RCC_Periph) CSSON 

func (p *RCC_Periph) CSSON() RMCR

func (*RCC_Periph) DAC1EN 

func (p *RCC_Periph) DAC1EN() RMAPB1ENR

func (*RCC_Periph) DAC1RST 

func (p *RCC_Periph) DAC1RST() RMAPB1RSTR

func (*RCC_Periph) DMA1EN 

func (p *RCC_Periph) DMA1EN() RMAHBENR

func (*RCC_Periph) DMA2EN 

func (p *RCC_Periph) DMA2EN() RMAHBENR

func (*RCC_Periph) FLITFEN 

func (p *RCC_Periph) FLITFEN() RMAHBENR

func (*RCC_Periph) FMCEN 

func (p *RCC_Periph) FMCEN() RMAHBENR

func (*RCC_Periph) FMCRST 

func (p *RCC_Periph) FMCRST() RMAHBRSTR

func (*RCC_Periph) GPIOAEN 

func (p *RCC_Periph) GPIOAEN() RMAHBENR

func (*RCC_Periph) GPIOARST 

func (p *RCC_Periph) GPIOARST() RMAHBRSTR

func (*RCC_Periph) GPIOBEN 

func (p *RCC_Periph) GPIOBEN() RMAHBENR

func (*RCC_Periph) GPIOBRST 

func (p *RCC_Periph) GPIOBRST() RMAHBRSTR

func (*RCC_Periph) GPIOCEN 

func (p *RCC_Periph) GPIOCEN() RMAHBENR

func (*RCC_Periph) GPIOCRST 

func (p *RCC_Periph) GPIOCRST() RMAHBRSTR

func (*RCC_Periph) GPIODEN 

func (p *RCC_Periph) GPIODEN() RMAHBENR

func (*RCC_Periph) GPIODRST 

func (p *RCC_Periph) GPIODRST() RMAHBRSTR

func (*RCC_Periph) GPIOEEN 

func (p *RCC_Periph) GPIOEEN() RMAHBENR

func (*RCC_Periph) GPIOERST 

func (p *RCC_Periph) GPIOERST() RMAHBRSTR

func (*RCC_Periph) GPIOFEN 

func (p *RCC_Periph) GPIOFEN() RMAHBENR

func (*RCC_Periph) GPIOFRST 

func (p *RCC_Periph) GPIOFRST() RMAHBRSTR

func (*RCC_Periph) GPIOGEN 

func (p *RCC_Periph) GPIOGEN() RMAHBENR

func (*RCC_Periph) GPIOGRST 

func (p *RCC_Periph) GPIOGRST() RMAHBRSTR

func (*RCC_Periph) GPIOHEN 

func (p *RCC_Periph) GPIOHEN() RMAHBENR

func (*RCC_Periph) GPIOHRST 

func (p *RCC_Periph) GPIOHRST() RMAHBRSTR

func (*RCC_Periph) HPRE 

func (p *RCC_Periph) HPRE() RMCFGR

func (*RCC_Periph) HSEBYP 

func (p *RCC_Periph) HSEBYP() RMCR

func (*RCC_Periph) HSEON 

func (p *RCC_Periph) HSEON() RMCR

func (*RCC_Periph) HSERDY 

func (p *RCC_Periph) HSERDY() RMCR

func (*RCC_Periph) HSERDYC 

func (p *RCC_Periph) HSERDYC() RMCIR

func (*RCC_Periph) HSERDYF 

func (p *RCC_Periph) HSERDYF() RMCIR

func (*RCC_Periph) HSERDYIE 

func (p *RCC_Periph) HSERDYIE() RMCIR

func (*RCC_Periph) HSICAL 

func (p *RCC_Periph) HSICAL() RMCR

func (*RCC_Periph) HSION 

func (p *RCC_Periph) HSION() RMCR

func (*RCC_Periph) HSIRDY 

func (p *RCC_Periph) HSIRDY() RMCR

func (*RCC_Periph) HSIRDYC 

func (p *RCC_Periph) HSIRDYC() RMCIR

func (*RCC_Periph) HSIRDYF 

func (p *RCC_Periph) HSIRDYF() RMCIR

func (*RCC_Periph) HSIRDYIE 

func (p *RCC_Periph) HSIRDYIE() RMCIR

func (*RCC_Periph) HSITRIM 

func (p *RCC_Periph) HSITRIM() RMCR

func (*RCC_Periph) I2C1EN 

func (p *RCC_Periph) I2C1EN() RMAPB1ENR

func (*RCC_Periph) I2C1RST 

func (p *RCC_Periph) I2C1RST() RMAPB1RSTR

func (*RCC_Periph) I2C2EN 

func (p *RCC_Periph) I2C2EN() RMAPB1ENR

func (*RCC_Periph) I2C2RST 

func (p *RCC_Periph) I2C2RST() RMAPB1RSTR

func (*RCC_Periph) I2C3EN 

func (p *RCC_Periph) I2C3EN() RMAPB1ENR

func (*RCC_Periph) I2C3RST 

func (p *RCC_Periph) I2C3RST() RMAPB1RSTR

func (*RCC_Periph) I2CSW 

func (p *RCC_Periph) I2CSW() RMCFGR3

func (*RCC_Periph) I2SSRC 

func (p *RCC_Periph) I2SSRC() RMCFGR

func (*RCC_Periph) IWDGRSTF 

func (p *RCC_Periph) IWDGRSTF() RMCSR

func (*RCC_Periph) LPWRRSTF 

func (p *RCC_Periph) LPWRRSTF() RMCSR

func (*RCC_Periph) LSE 

func (p *RCC_Periph) LSE() RMBDCR

func (*RCC_Periph) LSEDRV 

func (p *RCC_Periph) LSEDRV() RMBDCR

func (*RCC_Periph) LSERDYC 

func (p *RCC_Periph) LSERDYC() RMCIR

func (*RCC_Periph) LSERDYF 

func (p *RCC_Periph) LSERDYF() RMCIR

func (*RCC_Periph) LSERDYIE 

func (p *RCC_Periph) LSERDYIE() RMCIR

func (*RCC_Periph) LSION 

func (p *RCC_Periph) LSION() RMCSR

func (*RCC_Periph) LSIRDY 

func (p *RCC_Periph) LSIRDY() RMCSR

func (*RCC_Periph) LSIRDYC 

func (p *RCC_Periph) LSIRDYC() RMCIR

func (*RCC_Periph) LSIRDYF 

func (p *RCC_Periph) LSIRDYF() RMCIR

func (*RCC_Periph) LSIRDYIE 

func (p *RCC_Periph) LSIRDYIE() RMCIR

func (*RCC_Periph) MCO 

func (p *RCC_Periph) MCO() RMCFGR

func (*RCC_Periph) MCOPRE 

func (p *RCC_Periph) MCOPRE() RMCFGR

func (*RCC_Periph) OBLRSTF 

func (p *RCC_Periph) OBLRSTF() RMCSR

func (*RCC_Periph) PINRSTF 

func (p *RCC_Periph) PINRSTF() RMCSR

func (*RCC_Periph) PLLMUL 

func (p *RCC_Periph) PLLMUL() RMCFGR

func (*RCC_Periph) PLLNODIV 

func (p *RCC_Periph) PLLNODIV() RMCFGR

func (*RCC_Periph) PLLON 

func (p *RCC_Periph) PLLON() RMCR

func (*RCC_Periph) PLLRDY 

func (p *RCC_Periph) PLLRDY() RMCR

func (*RCC_Periph) PLLRDYC 

func (p *RCC_Periph) PLLRDYC() RMCIR

func (*RCC_Periph) PLLRDYF 

func (p *RCC_Periph) PLLRDYF() RMCIR

func (*RCC_Periph) PLLRDYIE 

func (p *RCC_Periph) PLLRDYIE() RMCIR

func (*RCC_Periph) PLLSRC 

func (p *RCC_Periph) PLLSRC() RMCFGR

func (*RCC_Periph) PLLXTPRE 

func (p *RCC_Periph) PLLXTPRE() RMCFGR

func (*RCC_Periph) PORRSTF 

func (p *RCC_Periph) PORRSTF() RMCSR

func (*RCC_Periph) PPRE1 

func (p *RCC_Periph) PPRE1() RMCFGR

func (*RCC_Periph) PPRE2 

func (p *RCC_Periph) PPRE2() RMCFGR

func (*RCC_Periph) PREDIV 

func (p *RCC_Periph) PREDIV() RMCFGR2

func (*RCC_Periph) PWREN 

func (p *RCC_Periph) PWREN() RMAPB1ENR

func (*RCC_Periph) PWRRST 

func (p *RCC_Periph) PWRRST() RMAPB1RSTR

func (*RCC_Periph) RMVF 

func (p *RCC_Periph) RMVF() RMCSR

func (*RCC_Periph) RTCEN 

func (p *RCC_Periph) RTCEN() RMBDCR

func (*RCC_Periph) RTCSEL 

func (p *RCC_Periph) RTCSEL() RMBDCR

func (*RCC_Periph) SFTRSTF 

func (p *RCC_Periph) SFTRSTF() RMCSR

func (*RCC_Periph) SPI1EN 

func (p *RCC_Periph) SPI1EN() RMAPB2ENR

func (*RCC_Periph) SPI1RST 

func (p *RCC_Periph) SPI1RST() RMAPB2RSTR

func (*RCC_Periph) SPI2EN 

func (p *RCC_Periph) SPI2EN() RMAPB1ENR

func (*RCC_Periph) SPI2RST 

func (p *RCC_Periph) SPI2RST() RMAPB1RSTR

func (*RCC_Periph) SPI3EN 

func (p *RCC_Periph) SPI3EN() RMAPB1ENR

func (*RCC_Periph) SPI3RST 

func (p *RCC_Periph) SPI3RST() RMAPB1RSTR

func (*RCC_Periph) SPI4EN 

func (p *RCC_Periph) SPI4EN() RMAPB2ENR

func (*RCC_Periph) SPI4RST 

func (p *RCC_Periph) SPI4RST() RMAPB2RSTR

func (*RCC_Periph) SRAMEN 

func (p *RCC_Periph) SRAMEN() RMAHBENR

func (*RCC_Periph) SW 

func (p *RCC_Periph) SW() RMCFGR

func (*RCC_Periph) SWS 

func (p *RCC_Periph) SWS() RMCFGR

func (*RCC_Periph) SYSCFGEN 

func (p *RCC_Periph) SYSCFGEN() RMAPB2ENR

func (*RCC_Periph) SYSCFGRST 

func (p *RCC_Periph) SYSCFGRST() RMAPB2RSTR

func (*RCC_Periph) TIM15EN 

func (p *RCC_Periph) TIM15EN() RMAPB2ENR

func (*RCC_Periph) TIM15RST 

func (p *RCC_Periph) TIM15RST() RMAPB2RSTR

func (*RCC_Periph) TIM16EN 

func (p *RCC_Periph) TIM16EN() RMAPB2ENR

func (*RCC_Periph) TIM16RST 

func (p *RCC_Periph) TIM16RST() RMAPB2RSTR

func (*RCC_Periph) TIM17EN 

func (p *RCC_Periph) TIM17EN() RMAPB2ENR

func (*RCC_Periph) TIM17RST 

func (p *RCC_Periph) TIM17RST() RMAPB2RSTR

func (*RCC_Periph) TIM1EN 

func (p *RCC_Periph) TIM1EN() RMAPB2ENR

func (*RCC_Periph) TIM1RST 

func (p *RCC_Periph) TIM1RST() RMAPB2RSTR

func (*RCC_Periph) TIM20EN 

func (p *RCC_Periph) TIM20EN() RMAPB2ENR

func (*RCC_Periph) TIM20RST 

func (p *RCC_Periph) TIM20RST() RMAPB2RSTR

func (*RCC_Periph) TIM2EN 

func (p *RCC_Periph) TIM2EN() RMAPB1ENR

func (*RCC_Periph) TIM2RST 

func (p *RCC_Periph) TIM2RST() RMAPB1RSTR

func (*RCC_Periph) TIM2SW 

func (p *RCC_Periph) TIM2SW() RMCFGR3

func (*RCC_Periph) TIM34SW 

func (p *RCC_Periph) TIM34SW() RMCFGR3

func (*RCC_Periph) TIM3EN 

func (p *RCC_Periph) TIM3EN() RMAPB1ENR

func (*RCC_Periph) TIM3RST 

func (p *RCC_Periph) TIM3RST() RMAPB1RSTR

func (*RCC_Periph) TIM4EN 

func (p *RCC_Periph) TIM4EN() RMAPB1ENR

func (*RCC_Periph) TIM4RST 

func (p *RCC_Periph) TIM4RST() RMAPB1RSTR

func (*RCC_Periph) TIM6EN 

func (p *RCC_Periph) TIM6EN() RMAPB1ENR

func (*RCC_Periph) TIM6RST 

func (p *RCC_Periph) TIM6RST() RMAPB1RSTR

func (*RCC_Periph) TIM7EN 

func (p *RCC_Periph) TIM7EN() RMAPB1ENR

func (*RCC_Periph) TIM7RST 

func (p *RCC_Periph) TIM7RST() RMAPB1RSTR

func (*RCC_Periph) TIM8EN 

func (p *RCC_Periph) TIM8EN() RMAPB2ENR

func (*RCC_Periph) TIM8RST 

func (p *RCC_Periph) TIM8RST() RMAPB2RSTR

func (*RCC_Periph) TIMSW 

func (p *RCC_Periph) TIMSW() RMCFGR3

func (*RCC_Periph) TSCEN 

func (p *RCC_Periph) TSCEN() RMAHBENR

func (*RCC_Periph) TSCRST 

func (p *RCC_Periph) TSCRST() RMAHBRSTR

func (*RCC_Periph) UART4EN 

func (p *RCC_Periph) UART4EN() RMAPB1ENR

func (*RCC_Periph) UART4RST 

func (p *RCC_Periph) UART4RST() RMAPB1RSTR

func (*RCC_Periph) UART4SW 

func (p *RCC_Periph) UART4SW() RMCFGR3

func (*RCC_Periph) UART5EN 

func (p *RCC_Periph) UART5EN() RMAPB1ENR

func (*RCC_Periph) UART5RST 

func (p *RCC_Periph) UART5RST() RMAPB1RSTR

func (*RCC_Periph) UART5SW 

func (p *RCC_Periph) UART5SW() RMCFGR3

func (*RCC_Periph) USART1EN 

func (p *RCC_Periph) USART1EN() RMAPB2ENR

func (*RCC_Periph) USART1RST 

func (p *RCC_Periph) USART1RST() RMAPB2RSTR

func (*RCC_Periph) USART1SW 

func (p *RCC_Periph) USART1SW() RMCFGR3

func (*RCC_Periph) USART2EN 

func (p *RCC_Periph) USART2EN() RMAPB1ENR

func (*RCC_Periph) USART2RST 

func (p *RCC_Periph) USART2RST() RMAPB1RSTR

func (*RCC_Periph) USART2SW 

func (p *RCC_Periph) USART2SW() RMCFGR3

func (*RCC_Periph) USART3EN 

func (p *RCC_Periph) USART3EN() RMAPB1ENR

func (*RCC_Periph) USART3RST 

func (p *RCC_Periph) USART3RST() RMAPB1RSTR

func (*RCC_Periph) USART3SW 

func (p *RCC_Periph) USART3SW() RMCFGR3

func (*RCC_Periph) USBEN 

func (p *RCC_Periph) USBEN() RMAPB1ENR

func (*RCC_Periph) USBPRE 

func (p *RCC_Periph) USBPRE() RMCFGR

func (*RCC_Periph) USBRST 

func (p *RCC_Periph) USBRST() RMAPB1RSTR

func (*RCC_Periph) V18PWRRSTF 

func (p *RCC_Periph) V18PWRRSTF() RMCSR

func (*RCC_Periph) WWDGEN 

func (p *RCC_Periph) WWDGEN() RMAPB1ENR

func (*RCC_Periph) WWDGRST 

func (p *RCC_Periph) WWDGRST() RMAPB1RSTR

func (*RCC_Periph) WWDGRSTF 

func (p *RCC_Periph) WWDGRSTF() RMCSR

type RCFGR 

type RCFGR struct{ mmio.U32 }

func (*RCFGR) AtomicClearBits 

func (r *RCFGR) AtomicClearBits(mask CFGR)

func (*RCFGR) AtomicSetBits 

func (r *RCFGR) AtomicSetBits(mask CFGR)

func (*RCFGR) AtomicStoreBits 

func (r *RCFGR) AtomicStoreBits(mask, b CFGR)

func (*RCFGR) Bits 

func (r *RCFGR) Bits(mask CFGR) CFGR

func (*RCFGR) ClearBits 

func (r *RCFGR) ClearBits(mask CFGR)

func (*RCFGR) Load 

func (r *RCFGR) Load() CFGR

func (*RCFGR) SetBits 

func (r *RCFGR) SetBits(mask CFGR)

func (*RCFGR) Store 

func (r *RCFGR) Store(b CFGR)

func (*RCFGR) StoreBits 

func (r *RCFGR) StoreBits(mask, b CFGR)

type RCFGR2 

type RCFGR2 struct{ mmio.U32 }

func (*RCFGR2) AtomicClearBits 

func (r *RCFGR2) AtomicClearBits(mask CFGR2)

func (*RCFGR2) AtomicSetBits 

func (r *RCFGR2) AtomicSetBits(mask CFGR2)

func (*RCFGR2) AtomicStoreBits 

func (r *RCFGR2) AtomicStoreBits(mask, b CFGR2)

func (*RCFGR2) Bits 

func (r *RCFGR2) Bits(mask CFGR2) CFGR2

func (*RCFGR2) ClearBits 

func (r *RCFGR2) ClearBits(mask CFGR2)

func (*RCFGR2) Load 

func (r *RCFGR2) Load() CFGR2

func (*RCFGR2) SetBits 

func (r *RCFGR2) SetBits(mask CFGR2)

func (*RCFGR2) Store 

func (r *RCFGR2) Store(b CFGR2)

func (*RCFGR2) StoreBits 

func (r *RCFGR2) StoreBits(mask, b CFGR2)

type RCFGR3 

type RCFGR3 struct{ mmio.U32 }

func (*RCFGR3) AtomicClearBits 

func (r *RCFGR3) AtomicClearBits(mask CFGR3)

func (*RCFGR3) AtomicSetBits 

func (r *RCFGR3) AtomicSetBits(mask CFGR3)

func (*RCFGR3) AtomicStoreBits 

func (r *RCFGR3) AtomicStoreBits(mask, b CFGR3)

func (*RCFGR3) Bits 

func (r *RCFGR3) Bits(mask CFGR3) CFGR3

func (*RCFGR3) ClearBits 

func (r *RCFGR3) ClearBits(mask CFGR3)

func (*RCFGR3) Load 

func (r *RCFGR3) Load() CFGR3

func (*RCFGR3) SetBits 

func (r *RCFGR3) SetBits(mask CFGR3)

func (*RCFGR3) Store 

func (r *RCFGR3) Store(b CFGR3)

func (*RCFGR3) StoreBits 

func (r *RCFGR3) StoreBits(mask, b CFGR3)

type RCIR 

type RCIR struct{ mmio.U32 }

func (*RCIR) AtomicClearBits 

func (r *RCIR) AtomicClearBits(mask CIR)

func (*RCIR) AtomicSetBits 

func (r *RCIR) AtomicSetBits(mask CIR)

func (*RCIR) AtomicStoreBits 

func (r *RCIR) AtomicStoreBits(mask, b CIR)

func (*RCIR) Bits 

func (r *RCIR) Bits(mask CIR) CIR

func (*RCIR) ClearBits 

func (r *RCIR) ClearBits(mask CIR)

func (*RCIR) Load 

func (r *RCIR) Load() CIR

func (*RCIR) SetBits 

func (r *RCIR) SetBits(mask CIR)

func (*RCIR) Store 

func (r *RCIR) Store(b CIR)

func (*RCIR) StoreBits 

func (r *RCIR) StoreBits(mask, b CIR)

type RCR 

type RCR struct{ mmio.U32 }

func (*RCR) AtomicClearBits 

func (r *RCR) AtomicClearBits(mask CR)

func (*RCR) AtomicSetBits 

func (r *RCR) AtomicSetBits(mask CR)

func (*RCR) AtomicStoreBits 

func (r *RCR) AtomicStoreBits(mask, b CR)

func (*RCR) Bits 

func (r *RCR) Bits(mask CR) CR

func (*RCR) ClearBits 

func (r *RCR) ClearBits(mask CR)

func (*RCR) Load 

func (r *RCR) Load() CR

func (*RCR) SetBits 

func (r *RCR) SetBits(mask CR)

func (*RCR) Store 

func (r *RCR) Store(b CR)

func (*RCR) StoreBits 

func (r *RCR) StoreBits(mask, b CR)

type RCSR 

type RCSR struct{ mmio.U32 }

func (*RCSR) AtomicClearBits 

func (r *RCSR) AtomicClearBits(mask CSR)

func (*RCSR) AtomicSetBits 

func (r *RCSR) AtomicSetBits(mask CSR)

func (*RCSR) AtomicStoreBits 

func (r *RCSR) AtomicStoreBits(mask, b CSR)

func (*RCSR) Bits 

func (r *RCSR) Bits(mask CSR) CSR

func (*RCSR) ClearBits 

func (r *RCSR) ClearBits(mask CSR)

func (*RCSR) Load 

func (r *RCSR) Load() CSR

func (*RCSR) SetBits 

func (r *RCSR) SetBits(mask CSR)

func (*RCSR) Store 

func (r *RCSR) Store(b CSR)

func (*RCSR) StoreBits 

func (r *RCSR) StoreBits(mask, b CSR)

type RMAHBENR 

type RMAHBENR struct{ mmio.UM32 }

func (RMAHBENR) Load 

func (rm RMAHBENR) Load() AHBENR

func (RMAHBENR) Store 

func (rm RMAHBENR) Store(b AHBENR)

type RMAHBRSTR 

type RMAHBRSTR struct{ mmio.UM32 }

func (RMAHBRSTR) Load 

func (rm RMAHBRSTR) Load() AHBRSTR

func (RMAHBRSTR) Store 

func (rm RMAHBRSTR) Store(b AHBRSTR)

type RMAPB1ENR 

type RMAPB1ENR struct{ mmio.UM32 }

func (RMAPB1ENR) Load 

func (rm RMAPB1ENR) Load() APB1ENR

func (RMAPB1ENR) Store 

func (rm RMAPB1ENR) Store(b APB1ENR)

type RMAPB1RSTR 

type RMAPB1RSTR struct{ mmio.UM32 }

func (RMAPB1RSTR) Load 

func (rm RMAPB1RSTR) Load() APB1RSTR

func (RMAPB1RSTR) Store 

func (rm RMAPB1RSTR) Store(b APB1RSTR)

type RMAPB2ENR 

type RMAPB2ENR struct{ mmio.UM32 }

func (RMAPB2ENR) Load 

func (rm RMAPB2ENR) Load() APB2ENR

func (RMAPB2ENR) Store 

func (rm RMAPB2ENR) Store(b APB2ENR)

type RMAPB2RSTR 

type RMAPB2RSTR struct{ mmio.UM32 }

func (RMAPB2RSTR) Load 

func (rm RMAPB2RSTR) Load() APB2RSTR

func (RMAPB2RSTR) Store 

func (rm RMAPB2RSTR) Store(b APB2RSTR)

type RMBDCR 

type RMBDCR struct{ mmio.UM32 }

func (RMBDCR) Load 

func (rm RMBDCR) Load() BDCR

func (RMBDCR) Store 

func (rm RMBDCR) Store(b BDCR)

type RMCFGR 

type RMCFGR struct{ mmio.UM32 }

func (RMCFGR) Load 

func (rm RMCFGR) Load() CFGR

func (RMCFGR) Store 

func (rm RMCFGR) Store(b CFGR)

type RMCFGR2 

type RMCFGR2 struct{ mmio.UM32 }

func (RMCFGR2) Load 

func (rm RMCFGR2) Load() CFGR2

func (RMCFGR2) Store 

func (rm RMCFGR2) Store(b CFGR2)

type RMCFGR3 

type RMCFGR3 struct{ mmio.UM32 }

func (RMCFGR3) Load 

func (rm RMCFGR3) Load() CFGR3

func (RMCFGR3) Store 

func (rm RMCFGR3) Store(b CFGR3)

type RMCIR 

type RMCIR struct{ mmio.UM32 }

func (RMCIR) Load 

func (rm RMCIR) Load() CIR

func (RMCIR) Store 

func (rm RMCIR) Store(b CIR)

type RMCR 

type RMCR struct{ mmio.UM32 }

func (RMCR) Load 

func (rm RMCR) Load() CR

func (RMCR) Store 

func (rm RMCR) Store(b CR)

type RMCSR 

type RMCSR struct{ mmio.UM32 }

func (RMCSR) Load 

func (rm RMCSR) Load() CSR

func (RMCSR) Store 

func (rm RMCSR) Store(b CSR)

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