mmap

Documentation

Overview

Package mmap provides base memory adresses for all peripherals.

Index

• Constants

Constants

const (
	FLASH_BASE      uintptr = 0x08000000 // FLASH base address in the alias region
	CCMDATARAM_BASE uintptr = 0x10000000 // CCM(core coupled memory) data RAM base address in the alias region
	SRAM_BASE       uintptr = 0x20000000 // SRAM base address in the alias region
	PERIPH_BASE     uintptr = 0x40000000 // Peripheral base address in the alias region
	FMC_BASE        uintptr = 0x60000000 // FMC base address
	FMC_R_BASE      uintptr = 0xA0000000 // FMC registers base address
	SRAM_BB_BASE    uintptr = 0x22000000 // SRAM base address in the bit-band region
	PERIPH_BB_BASE  uintptr = 0x42000000 // Peripheral base address in the bit-band region
)

const (
	APB1PERIPH_BASE uintptr = PERIPH_BASE
	APB2PERIPH_BASE uintptr = PERIPH_BASE + 0x00010000
	AHB1PERIPH_BASE uintptr = PERIPH_BASE + 0x00020000
	AHB2PERIPH_BASE uintptr = PERIPH_BASE + 0x08000000
	AHB3PERIPH_BASE uintptr = PERIPH_BASE + 0x10000000
)

Peripheral memory map

const (
	TIM2_BASE    uintptr = APB1PERIPH_BASE + 0x00000000
	TIM3_BASE    uintptr = APB1PERIPH_BASE + 0x00000400
	TIM4_BASE    uintptr = APB1PERIPH_BASE + 0x00000800
	TIM6_BASE    uintptr = APB1PERIPH_BASE + 0x00001000
	TIM7_BASE    uintptr = APB1PERIPH_BASE + 0x00001400
	RTC_BASE     uintptr = APB1PERIPH_BASE + 0x00002800
	WWDG_BASE    uintptr = APB1PERIPH_BASE + 0x00002C00
	IWDG_BASE    uintptr = APB1PERIPH_BASE + 0x00003000
	I2S2ext_BASE uintptr = APB1PERIPH_BASE + 0x00003400
	SPI2_BASE    uintptr = APB1PERIPH_BASE + 0x00003800
	SPI3_BASE    uintptr = APB1PERIPH_BASE + 0x00003C00
	I2S3ext_BASE uintptr = APB1PERIPH_BASE + 0x00004000
	USART2_BASE  uintptr = APB1PERIPH_BASE + 0x00004400
	USART3_BASE  uintptr = APB1PERIPH_BASE + 0x00004800
	UART4_BASE   uintptr = APB1PERIPH_BASE + 0x00004C00
	UART5_BASE   uintptr = APB1PERIPH_BASE + 0x00005000
	I2C1_BASE    uintptr = APB1PERIPH_BASE + 0x00005400
	I2C2_BASE    uintptr = APB1PERIPH_BASE + 0x00005800
	USB_BASE     uintptr = APB1PERIPH_BASE + 0x00005C00 // USB_IP Peripheral Registers base address
	USB_PMAADDR  uintptr = APB1PERIPH_BASE + 0x00006000 // USB_IP Packet Memory Area base address
	CAN_BASE     uintptr = APB1PERIPH_BASE + 0x00006400
	PWR_BASE     uintptr = APB1PERIPH_BASE + 0x00007000
	DAC1_BASE    uintptr = APB1PERIPH_BASE + 0x00007400
	DAC_BASE     uintptr = DAC1_BASE
	I2C3_BASE    uintptr = APB1PERIPH_BASE + 0x00007800
)

APB1 peripherals

const (
	SYSCFG_BASE uintptr = APB2PERIPH_BASE + 0x00000000
	COMP1_BASE  uintptr = APB2PERIPH_BASE + 0x0000001C
	COMP2_BASE  uintptr = APB2PERIPH_BASE + 0x00000020
	COMP3_BASE  uintptr = APB2PERIPH_BASE + 0x00000024
	COMP4_BASE  uintptr = APB2PERIPH_BASE + 0x00000028
	COMP5_BASE  uintptr = APB2PERIPH_BASE + 0x0000002C
	COMP6_BASE  uintptr = APB2PERIPH_BASE + 0x00000030
	COMP7_BASE  uintptr = APB2PERIPH_BASE + 0x00000034
	COMP_BASE   uintptr = COMP1_BASE
	OPAMP1_BASE uintptr = APB2PERIPH_BASE + 0x00000038
	OPAMP2_BASE uintptr = APB2PERIPH_BASE + 0x0000003C
	OPAMP3_BASE uintptr = APB2PERIPH_BASE + 0x00000040
	OPAMP4_BASE uintptr = APB2PERIPH_BASE + 0x00000044
	OPAMP_BASE  uintptr = OPAMP1_BASE
	EXTI_BASE   uintptr = APB2PERIPH_BASE + 0x00000400
	TIM1_BASE   uintptr = APB2PERIPH_BASE + 0x00002C00
	SPI1_BASE   uintptr = APB2PERIPH_BASE + 0x00003000
	TIM8_BASE   uintptr = APB2PERIPH_BASE + 0x00003400
	USART1_BASE uintptr = APB2PERIPH_BASE + 0x00003800
	SPI4_BASE   uintptr = APB2PERIPH_BASE + 0x00003C00
	TIM15_BASE  uintptr = APB2PERIPH_BASE + 0x00004000
	TIM16_BASE  uintptr = APB2PERIPH_BASE + 0x00004400
	TIM17_BASE  uintptr = APB2PERIPH_BASE + 0x00004800
	TIM20_BASE  uintptr = APB2PERIPH_BASE + 0x00005000
)

APB2 peripherals

const (
	DMA1_BASE          uintptr = AHB1PERIPH_BASE + 0x00000000
	DMA1_Channel1_BASE uintptr = AHB1PERIPH_BASE + 0x00000008
	DMA1_Channel2_BASE uintptr = AHB1PERIPH_BASE + 0x0000001C
	DMA1_Channel3_BASE uintptr = AHB1PERIPH_BASE + 0x00000030
	DMA1_Channel4_BASE uintptr = AHB1PERIPH_BASE + 0x00000044
	DMA1_Channel5_BASE uintptr = AHB1PERIPH_BASE + 0x00000058
	DMA1_Channel6_BASE uintptr = AHB1PERIPH_BASE + 0x0000006C
	DMA1_Channel7_BASE uintptr = AHB1PERIPH_BASE + 0x00000080
	DMA2_BASE          uintptr = AHB1PERIPH_BASE + 0x00000400
	DMA2_Channel1_BASE uintptr = AHB1PERIPH_BASE + 0x00000408
	DMA2_Channel2_BASE uintptr = AHB1PERIPH_BASE + 0x0000041C
	DMA2_Channel3_BASE uintptr = AHB1PERIPH_BASE + 0x00000430
	DMA2_Channel4_BASE uintptr = AHB1PERIPH_BASE + 0x00000444
	DMA2_Channel5_BASE uintptr = AHB1PERIPH_BASE + 0x00000458
	RCC_BASE           uintptr = AHB1PERIPH_BASE + 0x00001000
	FLASH_R_BASE       uintptr = AHB1PERIPH_BASE + 0x00002000 // Flash registers base address
	OB_BASE            uintptr = 0x1FFFF800                   // Flash Option Bytes base address
	FLASHSIZE_BASE     uintptr = 0x1FFFF7CC                   // FLASH Size register base address
	UID_BASE           uintptr = 0x1FFFF7AC                   // Unique device ID register base address
	CRC_BASE           uintptr = AHB1PERIPH_BASE + 0x00003000
	TSC_BASE           uintptr = AHB1PERIPH_BASE + 0x00004000
)

AHB1 peripherals

const (
	GPIOA_BASE uintptr = AHB2PERIPH_BASE + 0x00000000
	GPIOB_BASE uintptr = AHB2PERIPH_BASE + 0x00000400
	GPIOC_BASE uintptr = AHB2PERIPH_BASE + 0x00000800
	GPIOD_BASE uintptr = AHB2PERIPH_BASE + 0x00000C00
	GPIOE_BASE uintptr = AHB2PERIPH_BASE + 0x00001000
	GPIOF_BASE uintptr = AHB2PERIPH_BASE + 0x00001400
	GPIOG_BASE uintptr = AHB2PERIPH_BASE + 0x00001800
	GPIOH_BASE uintptr = AHB2PERIPH_BASE + 0x00001C00
)

AHB2 peripherals

const (
	ADC1_BASE          uintptr = AHB3PERIPH_BASE + 0x00000000
	ADC2_BASE          uintptr = AHB3PERIPH_BASE + 0x00000100
	ADC1_2_COMMON_BASE uintptr = AHB3PERIPH_BASE + 0x00000300
	ADC3_BASE          uintptr = AHB3PERIPH_BASE + 0x00000400
	ADC4_BASE          uintptr = AHB3PERIPH_BASE + 0x00000500
	ADC3_4_COMMON_BASE uintptr = AHB3PERIPH_BASE + 0x00000700
)

AHB3 peripherals

const (
	FMC_BANK1   uintptr = FMC_BASE               // FMC Bank1 base address
	FMC_BANK1_1 uintptr = FMC_BANK1              // FMC Bank1_1 base address
	FMC_BANK1_2 uintptr = FMC_BANK1 + 0x04000000 // FMC Bank1_2 base address
	FMC_BANK1_3 uintptr = FMC_BANK1 + 0x08000000 // FMC Bank1_3 base address
	FMC_BANK1_4 uintptr = FMC_BANK1 + 0x0C000000 // FMC Bank1_4 base address
	FMC_BANK2   uintptr = FMC_BASE + 0x10000000  // FMC Bank2 base address
	FMC_BANK3   uintptr = FMC_BASE + 0x20000000  // FMC Bank3 base address
	FMC_BANK4   uintptr = FMC_BASE + 0x30000000  // FMC Bank4 base address
)

FMC Bankx base address

const (
	FMC_Bank1_R_BASE   uintptr = FMC_R_BASE + 0x0000
	FMC_Bank1E_R_BASE  uintptr = FMC_R_BASE + 0x0104
	FMC_Bank2_3_R_BASE uintptr = FMC_R_BASE + 0x0060
	FMC_Bank4_R_BASE   uintptr = FMC_R_BASE + 0x00A0
	DBGMCU_BASE        uintptr = 0xE0042000 // Debug MCU registers base address
)

FMC Bankx registers base address