fmc

package
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 Go to latest Published: Dec 5, 2021 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package fmc provides interface to .

Peripheral: FMC_Bank1_Periph Flexible Memory Controller. Instances: 

FMC_Bank1  mmap.FMC_Bank1_R_BASE

Registers: 

0x00 32  BTCR{BCR,BTR}[4] NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR).

Import: 

stm32/o/f303xe/mmap

Peripheral: FMC_Bank1E_Periph Flexible Memory Controller Bank1E. Instances: 

FMC_Bank1E  mmap.FMC_Bank1E_R_BASE

Registers: 

0x00 32  BWTR[7] NOR/PSRAM write timing registers.

Import: 

stm32/o/f303xe/mmap

Peripheral: FMC_Bank2_3_Periph Flexible Memory Controller Bank2. Instances: 

FMC_Bank2_3  mmap.FMC_Bank2_3_R_BASE

Registers: 

0x00 32  PCR2  NAND Flash control register 2.
0x04 32  SR2   NAND Flash FIFO status and interrupt register 2.
0x08 32  PMEM2 NAND Flash Common memory space timing register 2.
0x0C 32  PATT2 NAND Flash Attribute memory space timing register 2.
0x14 32  ECCR2 NAND Flash ECC result registers 2.
0x20 32  PCR3  NAND Flash control register 3.
0x24 32  SR3   NAND Flash FIFO status and interrupt register 3.
0x28 32  PMEM3 NAND Flash Common memory space timing register 3.
0x2C 32  PATT3 NAND Flash Attribute memory space timing register 3.
0x34 32  ECCR3 NAND Flash ECC result registers 3.

Import: 

stm32/o/f303xe/mmap

Peripheral: FMC_Bank4_Periph Flexible Memory Controller Bank4. Instances: 

FMC_Bank4  mmap.FMC_Bank4_R_BASE

Registers: 

0x00 32  PCR4  PC Card  control register 4.
0x04 32  SR4   PC Card  FIFO status and interrupt register 4.
0x08 32  PMEM4 PC Card  Common memory space timing register 4.
0x0C 32  PATT4 PC Card  Attribute memory space timing register 4.
0x10 32  PIO4  PC Card  I/O space timing register 4.

Import: 

stm32/o/f303xe/mmap

Index

Constants

View Source 
const (
	MBKENn     = 0
	MUXENn     = 1
	MTYPn      = 2
	MWIDn      = 4
	FACCENn    = 6
	BURSTENn   = 8
	WAITPOLn   = 9
	WRAPMODn   = 10
	WAITCFGn   = 11
	WRENn      = 12
	WAITENn    = 13
	EXTMODn    = 14
	ASYNCWAITn = 15
	CBURSTRWn  = 19
	CCLKENn    = 20
)
View Source 
const (
	ADDSETn  = 0
	ADDHLDn  = 4
	DATASTn  = 8
	BUSTURNn = 16
	CLKDIVn  = 20
	DATLATn  = 24
	ACCMODn  = 28
)
View Source 
const (
	EADDSETn = 0
	EADDHLDn = 4
	EDATASTn = 8
	ECLKDIVn = 20
	EDATLATn = 24
	EACCMODn = 28
)
View Source 
const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)
View Source 
const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)
View Source 
const (
	MEMSET2n  = 0
	MEMWAIT2n = 8
	MEMHOLD2n = 16
	MEMHIZ2n  = 24
)
View Source 
const (
	ATTSET2n  = 0
	ATTWAIT2n = 8
	ATTHOLD2n = 16
	ATTHIZ2n  = 24
)
View Source 
const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)
View Source 
const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)
View Source 
const (
	MEMSET3n  = 0
	MEMWAIT3n = 8
	MEMHOLD3n = 16
	MEMHIZ3n  = 24
)
View Source 
const (
	ATTSET3n  = 0
	ATTWAIT3n = 8
	ATTHOLD3n = 16
	ATTHIZ3n  = 24
)
View Source 
const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)
View Source 
const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)
View Source 
const (
	MEMSET4n  = 0
	MEMWAIT4n = 8
	MEMHOLD4n = 16
	MEMHIZ4n  = 24
)
View Source 
const (
	ATTSET4n  = 0
	ATTWAIT4n = 8
	ATTHOLD4n = 16
	ATTHIZ4n  = 24
)
View Source 
const (
	IOSET4n  = 0
	IOWAIT4n = 8
	IOHOLD4n = 16
	IOHIZ4n  = 24
)
View Source 
const (
	ECC2n = 0
)
View Source 
const (
	ECC3n = 0
)

Variables

View Source 
var FMC_Bank1 = (*FMC_Bank1_Periph)(unsafe.Pointer(uintptr(mmap.FMC_Bank1_R_BASE)))
View Source 
var FMC_Bank1E = (*FMC_Bank1E_Periph)(unsafe.Pointer(uintptr(mmap.FMC_Bank1E_R_BASE)))
View Source 
var FMC_Bank2_3 = (*FMC_Bank2_3_Periph)(unsafe.Pointer(uintptr(mmap.FMC_Bank2_3_R_BASE)))
View Source 
var FMC_Bank4 = (*FMC_Bank4_Periph)(unsafe.Pointer(uintptr(mmap.FMC_Bank4_R_BASE)))

Functions

This section is empty.

Types

type BCR 

type BCR uint32
const (
	MBKEN     BCR = 0x01 << 0  //+ Memory bank enable bit.
	MUXEN     BCR = 0x01 << 1  //+ Address/data multiplexing enable bit.
	MTYP      BCR = 0x03 << 2  //+ MTYP[1:0] bits (Memory type).
	MWID      BCR = 0x03 << 4  //+ MWID[1:0] bits (Memory data bus width).
	FACCEN    BCR = 0x01 << 6  //+ Flash access enable.
	BURSTEN   BCR = 0x01 << 8  //+ Burst enable bit.
	WAITPOL   BCR = 0x01 << 9  //+ Wait signal polarity bit.
	WRAPMOD   BCR = 0x01 << 10 //+ Wrapped burst mode support.
	WAITCFG   BCR = 0x01 << 11 //+ Wait timing configuration.
	WREN      BCR = 0x01 << 12 //+ Write enable bit.
	WAITEN    BCR = 0x01 << 13 //+ Wait enable bit.
	EXTMOD    BCR = 0x01 << 14 //+ Extended mode enable.
	ASYNCWAIT BCR = 0x01 << 15 //+ Asynchronous wait.
	CBURSTRW  BCR = 0x01 << 19 //+ Write burst enable.
	CCLKEN    BCR = 0x01 << 20 //+ Continous clock enable.
)

func (BCR) Field 

func (b BCR) Field(mask BCR) int

func (BCR) J 

func (mask BCR) J(v int) BCR

type BTR 

type BTR uint32
const (
	ADDSET  BTR = 0x0F << 0  //+ ADDSET[3:0] bits (Address setup phase duration).
	ADDHLD  BTR = 0x0F << 4  //+ ADDHLD[3:0] bits (Address-hold phase duration).
	DATAST  BTR = 0xFF << 8  //+ DATAST [3:0] bits (Data-phase duration).
	BUSTURN BTR = 0x0F << 16 //+ BUSTURN[3:0] bits (Bus turnaround phase duration).
	CLKDIV  BTR = 0x0F << 20 //+ CLKDIV[3:0] bits (Clock divide ratio).
	DATLAT  BTR = 0x0F << 24 //+ DATLA[3:0] bits (Data latency).
	ACCMOD  BTR = 0x03 << 28 //+ ACCMOD[1:0] bits (Access mode).
)

func (BTR) Field 

func (b BTR) Field(mask BTR) int

func (BTR) J 

func (mask BTR) J(v int) BTR

type BWTR 

type BWTR uint32
const (
	EADDSET BWTR = 0x0F << 0  //+ ADDSET[3:0] bits (Address setup phase duration).
	EADDHLD BWTR = 0x0F << 4  //+ ADDHLD[3:0] bits (Address-hold phase duration).
	EDATAST BWTR = 0xFF << 8  //+ DATAST [3:0] bits (Data-phase duration).
	ECLKDIV BWTR = 0x0F << 20 //+ CLKDIV[3:0] bits (Clock divide ratio).
	EDATLAT BWTR = 0x0F << 24 //+ DATLA[3:0] bits (Data latency).
	EACCMOD BWTR = 0x03 << 28 //+ ACCMOD[1:0] bits (Access mode).
)

func (BWTR) Field 

func (b BWTR) Field(mask BWTR) int

func (BWTR) J 

func (mask BWTR) J(v int) BWTR

type ECCR2 

type ECCR2 uint32
const (
	ECC2 ECCR2 = 0xFFFFFFFF << 0 //+ ECC result.
)

func (ECCR2) Field 

func (b ECCR2) Field(mask ECCR2) int

func (ECCR2) J 

func (mask ECCR2) J(v int) ECCR2

type ECCR3 

type ECCR3 uint32
const (
	ECC3 ECCR3 = 0xFFFFFFFF << 0 //+ ECC result.
)

func (ECCR3) Field 

func (b ECCR3) Field(mask ECCR3) int

func (ECCR3) J 

func (mask ECCR3) J(v int) ECCR3

type FMC_Bank1E_Periph 

type FMC_Bank1E_Periph struct {
	BWTR [7]RBWTR
}

func (*FMC_Bank1E_Periph) BaseAddr 

func (p *FMC_Bank1E_Periph) BaseAddr() uintptr

func (*FMC_Bank1E_Periph) EACCMOD 

func (p *FMC_Bank1E_Periph) EACCMOD(n int) RMBWTR

func (*FMC_Bank1E_Periph) EADDHLD 

func (p *FMC_Bank1E_Periph) EADDHLD(n int) RMBWTR

func (*FMC_Bank1E_Periph) EADDSET 

func (p *FMC_Bank1E_Periph) EADDSET(n int) RMBWTR

func (*FMC_Bank1E_Periph) ECLKDIV 

func (p *FMC_Bank1E_Periph) ECLKDIV(n int) RMBWTR

func (*FMC_Bank1E_Periph) EDATAST 

func (p *FMC_Bank1E_Periph) EDATAST(n int) RMBWTR

func (*FMC_Bank1E_Periph) EDATLAT 

func (p *FMC_Bank1E_Periph) EDATLAT(n int) RMBWTR

type FMC_Bank1_Periph 

type FMC_Bank1_Periph struct {
	BTCR [4]RBTCR
}

func (*FMC_Bank1_Periph) ACCMOD 

func (p *FMC_Bank1_Periph) ACCMOD(n int) RMBTR

func (*FMC_Bank1_Periph) ADDHLD 

func (p *FMC_Bank1_Periph) ADDHLD(n int) RMBTR

func (*FMC_Bank1_Periph) ADDSET 

func (p *FMC_Bank1_Periph) ADDSET(n int) RMBTR

func (*FMC_Bank1_Periph) ASYNCWAIT 

func (p *FMC_Bank1_Periph) ASYNCWAIT(n int) RMBCR

func (*FMC_Bank1_Periph) BURSTEN 

func (p *FMC_Bank1_Periph) BURSTEN(n int) RMBCR

func (*FMC_Bank1_Periph) BUSTURN 

func (p *FMC_Bank1_Periph) BUSTURN(n int) RMBTR

func (*FMC_Bank1_Periph) BaseAddr 

func (p *FMC_Bank1_Periph) BaseAddr() uintptr

func (*FMC_Bank1_Periph) CBURSTRW 

func (p *FMC_Bank1_Periph) CBURSTRW(n int) RMBCR

func (*FMC_Bank1_Periph) CCLKEN 

func (p *FMC_Bank1_Periph) CCLKEN(n int) RMBCR

func (*FMC_Bank1_Periph) CLKDIV 

func (p *FMC_Bank1_Periph) CLKDIV(n int) RMBTR

func (*FMC_Bank1_Periph) DATAST 

func (p *FMC_Bank1_Periph) DATAST(n int) RMBTR

func (*FMC_Bank1_Periph) DATLAT 

func (p *FMC_Bank1_Periph) DATLAT(n int) RMBTR

func (*FMC_Bank1_Periph) EXTMOD 

func (p *FMC_Bank1_Periph) EXTMOD(n int) RMBCR

func (*FMC_Bank1_Periph) FACCEN 

func (p *FMC_Bank1_Periph) FACCEN(n int) RMBCR

func (*FMC_Bank1_Periph) MBKEN 

func (p *FMC_Bank1_Periph) MBKEN(n int) RMBCR

func (*FMC_Bank1_Periph) MTYP 

func (p *FMC_Bank1_Periph) MTYP(n int) RMBCR

func (*FMC_Bank1_Periph) MUXEN 

func (p *FMC_Bank1_Periph) MUXEN(n int) RMBCR

func (*FMC_Bank1_Periph) MWID 

func (p *FMC_Bank1_Periph) MWID(n int) RMBCR

func (*FMC_Bank1_Periph) WAITCFG 

func (p *FMC_Bank1_Periph) WAITCFG(n int) RMBCR

func (*FMC_Bank1_Periph) WAITEN 

func (p *FMC_Bank1_Periph) WAITEN(n int) RMBCR

func (*FMC_Bank1_Periph) WAITPOL 

func (p *FMC_Bank1_Periph) WAITPOL(n int) RMBCR

func (*FMC_Bank1_Periph) WRAPMOD 

func (p *FMC_Bank1_Periph) WRAPMOD(n int) RMBCR

func (*FMC_Bank1_Periph) WREN 

func (p *FMC_Bank1_Periph) WREN(n int) RMBCR

type FMC_Bank2_3_Periph 

type FMC_Bank2_3_Periph struct {
	PCR2  RPCR2
	SR2   RSR2
	PMEM2 RPMEM2
	PATT2 RPATT2

	ECCR2 RECCR2

	PCR3  RPCR3
	SR3   RSR3
	PMEM3 RPMEM3
	PATT3 RPATT3

	ECCR3 RECCR3
	// contains filtered or unexported fields
}

func (*FMC_Bank2_3_Periph) ATTHIZ2 

func (p *FMC_Bank2_3_Periph) ATTHIZ2() RMPATT2

func (*FMC_Bank2_3_Periph) ATTHIZ3 

func (p *FMC_Bank2_3_Periph) ATTHIZ3() RMPATT3

func (*FMC_Bank2_3_Periph) ATTHOLD2 

func (p *FMC_Bank2_3_Periph) ATTHOLD2() RMPATT2

func (*FMC_Bank2_3_Periph) ATTHOLD3 

func (p *FMC_Bank2_3_Periph) ATTHOLD3() RMPATT3

func (*FMC_Bank2_3_Periph) ATTSET2 

func (p *FMC_Bank2_3_Periph) ATTSET2() RMPATT2

func (*FMC_Bank2_3_Periph) ATTSET3 

func (p *FMC_Bank2_3_Periph) ATTSET3() RMPATT3

func (*FMC_Bank2_3_Periph) ATTWAIT2 

func (p *FMC_Bank2_3_Periph) ATTWAIT2() RMPATT2

func (*FMC_Bank2_3_Periph) ATTWAIT3 

func (p *FMC_Bank2_3_Periph) ATTWAIT3() RMPATT3

func (*FMC_Bank2_3_Periph) BaseAddr 

func (p *FMC_Bank2_3_Periph) BaseAddr() uintptr

func (*FMC_Bank2_3_Periph) ECC2 

func (p *FMC_Bank2_3_Periph) ECC2() RMECCR2

func (*FMC_Bank2_3_Periph) ECC3 

func (p *FMC_Bank2_3_Periph) ECC3() RMECCR3

func (*FMC_Bank2_3_Periph) ECCEN 

func (p *FMC_Bank2_3_Periph) ECCEN() RMPCR3

func (*FMC_Bank2_3_Periph) ECCPS 

func (p *FMC_Bank2_3_Periph) ECCPS() RMPCR3

func (*FMC_Bank2_3_Periph) FEMPT 

func (p *FMC_Bank2_3_Periph) FEMPT() RMSR3

func (*FMC_Bank2_3_Periph) IFEN 

func (p *FMC_Bank2_3_Periph) IFEN() RMSR3

func (*FMC_Bank2_3_Periph) IFS 

func (p *FMC_Bank2_3_Periph) IFS() RMSR3

func (*FMC_Bank2_3_Periph) ILEN 

func (p *FMC_Bank2_3_Periph) ILEN() RMSR3

func (*FMC_Bank2_3_Periph) ILS 

func (p *FMC_Bank2_3_Periph) ILS() RMSR3

func (*FMC_Bank2_3_Periph) IREN 

func (p *FMC_Bank2_3_Periph) IREN() RMSR3

func (*FMC_Bank2_3_Periph) IRS 

func (p *FMC_Bank2_3_Periph) IRS() RMSR3

func (*FMC_Bank2_3_Periph) MEMHIZ2 

func (p *FMC_Bank2_3_Periph) MEMHIZ2() RMPMEM2

func (*FMC_Bank2_3_Periph) MEMHIZ3 

func (p *FMC_Bank2_3_Periph) MEMHIZ3() RMPMEM3

func (*FMC_Bank2_3_Periph) MEMHOLD2 

func (p *FMC_Bank2_3_Periph) MEMHOLD2() RMPMEM2

func (*FMC_Bank2_3_Periph) MEMHOLD3 

func (p *FMC_Bank2_3_Periph) MEMHOLD3() RMPMEM3

func (*FMC_Bank2_3_Periph) MEMSET2 

func (p *FMC_Bank2_3_Periph) MEMSET2() RMPMEM2

func (*FMC_Bank2_3_Periph) MEMSET3 

func (p *FMC_Bank2_3_Periph) MEMSET3() RMPMEM3

func (*FMC_Bank2_3_Periph) MEMWAIT2 

func (p *FMC_Bank2_3_Periph) MEMWAIT2() RMPMEM2

func (*FMC_Bank2_3_Periph) MEMWAIT3 

func (p *FMC_Bank2_3_Periph) MEMWAIT3() RMPMEM3

func (*FMC_Bank2_3_Periph) PBKEN 

func (p *FMC_Bank2_3_Periph) PBKEN() RMPCR3

func (*FMC_Bank2_3_Periph) PTYP 

func (p *FMC_Bank2_3_Periph) PTYP() RMPCR3

func (*FMC_Bank2_3_Periph) PWAITEN 

func (p *FMC_Bank2_3_Periph) PWAITEN() RMPCR3

func (*FMC_Bank2_3_Periph) PWID 

func (p *FMC_Bank2_3_Periph) PWID() RMPCR3

func (*FMC_Bank2_3_Periph) TAR 

func (p *FMC_Bank2_3_Periph) TAR() RMPCR3

func (*FMC_Bank2_3_Periph) TCLR 

func (p *FMC_Bank2_3_Periph) TCLR() RMPCR3

type FMC_Bank4_Periph 

type FMC_Bank4_Periph struct {
	PCR4  RPCR4
	SR4   RSR4
	PMEM4 RPMEM4
	PATT4 RPATT4
	PIO4  RPIO4
}

func (*FMC_Bank4_Periph) ATTHIZ4 

func (p *FMC_Bank4_Periph) ATTHIZ4() RMPATT4

func (*FMC_Bank4_Periph) ATTHOLD4 

func (p *FMC_Bank4_Periph) ATTHOLD4() RMPATT4

func (*FMC_Bank4_Periph) ATTSET4 

func (p *FMC_Bank4_Periph) ATTSET4() RMPATT4

func (*FMC_Bank4_Periph) ATTWAIT4 

func (p *FMC_Bank4_Periph) ATTWAIT4() RMPATT4

func (*FMC_Bank4_Periph) BaseAddr 

func (p *FMC_Bank4_Periph) BaseAddr() uintptr

func (*FMC_Bank4_Periph) ECCEN 

func (p *FMC_Bank4_Periph) ECCEN() RMPCR4

func (*FMC_Bank4_Periph) ECCPS 

func (p *FMC_Bank4_Periph) ECCPS() RMPCR4

func (*FMC_Bank4_Periph) FEMPT 

func (p *FMC_Bank4_Periph) FEMPT() RMSR4

func (*FMC_Bank4_Periph) IFEN 

func (p *FMC_Bank4_Periph) IFEN() RMSR4

func (*FMC_Bank4_Periph) IFS 

func (p *FMC_Bank4_Periph) IFS() RMSR4

func (*FMC_Bank4_Periph) ILEN 

func (p *FMC_Bank4_Periph) ILEN() RMSR4

func (*FMC_Bank4_Periph) ILS 

func (p *FMC_Bank4_Periph) ILS() RMSR4

func (*FMC_Bank4_Periph) IOHIZ4 

func (p *FMC_Bank4_Periph) IOHIZ4() RMPIO4

func (*FMC_Bank4_Periph) IOHOLD4 

func (p *FMC_Bank4_Periph) IOHOLD4() RMPIO4

func (*FMC_Bank4_Periph) IOSET4 

func (p *FMC_Bank4_Periph) IOSET4() RMPIO4

func (*FMC_Bank4_Periph) IOWAIT4 

func (p *FMC_Bank4_Periph) IOWAIT4() RMPIO4

func (*FMC_Bank4_Periph) IREN 

func (p *FMC_Bank4_Periph) IREN() RMSR4

func (*FMC_Bank4_Periph) IRS 

func (p *FMC_Bank4_Periph) IRS() RMSR4

func (*FMC_Bank4_Periph) MEMHIZ4 

func (p *FMC_Bank4_Periph) MEMHIZ4() RMPMEM4

func (*FMC_Bank4_Periph) MEMHOLD4 

func (p *FMC_Bank4_Periph) MEMHOLD4() RMPMEM4

func (*FMC_Bank4_Periph) MEMSET4 

func (p *FMC_Bank4_Periph) MEMSET4() RMPMEM4

func (*FMC_Bank4_Periph) MEMWAIT4 

func (p *FMC_Bank4_Periph) MEMWAIT4() RMPMEM4

func (*FMC_Bank4_Periph) PBKEN 

func (p *FMC_Bank4_Periph) PBKEN() RMPCR4

func (*FMC_Bank4_Periph) PTYP 

func (p *FMC_Bank4_Periph) PTYP() RMPCR4

func (*FMC_Bank4_Periph) PWAITEN 

func (p *FMC_Bank4_Periph) PWAITEN() RMPCR4

func (*FMC_Bank4_Periph) PWID 

func (p *FMC_Bank4_Periph) PWID() RMPCR4

func (*FMC_Bank4_Periph) TAR 

func (p *FMC_Bank4_Periph) TAR() RMPCR4

func (*FMC_Bank4_Periph) TCLR 

func (p *FMC_Bank4_Periph) TCLR() RMPCR4

type PATT2 

type PATT2 uint32
const (
	ATTSET2  PATT2 = 0xFF << 0  //+ ATTSET2[7:0] bits (Attribute memory 2 setup time).
	ATTWAIT2 PATT2 = 0xFF << 8  //+ ATTWAIT2[7:0] bits (Attribute memory 2 wait time).
	ATTHOLD2 PATT2 = 0xFF << 16 //+ ATTHOLD2[7:0] bits (Attribute memory 2 hold time).
	ATTHIZ2  PATT2 = 0xFF << 24 //+ ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time).
)

func (PATT2) Field 

func (b PATT2) Field(mask PATT2) int

func (PATT2) J 

func (mask PATT2) J(v int) PATT2

type PATT3 

type PATT3 uint32
const (
	ATTSET3  PATT3 = 0xFF << 0  //+ ATTSET3[7:0] bits (Attribute memory 3 setup time).
	ATTWAIT3 PATT3 = 0xFF << 8  //+ ATTWAIT3[7:0] bits (Attribute memory 3 wait time).
	ATTHOLD3 PATT3 = 0xFF << 16 //+ ATTHOLD3[7:0] bits (Attribute memory 3 hold time).
	ATTHIZ3  PATT3 = 0xFF << 24 //+ ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time).
)

func (PATT3) Field 

func (b PATT3) Field(mask PATT3) int

func (PATT3) J 

func (mask PATT3) J(v int) PATT3

type PATT4 

type PATT4 uint32
const (
	ATTSET4  PATT4 = 0xFF << 0  //+ ATTSET4[7:0] bits (Attribute memory 4 setup time).
	ATTWAIT4 PATT4 = 0xFF << 8  //+ ATTWAIT4[7:0] bits (Attribute memory 4 wait time).
	ATTHOLD4 PATT4 = 0xFF << 16 //+ ATTHOLD4[7:0] bits (Attribute memory 4 hold time).
	ATTHIZ4  PATT4 = 0xFF << 24 //+ ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time).
)

func (PATT4) Field 

func (b PATT4) Field(mask PATT4) int

func (PATT4) J 

func (mask PATT4) J(v int) PATT4

type PCR2 

type PCR2 uint32
const (
	PWAITEN PCR2 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR2 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR2 = 0x01 << 3  //+ Memory type.
	PWID    PCR2 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	ECCEN   PCR2 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR2 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TAR     PCR2 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	ECCPS   PCR2 = 0x07 << 17 //+ ECCPS[1:0] bits (ECC page size).
)

func (PCR2) Field 

func (b PCR2) Field(mask PCR2) int

func (PCR2) J 

func (mask PCR2) J(v int) PCR2

type PCR3 

type PCR3 uint32
const (
	PWAITEN PCR3 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR3 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR3 = 0x01 << 3  //+ Memory type.
	PWID    PCR3 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	ECCEN   PCR3 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR3 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TAR     PCR3 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	ECCPS   PCR3 = 0x07 << 17 //+ ECCPS[2:0] bits (ECC page size).
)

func (PCR3) Field 

func (b PCR3) Field(mask PCR3) int

func (PCR3) J 

func (mask PCR3) J(v int) PCR3

type PCR4 

type PCR4 uint32
const (
	PWAITEN PCR4 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR4 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR4 = 0x01 << 3  //+ Memory type.
	PWID    PCR4 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	ECCEN   PCR4 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR4 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TAR     PCR4 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	ECCPS   PCR4 = 0x07 << 17 //+ ECCPS[2:0] bits (ECC page size).
)

func (PCR4) Field 

func (b PCR4) Field(mask PCR4) int

func (PCR4) J 

func (mask PCR4) J(v int) PCR4

type PIO4 

type PIO4 uint32
const (
	IOSET4  PIO4 = 0xFF << 0  //+ IOSET4[7:0] bits (I/O 4 setup time).
	IOWAIT4 PIO4 = 0xFF << 8  //+ IOWAIT4[7:0] bits (I/O 4 wait time).
	IOHOLD4 PIO4 = 0xFF << 16 //+ IOHOLD4[7:0] bits (I/O 4 hold time).
	IOHIZ4  PIO4 = 0xFF << 24 //+ IOHIZ4[7:0] bits (I/O 4 databus HiZ time).
)

func (PIO4) Field 

func (b PIO4) Field(mask PIO4) int

func (PIO4) J 

func (mask PIO4) J(v int) PIO4

type PMEM2 

type PMEM2 uint32
const (
	MEMSET2  PMEM2 = 0xFF << 0  //+ MEMSET2[7:0] bits (Common memory 2 setup time).
	MEMWAIT2 PMEM2 = 0xFF << 8  //+ MEMWAIT2[7:0] bits (Common memory 2 wait time).
	MEMHOLD2 PMEM2 = 0xFF << 16 //+ MEMHOLD2[7:0] bits (Common memory 2 hold time).
	MEMHIZ2  PMEM2 = 0xFF << 24 //+ MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time).
)

func (PMEM2) Field 

func (b PMEM2) Field(mask PMEM2) int

func (PMEM2) J 

func (mask PMEM2) J(v int) PMEM2

type PMEM3 

type PMEM3 uint32
const (
	MEMSET3  PMEM3 = 0xFF << 0  //+ MEMSET3[7:0] bits (Common memory 3 setup time).
	MEMWAIT3 PMEM3 = 0xFF << 8  //+ MEMWAIT3[7:0] bits (Common memory 3 wait time).
	MEMHOLD3 PMEM3 = 0xFF << 16 //+ MEMHOLD3[7:0] bits (Common memory 3 hold time).
	MEMHIZ3  PMEM3 = 0xFF << 24 //+ MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time).
)

func (PMEM3) Field 

func (b PMEM3) Field(mask PMEM3) int

func (PMEM3) J 

func (mask PMEM3) J(v int) PMEM3

type PMEM4 

type PMEM4 uint32
const (
	MEMSET4  PMEM4 = 0xFF << 0  //+ MEMSET4[7:0] bits (Common memory 4 setup time).
	MEMWAIT4 PMEM4 = 0xFF << 8  //+ MEMWAIT4[7:0] bits (Common memory 4 wait time).
	MEMHOLD4 PMEM4 = 0xFF << 16 //+ MEMHOLD4[7:0] bits (Common memory 4 hold time).
	MEMHIZ4  PMEM4 = 0xFF << 24 //+ MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time).
)

func (PMEM4) Field 

func (b PMEM4) Field(mask PMEM4) int

func (PMEM4) J 

func (mask PMEM4) J(v int) PMEM4

type RBCR 

type RBCR struct{ mmio.U32 }

func (*RBCR) AtomicClearBits 

func (r *RBCR) AtomicClearBits(mask BCR)

func (*RBCR) AtomicSetBits 

func (r *RBCR) AtomicSetBits(mask BCR)

func (*RBCR) AtomicStoreBits 

func (r *RBCR) AtomicStoreBits(mask, b BCR)

func (*RBCR) Bits 

func (r *RBCR) Bits(mask BCR) BCR

func (*RBCR) ClearBits 

func (r *RBCR) ClearBits(mask BCR)

func (*RBCR) Load 

func (r *RBCR) Load() BCR

func (*RBCR) SetBits 

func (r *RBCR) SetBits(mask BCR)

func (*RBCR) Store 

func (r *RBCR) Store(b BCR)

func (*RBCR) StoreBits 

func (r *RBCR) StoreBits(mask, b BCR)

type RBTCR 

type RBTCR struct {
	BCR RBCR
	BTR RBTR
}

type RBTR 

type RBTR struct{ mmio.U32 }

func (*RBTR) AtomicClearBits 

func (r *RBTR) AtomicClearBits(mask BTR)

func (*RBTR) AtomicSetBits 

func (r *RBTR) AtomicSetBits(mask BTR)

func (*RBTR) AtomicStoreBits 

func (r *RBTR) AtomicStoreBits(mask, b BTR)

func (*RBTR) Bits 

func (r *RBTR) Bits(mask BTR) BTR

func (*RBTR) ClearBits 

func (r *RBTR) ClearBits(mask BTR)

func (*RBTR) Load 

func (r *RBTR) Load() BTR

func (*RBTR) SetBits 

func (r *RBTR) SetBits(mask BTR)

func (*RBTR) Store 

func (r *RBTR) Store(b BTR)

func (*RBTR) StoreBits 

func (r *RBTR) StoreBits(mask, b BTR)

type RBWTR 

type RBWTR struct{ mmio.U32 }

func (*RBWTR) AtomicClearBits 

func (r *RBWTR) AtomicClearBits(mask BWTR)

func (*RBWTR) AtomicSetBits 

func (r *RBWTR) AtomicSetBits(mask BWTR)

func (*RBWTR) AtomicStoreBits 

func (r *RBWTR) AtomicStoreBits(mask, b BWTR)

func (*RBWTR) Bits 

func (r *RBWTR) Bits(mask BWTR) BWTR

func (*RBWTR) ClearBits 

func (r *RBWTR) ClearBits(mask BWTR)

func (*RBWTR) Load 

func (r *RBWTR) Load() BWTR

func (*RBWTR) SetBits 

func (r *RBWTR) SetBits(mask BWTR)

func (*RBWTR) Store 

func (r *RBWTR) Store(b BWTR)

func (*RBWTR) StoreBits 

func (r *RBWTR) StoreBits(mask, b BWTR)

type RECCR2 

type RECCR2 struct{ mmio.U32 }

func (*RECCR2) AtomicClearBits 

func (r *RECCR2) AtomicClearBits(mask ECCR2)

func (*RECCR2) AtomicSetBits 

func (r *RECCR2) AtomicSetBits(mask ECCR2)

func (*RECCR2) AtomicStoreBits 

func (r *RECCR2) AtomicStoreBits(mask, b ECCR2)

func (*RECCR2) Bits 

func (r *RECCR2) Bits(mask ECCR2) ECCR2

func (*RECCR2) ClearBits 

func (r *RECCR2) ClearBits(mask ECCR2)

func (*RECCR2) Load 

func (r *RECCR2) Load() ECCR2

func (*RECCR2) SetBits 

func (r *RECCR2) SetBits(mask ECCR2)

func (*RECCR2) Store 

func (r *RECCR2) Store(b ECCR2)

func (*RECCR2) StoreBits 

func (r *RECCR2) StoreBits(mask, b ECCR2)

type RECCR3 

type RECCR3 struct{ mmio.U32 }

func (*RECCR3) AtomicClearBits 

func (r *RECCR3) AtomicClearBits(mask ECCR3)

func (*RECCR3) AtomicSetBits 

func (r *RECCR3) AtomicSetBits(mask ECCR3)

func (*RECCR3) AtomicStoreBits 

func (r *RECCR3) AtomicStoreBits(mask, b ECCR3)

func (*RECCR3) Bits 

func (r *RECCR3) Bits(mask ECCR3) ECCR3

func (*RECCR3) ClearBits 

func (r *RECCR3) ClearBits(mask ECCR3)

func (*RECCR3) Load 

func (r *RECCR3) Load() ECCR3

func (*RECCR3) SetBits 

func (r *RECCR3) SetBits(mask ECCR3)

func (*RECCR3) Store 

func (r *RECCR3) Store(b ECCR3)

func (*RECCR3) StoreBits 

func (r *RECCR3) StoreBits(mask, b ECCR3)

type RMBCR 

type RMBCR struct{ mmio.UM32 }

func (RMBCR) Load 

func (rm RMBCR) Load() BCR

func (RMBCR) Store 

func (rm RMBCR) Store(b BCR)

type RMBTR 

type RMBTR struct{ mmio.UM32 }

func (RMBTR) Load 

func (rm RMBTR) Load() BTR

func (RMBTR) Store 

func (rm RMBTR) Store(b BTR)

type RMBWTR 

type RMBWTR struct{ mmio.UM32 }

func (RMBWTR) Load 

func (rm RMBWTR) Load() BWTR

func (RMBWTR) Store 

func (rm RMBWTR) Store(b BWTR)

type RMECCR2 

type RMECCR2 struct{ mmio.UM32 }

func (RMECCR2) Load 

func (rm RMECCR2) Load() ECCR2

func (RMECCR2) Store 

func (rm RMECCR2) Store(b ECCR2)

type RMECCR3 

type RMECCR3 struct{ mmio.UM32 }

func (RMECCR3) Load 

func (rm RMECCR3) Load() ECCR3

func (RMECCR3) Store 

func (rm RMECCR3) Store(b ECCR3)

type RMPATT2 

type RMPATT2 struct{ mmio.UM32 }

func (RMPATT2) Load 

func (rm RMPATT2) Load() PATT2

func (RMPATT2) Store 

func (rm RMPATT2) Store(b PATT2)

type RMPATT3 

type RMPATT3 struct{ mmio.UM32 }

func (RMPATT3) Load 

func (rm RMPATT3) Load() PATT3

func (RMPATT3) Store 

func (rm RMPATT3) Store(b PATT3)

type RMPATT4 

type RMPATT4 struct{ mmio.UM32 }

func (RMPATT4) Load 

func (rm RMPATT4) Load() PATT4

func (RMPATT4) Store 

func (rm RMPATT4) Store(b PATT4)

type RMPCR2 

type RMPCR2 struct{ mmio.UM32 }

func (RMPCR2) Load 

func (rm RMPCR2) Load() PCR2

func (RMPCR2) Store 

func (rm RMPCR2) Store(b PCR2)

type RMPCR3 

type RMPCR3 struct{ mmio.UM32 }

func (RMPCR3) Load 

func (rm RMPCR3) Load() PCR3

func (RMPCR3) Store 

func (rm RMPCR3) Store(b PCR3)

type RMPCR4 

type RMPCR4 struct{ mmio.UM32 }

func (RMPCR4) Load 

func (rm RMPCR4) Load() PCR4

func (RMPCR4) Store 

func (rm RMPCR4) Store(b PCR4)

type RMPIO4 

type RMPIO4 struct{ mmio.UM32 }

func (RMPIO4) Load 

func (rm RMPIO4) Load() PIO4

func (RMPIO4) Store 

func (rm RMPIO4) Store(b PIO4)

type RMPMEM2 

type RMPMEM2 struct{ mmio.UM32 }

func (RMPMEM2) Load 

func (rm RMPMEM2) Load() PMEM2

func (RMPMEM2) Store 

func (rm RMPMEM2) Store(b PMEM2)

type RMPMEM3 

type RMPMEM3 struct{ mmio.UM32 }

func (RMPMEM3) Load 

func (rm RMPMEM3) Load() PMEM3

func (RMPMEM3) Store 

func (rm RMPMEM3) Store(b PMEM3)

type RMPMEM4 

type RMPMEM4 struct{ mmio.UM32 }

func (RMPMEM4) Load 

func (rm RMPMEM4) Load() PMEM4

func (RMPMEM4) Store 

func (rm RMPMEM4) Store(b PMEM4)

type RMSR2 

type RMSR2 struct{ mmio.UM32 }

func (RMSR2) Load 

func (rm RMSR2) Load() SR2

func (RMSR2) Store 

func (rm RMSR2) Store(b SR2)

type RMSR3 

type RMSR3 struct{ mmio.UM32 }

func (RMSR3) Load 

func (rm RMSR3) Load() SR3

func (RMSR3) Store 

func (rm RMSR3) Store(b SR3)

type RMSR4 

type RMSR4 struct{ mmio.UM32 }

func (RMSR4) Load 

func (rm RMSR4) Load() SR4

func (RMSR4) Store 

func (rm RMSR4) Store(b SR4)

type RPATT2 

type RPATT2 struct{ mmio.U32 }

func (*RPATT2) AtomicClearBits 

func (r *RPATT2) AtomicClearBits(mask PATT2)

func (*RPATT2) AtomicSetBits 

func (r *RPATT2) AtomicSetBits(mask PATT2)

func (*RPATT2) AtomicStoreBits 

func (r *RPATT2) AtomicStoreBits(mask, b PATT2)

func (*RPATT2) Bits 

func (r *RPATT2) Bits(mask PATT2) PATT2

func (*RPATT2) ClearBits 

func (r *RPATT2) ClearBits(mask PATT2)

func (*RPATT2) Load 

func (r *RPATT2) Load() PATT2

func (*RPATT2) SetBits 

func (r *RPATT2) SetBits(mask PATT2)

func (*RPATT2) Store 

func (r *RPATT2) Store(b PATT2)

func (*RPATT2) StoreBits 

func (r *RPATT2) StoreBits(mask, b PATT2)

type RPATT3 

type RPATT3 struct{ mmio.U32 }

func (*RPATT3) AtomicClearBits 

func (r *RPATT3) AtomicClearBits(mask PATT3)

func (*RPATT3) AtomicSetBits 

func (r *RPATT3) AtomicSetBits(mask PATT3)

func (*RPATT3) AtomicStoreBits 

func (r *RPATT3) AtomicStoreBits(mask, b PATT3)

func (*RPATT3) Bits 

func (r *RPATT3) Bits(mask PATT3) PATT3

func (*RPATT3) ClearBits 

func (r *RPATT3) ClearBits(mask PATT3)

func (*RPATT3) Load 

func (r *RPATT3) Load() PATT3

func (*RPATT3) SetBits 

func (r *RPATT3) SetBits(mask PATT3)

func (*RPATT3) Store 

func (r *RPATT3) Store(b PATT3)

func (*RPATT3) StoreBits 

func (r *RPATT3) StoreBits(mask, b PATT3)

type RPATT4 

type RPATT4 struct{ mmio.U32 }

func (*RPATT4) AtomicClearBits 

func (r *RPATT4) AtomicClearBits(mask PATT4)

func (*RPATT4) AtomicSetBits 

func (r *RPATT4) AtomicSetBits(mask PATT4)

func (*RPATT4) AtomicStoreBits 

func (r *RPATT4) AtomicStoreBits(mask, b PATT4)

func (*RPATT4) Bits 

func (r *RPATT4) Bits(mask PATT4) PATT4

func (*RPATT4) ClearBits 

func (r *RPATT4) ClearBits(mask PATT4)

func (*RPATT4) Load 

func (r *RPATT4) Load() PATT4

func (*RPATT4) SetBits 

func (r *RPATT4) SetBits(mask PATT4)

func (*RPATT4) Store 

func (r *RPATT4) Store(b PATT4)

func (*RPATT4) StoreBits 

func (r *RPATT4) StoreBits(mask, b PATT4)

type RPCR2 

type RPCR2 struct{ mmio.U32 }

func (*RPCR2) AtomicClearBits 

func (r *RPCR2) AtomicClearBits(mask PCR2)

func (*RPCR2) AtomicSetBits 

func (r *RPCR2) AtomicSetBits(mask PCR2)

func (*RPCR2) AtomicStoreBits 

func (r *RPCR2) AtomicStoreBits(mask, b PCR2)

func (*RPCR2) Bits 

func (r *RPCR2) Bits(mask PCR2) PCR2

func (*RPCR2) ClearBits 

func (r *RPCR2) ClearBits(mask PCR2)

func (*RPCR2) Load 

func (r *RPCR2) Load() PCR2

func (*RPCR2) SetBits 

func (r *RPCR2) SetBits(mask PCR2)

func (*RPCR2) Store 

func (r *RPCR2) Store(b PCR2)

func (*RPCR2) StoreBits 

func (r *RPCR2) StoreBits(mask, b PCR2)

type RPCR3 

type RPCR3 struct{ mmio.U32 }

func (*RPCR3) AtomicClearBits 

func (r *RPCR3) AtomicClearBits(mask PCR3)

func (*RPCR3) AtomicSetBits 

func (r *RPCR3) AtomicSetBits(mask PCR3)

func (*RPCR3) AtomicStoreBits 

func (r *RPCR3) AtomicStoreBits(mask, b PCR3)

func (*RPCR3) Bits 

func (r *RPCR3) Bits(mask PCR3) PCR3

func (*RPCR3) ClearBits 

func (r *RPCR3) ClearBits(mask PCR3)

func (*RPCR3) Load 

func (r *RPCR3) Load() PCR3

func (*RPCR3) SetBits 

func (r *RPCR3) SetBits(mask PCR3)

func (*RPCR3) Store 

func (r *RPCR3) Store(b PCR3)

func (*RPCR3) StoreBits 

func (r *RPCR3) StoreBits(mask, b PCR3)

type RPCR4 

type RPCR4 struct{ mmio.U32 }

func (*RPCR4) AtomicClearBits 

func (r *RPCR4) AtomicClearBits(mask PCR4)

func (*RPCR4) AtomicSetBits 

func (r *RPCR4) AtomicSetBits(mask PCR4)

func (*RPCR4) AtomicStoreBits 

func (r *RPCR4) AtomicStoreBits(mask, b PCR4)

func (*RPCR4) Bits 

func (r *RPCR4) Bits(mask PCR4) PCR4

func (*RPCR4) ClearBits 

func (r *RPCR4) ClearBits(mask PCR4)

func (*RPCR4) Load 

func (r *RPCR4) Load() PCR4

func (*RPCR4) SetBits 

func (r *RPCR4) SetBits(mask PCR4)

func (*RPCR4) Store 

func (r *RPCR4) Store(b PCR4)

func (*RPCR4) StoreBits 

func (r *RPCR4) StoreBits(mask, b PCR4)

type RPIO4 

type RPIO4 struct{ mmio.U32 }

func (*RPIO4) AtomicClearBits 

func (r *RPIO4) AtomicClearBits(mask PIO4)

func (*RPIO4) AtomicSetBits 

func (r *RPIO4) AtomicSetBits(mask PIO4)

func (*RPIO4) AtomicStoreBits 

func (r *RPIO4) AtomicStoreBits(mask, b PIO4)

func (*RPIO4) Bits 

func (r *RPIO4) Bits(mask PIO4) PIO4

func (*RPIO4) ClearBits 

func (r *RPIO4) ClearBits(mask PIO4)

func (*RPIO4) Load 

func (r *RPIO4) Load() PIO4

func (*RPIO4) SetBits 

func (r *RPIO4) SetBits(mask PIO4)

func (*RPIO4) Store 

func (r *RPIO4) Store(b PIO4)

func (*RPIO4) StoreBits 

func (r *RPIO4) StoreBits(mask, b PIO4)

type RPMEM2 

type RPMEM2 struct{ mmio.U32 }

func (*RPMEM2) AtomicClearBits 

func (r *RPMEM2) AtomicClearBits(mask PMEM2)

func (*RPMEM2) AtomicSetBits 

func (r *RPMEM2) AtomicSetBits(mask PMEM2)

func (*RPMEM2) AtomicStoreBits 

func (r *RPMEM2) AtomicStoreBits(mask, b PMEM2)

func (*RPMEM2) Bits 

func (r *RPMEM2) Bits(mask PMEM2) PMEM2

func (*RPMEM2) ClearBits 

func (r *RPMEM2) ClearBits(mask PMEM2)

func (*RPMEM2) Load 

func (r *RPMEM2) Load() PMEM2

func (*RPMEM2) SetBits 

func (r *RPMEM2) SetBits(mask PMEM2)

func (*RPMEM2) Store 

func (r *RPMEM2) Store(b PMEM2)

func (*RPMEM2) StoreBits 

func (r *RPMEM2) StoreBits(mask, b PMEM2)

type RPMEM3 

type RPMEM3 struct{ mmio.U32 }

func (*RPMEM3) AtomicClearBits 

func (r *RPMEM3) AtomicClearBits(mask PMEM3)

func (*RPMEM3) AtomicSetBits 

func (r *RPMEM3) AtomicSetBits(mask PMEM3)

func (*RPMEM3) AtomicStoreBits 

func (r *RPMEM3) AtomicStoreBits(mask, b PMEM3)

func (*RPMEM3) Bits 

func (r *RPMEM3) Bits(mask PMEM3) PMEM3

func (*RPMEM3) ClearBits 

func (r *RPMEM3) ClearBits(mask PMEM3)

func (*RPMEM3) Load 

func (r *RPMEM3) Load() PMEM3

func (*RPMEM3) SetBits 

func (r *RPMEM3) SetBits(mask PMEM3)

func (*RPMEM3) Store 

func (r *RPMEM3) Store(b PMEM3)

func (*RPMEM3) StoreBits 

func (r *RPMEM3) StoreBits(mask, b PMEM3)

type RPMEM4 

type RPMEM4 struct{ mmio.U32 }

func (*RPMEM4) AtomicClearBits 

func (r *RPMEM4) AtomicClearBits(mask PMEM4)

func (*RPMEM4) AtomicSetBits 

func (r *RPMEM4) AtomicSetBits(mask PMEM4)

func (*RPMEM4) AtomicStoreBits 

func (r *RPMEM4) AtomicStoreBits(mask, b PMEM4)

func (*RPMEM4) Bits 

func (r *RPMEM4) Bits(mask PMEM4) PMEM4

func (*RPMEM4) ClearBits 

func (r *RPMEM4) ClearBits(mask PMEM4)

func (*RPMEM4) Load 

func (r *RPMEM4) Load() PMEM4

func (*RPMEM4) SetBits 

func (r *RPMEM4) SetBits(mask PMEM4)

func (*RPMEM4) Store 

func (r *RPMEM4) Store(b PMEM4)

func (*RPMEM4) StoreBits 

func (r *RPMEM4) StoreBits(mask, b PMEM4)

type RSR2 

type RSR2 struct{ mmio.U32 }

func (*RSR2) AtomicClearBits 

func (r *RSR2) AtomicClearBits(mask SR2)

func (*RSR2) AtomicSetBits 

func (r *RSR2) AtomicSetBits(mask SR2)

func (*RSR2) AtomicStoreBits 

func (r *RSR2) AtomicStoreBits(mask, b SR2)

func (*RSR2) Bits 

func (r *RSR2) Bits(mask SR2) SR2

func (*RSR2) ClearBits 

func (r *RSR2) ClearBits(mask SR2)

func (*RSR2) Load 

func (r *RSR2) Load() SR2

func (*RSR2) SetBits 

func (r *RSR2) SetBits(mask SR2)

func (*RSR2) Store 

func (r *RSR2) Store(b SR2)

func (*RSR2) StoreBits 

func (r *RSR2) StoreBits(mask, b SR2)

type RSR3 

type RSR3 struct{ mmio.U32 }

func (*RSR3) AtomicClearBits 

func (r *RSR3) AtomicClearBits(mask SR3)

func (*RSR3) AtomicSetBits 

func (r *RSR3) AtomicSetBits(mask SR3)

func (*RSR3) AtomicStoreBits 

func (r *RSR3) AtomicStoreBits(mask, b SR3)

func (*RSR3) Bits 

func (r *RSR3) Bits(mask SR3) SR3

func (*RSR3) ClearBits 

func (r *RSR3) ClearBits(mask SR3)

func (*RSR3) Load 

func (r *RSR3) Load() SR3

func (*RSR3) SetBits 

func (r *RSR3) SetBits(mask SR3)

func (*RSR3) Store 

func (r *RSR3) Store(b SR3)

func (*RSR3) StoreBits 

func (r *RSR3) StoreBits(mask, b SR3)

type RSR4 

type RSR4 struct{ mmio.U32 }

func (*RSR4) AtomicClearBits 

func (r *RSR4) AtomicClearBits(mask SR4)

func (*RSR4) AtomicSetBits 

func (r *RSR4) AtomicSetBits(mask SR4)

func (*RSR4) AtomicStoreBits 

func (r *RSR4) AtomicStoreBits(mask, b SR4)

func (*RSR4) Bits 

func (r *RSR4) Bits(mask SR4) SR4

func (*RSR4) ClearBits 

func (r *RSR4) ClearBits(mask SR4)

func (*RSR4) Load 

func (r *RSR4) Load() SR4

func (*RSR4) SetBits 

func (r *RSR4) SetBits(mask SR4)

func (*RSR4) Store 

func (r *RSR4) Store(b SR4)

func (*RSR4) StoreBits 

func (r *RSR4) StoreBits(mask, b SR4)

type SR2 

type SR2 uint32
const (
	IRS   SR2 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR2 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR2 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR2 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR2 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR2 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR2 = 0x01 << 6 //+ FIFO empty.
)

func (SR2) Field 

func (b SR2) Field(mask SR2) int

func (SR2) J 

func (mask SR2) J(v int) SR2

type SR3 

type SR3 uint32
const (
	IRS   SR3 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR3 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR3 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR3 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR3 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR3 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR3 = 0x01 << 6 //+ FIFO empty.
)

func (SR3) Field 

func (b SR3) Field(mask SR3) int

func (SR3) J 

func (mask SR3) J(v int) SR3

type SR4 

type SR4 uint32
const (
	IRS   SR4 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR4 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR4 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR4 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR4 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR4 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR4 = 0x01 << 6 //+ FIFO empty.
)

func (SR4) Field 

func (b SR4) Field(mask SR4) int

func (SR4) J 

func (mask SR4) J(v int) SR4

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