fsmc

package
v0.0.0-...-168ccc2 Latest Latest
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 Go to latest Published: Dec 5, 2021 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package fsmc provides interface to .

Peripheral: FSMC_Bank1_Periph Flexible Static Memory Controller. Instances: 

FSMC_Bank1  mmap.FSMC_Bank1_R_BASE

Registers: 

0x00 32  BTCR{BCR,BTR}[4]

Import: 

stm32/o/f10x_hd/mmap

Peripheral: FSMC_Bank1E_Periph Flexible Static Memory Controller Bank1E. Instances: 

FSMC_Bank1E  mmap.FSMC_Bank1E_R_BASE

Registers: 

0x00 32  BWTR[7]

Import: 

stm32/o/f10x_hd/mmap

Peripheral: FSMC_Bank2_Periph Flexible Static Memory Controller Bank2. Instances: 

FSMC_Bank2  mmap.FSMC_Bank2_R_BASE

Registers: 

0x00 32  PCR2
0x04 32  SR2
0x08 32  PMEM2
0x0C 32  PATT2
0x14 32  ECCR2

Import: 

stm32/o/f10x_hd/mmap

Peripheral: FSMC_Bank3_Periph Flexible Static Memory Controller Bank3. Instances: 

FSMC_Bank3  mmap.FSMC_Bank3_R_BASE

Registers: 

0x00 32  PCR3
0x04 32  SR3
0x08 32  PMEM3
0x0C 32  PATT3
0x14 32  ECCR3

Import: 

stm32/o/f10x_hd/mmap

Peripheral: FSMC_Bank4_Periph Flexible Static Memory Controller Bank4. Instances: 

FSMC_Bank4  mmap.FSMC_Bank4_R_BASE

Registers: 

0x00 32  PCR4
0x04 32  SR4
0x08 32  PMEM4
0x0C 32  PATT4
0x10 32  PIO4

Import: 

stm32/o/f10x_hd/mmap

Index

Constants

View Source 
const (
	MBKENn     = 0
	MUXENn     = 1
	MTYPn      = 2
	MWIDn      = 4
	FACCENn    = 6
	BURSTENn   = 8
	WAITPOLn   = 9
	WRAPMODn   = 10
	WAITCFGn   = 11
	WRENn      = 12
	WAITENn    = 13
	EXTMODn    = 14
	ASYNCWAITn = 15
	CBURSTRWn  = 19
)
View Source 
const (
	ADDSETn  = 0
	ADDHLDn  = 4
	DATASTn  = 8
	BUSTURNn = 16
	CLKDIVn  = 20
	DATLATn  = 24
	ACCMODn  = 28
)
View Source 
const (
	EADDSETn = 0
	EADDHLDn = 4
	EDATASTn = 8
	ECLKDIVn = 20
	EDATLATn = 24
	EACCMODn = 28
)
View Source 
const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)
View Source 
const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)
View Source 
const (
	MEMSET2n  = 0
	MEMWAIT2n = 8
	MEMHOLD2n = 16
	MEMHIZ2n  = 24
)
View Source 
const (
	ATTSET2n  = 0
	ATTWAIT2n = 8
	ATTHOLD2n = 16
	ATTHIZ2n  = 24
)
View Source 
const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)
View Source 
const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)
View Source 
const (
	MEMSET3n  = 0
	MEMWAIT3n = 8
	MEMHOLD3n = 16
	MEMHIZ3n  = 24
)
View Source 
const (
	ATTSET3n  = 0
	ATTWAIT3n = 8
	ATTHOLD3n = 16
	ATTHIZ3n  = 24
)
View Source 
const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)
View Source 
const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)
View Source 
const (
	MEMSET4n  = 0
	MEMWAIT4n = 8
	MEMHOLD4n = 16
	MEMHIZ4n  = 24
)
View Source 
const (
	ATTSET4n  = 0
	ATTWAIT4n = 8
	ATTHOLD4n = 16
	ATTHIZ4n  = 24
)
View Source 
const (
	IOSET4n  = 0
	IOWAIT4n = 8
	IOHOLD4n = 16
	IOHIZ4n  = 24
)
View Source 
const (
	ECC2n = 0
)
View Source 
const (
	ECC3n = 0
)

Variables

View Source 
var FSMC_Bank1 = (*FSMC_Bank1_Periph)(unsafe.Pointer(uintptr(mmap.FSMC_Bank1_R_BASE)))
View Source 
var FSMC_Bank1E = (*FSMC_Bank1E_Periph)(unsafe.Pointer(uintptr(mmap.FSMC_Bank1E_R_BASE)))
View Source 
var FSMC_Bank2 = (*FSMC_Bank2_Periph)(unsafe.Pointer(uintptr(mmap.FSMC_Bank2_R_BASE)))
View Source 
var FSMC_Bank3 = (*FSMC_Bank3_Periph)(unsafe.Pointer(uintptr(mmap.FSMC_Bank3_R_BASE)))
View Source 
var FSMC_Bank4 = (*FSMC_Bank4_Periph)(unsafe.Pointer(uintptr(mmap.FSMC_Bank4_R_BASE)))

Functions

This section is empty.

Types

type BCR 

type BCR uint32
const (
	MBKEN     BCR = 0x01 << 0  //+ Memory bank enable bit.
	MUXEN     BCR = 0x01 << 1  //+ Address/data multiplexing enable bit.
	MTYP      BCR = 0x03 << 2  //+ MTYP[1:0] bits (Memory type).
	MTYP_0    BCR = 0x01 << 2  //  Bit 0.
	MTYP_1    BCR = 0x02 << 2  //  Bit 1.
	MWID      BCR = 0x03 << 4  //+ MWID[1:0] bits (Memory data bus width).
	MWID_0    BCR = 0x01 << 4  //  Bit 0.
	MWID_1    BCR = 0x02 << 4  //  Bit 1.
	FACCEN    BCR = 0x01 << 6  //+ Flash access enable.
	BURSTEN   BCR = 0x01 << 8  //+ Burst enable bit.
	WAITPOL   BCR = 0x01 << 9  //+ Wait signal polarity bit.
	WRAPMOD   BCR = 0x01 << 10 //+ Wrapped burst mode support.
	WAITCFG   BCR = 0x01 << 11 //+ Wait timing configuration.
	WREN      BCR = 0x01 << 12 //+ Write enable bit.
	WAITEN    BCR = 0x01 << 13 //+ Wait enable bit.
	EXTMOD    BCR = 0x01 << 14 //+ Extended mode enable.
	ASYNCWAIT BCR = 0x01 << 15 //+ Asynchronous wait.
	CBURSTRW  BCR = 0x01 << 19 //+ Write burst enable.
)

func (BCR) Field 

func (b BCR) Field(mask BCR) int

func (BCR) J 

func (mask BCR) J(v int) BCR

type BTR 

type BTR uint32
const (
	ADDSET    BTR = 0x0F << 0  //+ ADDSET[3:0] bits (Address setup phase duration).
	ADDSET_0  BTR = 0x01 << 0  //  Bit 0.
	ADDSET_1  BTR = 0x02 << 0  //  Bit 1.
	ADDSET_2  BTR = 0x04 << 0  //  Bit 2.
	ADDSET_3  BTR = 0x08 << 0  //  Bit 3.
	ADDHLD    BTR = 0x0F << 4  //+ ADDHLD[3:0] bits (Address-hold phase duration).
	ADDHLD_0  BTR = 0x01 << 4  //  Bit 0.
	ADDHLD_1  BTR = 0x02 << 4  //  Bit 1.
	ADDHLD_2  BTR = 0x04 << 4  //  Bit 2.
	ADDHLD_3  BTR = 0x08 << 4  //  Bit 3.
	DATAST    BTR = 0xFF << 8  //+ DATAST [3:0] bits (Data-phase duration).
	DATAST_0  BTR = 0x01 << 8  //  Bit 0.
	DATAST_1  BTR = 0x02 << 8  //  Bit 1.
	DATAST_2  BTR = 0x04 << 8  //  Bit 2.
	DATAST_3  BTR = 0x08 << 8  //  Bit 3.
	BUSTURN   BTR = 0x0F << 16 //+ BUSTURN[3:0] bits (Bus turnaround phase duration).
	BUSTURN_0 BTR = 0x01 << 16 //  Bit 0.
	BUSTURN_1 BTR = 0x02 << 16 //  Bit 1.
	BUSTURN_2 BTR = 0x04 << 16 //  Bit 2.
	BUSTURN_3 BTR = 0x08 << 16 //  Bit 3.
	CLKDIV    BTR = 0x0F << 20 //+ CLKDIV[3:0] bits (Clock divide ratio).
	CLKDIV_0  BTR = 0x01 << 20 //  Bit 0.
	CLKDIV_1  BTR = 0x02 << 20 //  Bit 1.
	CLKDIV_2  BTR = 0x04 << 20 //  Bit 2.
	CLKDIV_3  BTR = 0x08 << 20 //  Bit 3.
	DATLAT    BTR = 0x0F << 24 //+ DATLA[3:0] bits (Data latency).
	DATLAT_0  BTR = 0x01 << 24 //  Bit 0.
	DATLAT_1  BTR = 0x02 << 24 //  Bit 1.
	DATLAT_2  BTR = 0x04 << 24 //  Bit 2.
	DATLAT_3  BTR = 0x08 << 24 //  Bit 3.
	ACCMOD    BTR = 0x03 << 28 //+ ACCMOD[1:0] bits (Access mode).
	ACCMOD_0  BTR = 0x01 << 28 //  Bit 0.
	ACCMOD_1  BTR = 0x02 << 28 //  Bit 1.
)

func (BTR) Field 

func (b BTR) Field(mask BTR) int

func (BTR) J 

func (mask BTR) J(v int) BTR

type BWTR 

type BWTR uint32
const (
	EADDSET   BWTR = 0x0F << 0  //+ ADDSET[3:0] bits (Address setup phase duration).
	EADDSET_0 BWTR = 0x01 << 0  //  Bit 0.
	EADDSET_1 BWTR = 0x02 << 0  //  Bit 1.
	EADDSET_2 BWTR = 0x04 << 0  //  Bit 2.
	EADDSET_3 BWTR = 0x08 << 0  //  Bit 3.
	EADDHLD   BWTR = 0x0F << 4  //+ ADDHLD[3:0] bits (Address-hold phase duration).
	EADDHLD_0 BWTR = 0x01 << 4  //  Bit 0.
	EADDHLD_1 BWTR = 0x02 << 4  //  Bit 1.
	EADDHLD_2 BWTR = 0x04 << 4  //  Bit 2.
	EADDHLD_3 BWTR = 0x08 << 4  //  Bit 3.
	EDATAST   BWTR = 0xFF << 8  //+ DATAST [3:0] bits (Data-phase duration).
	EDATAST_0 BWTR = 0x01 << 8  //  Bit 0.
	EDATAST_1 BWTR = 0x02 << 8  //  Bit 1.
	EDATAST_2 BWTR = 0x04 << 8  //  Bit 2.
	EDATAST_3 BWTR = 0x08 << 8  //  Bit 3.
	ECLKDIV   BWTR = 0x0F << 20 //+ CLKDIV[3:0] bits (Clock divide ratio).
	ECLKDIV_0 BWTR = 0x01 << 20 //  Bit 0.
	ECLKDIV_1 BWTR = 0x02 << 20 //  Bit 1.
	ECLKDIV_2 BWTR = 0x04 << 20 //  Bit 2.
	ECLKDIV_3 BWTR = 0x08 << 20 //  Bit 3.
	EDATLAT   BWTR = 0x0F << 24 //+ DATLA[3:0] bits (Data latency).
	EDATLAT_0 BWTR = 0x01 << 24 //  Bit 0.
	EDATLAT_1 BWTR = 0x02 << 24 //  Bit 1.
	EDATLAT_2 BWTR = 0x04 << 24 //  Bit 2.
	EDATLAT_3 BWTR = 0x08 << 24 //  Bit 3.
	EACCMOD   BWTR = 0x03 << 28 //+ ACCMOD[1:0] bits (Access mode).
	EACCMOD_0 BWTR = 0x01 << 28 //  Bit 0.
	EACCMOD_1 BWTR = 0x02 << 28 //  Bit 1.
)

func (BWTR) Field 

func (b BWTR) Field(mask BWTR) int

func (BWTR) J 

func (mask BWTR) J(v int) BWTR

type ECCR2 

type ECCR2 uint32
const (
	ECC2 ECCR2 = 0xFFFFFFFF << 0 //+ ECC result.
)

func (ECCR2) Field 

func (b ECCR2) Field(mask ECCR2) int

func (ECCR2) J 

func (mask ECCR2) J(v int) ECCR2

type ECCR3 

type ECCR3 uint32
const (
	ECC3 ECCR3 = 0xFFFFFFFF << 0 //+ ECC result.
)

func (ECCR3) Field 

func (b ECCR3) Field(mask ECCR3) int

func (ECCR3) J 

func (mask ECCR3) J(v int) ECCR3

type FSMC_Bank1E_Periph 

type FSMC_Bank1E_Periph struct {
	BWTR [7]RBWTR
}

func (*FSMC_Bank1E_Periph) BaseAddr 

func (p *FSMC_Bank1E_Periph) BaseAddr() uintptr

func (*FSMC_Bank1E_Periph) EACCMOD 

func (p *FSMC_Bank1E_Periph) EACCMOD(n int) RMBWTR

func (*FSMC_Bank1E_Periph) EADDHLD 

func (p *FSMC_Bank1E_Periph) EADDHLD(n int) RMBWTR

func (*FSMC_Bank1E_Periph) EADDSET 

func (p *FSMC_Bank1E_Periph) EADDSET(n int) RMBWTR

func (*FSMC_Bank1E_Periph) ECLKDIV 

func (p *FSMC_Bank1E_Periph) ECLKDIV(n int) RMBWTR

func (*FSMC_Bank1E_Periph) EDATAST 

func (p *FSMC_Bank1E_Periph) EDATAST(n int) RMBWTR

func (*FSMC_Bank1E_Periph) EDATLAT 

func (p *FSMC_Bank1E_Periph) EDATLAT(n int) RMBWTR

type FSMC_Bank1_Periph 

type FSMC_Bank1_Periph struct {
	BTCR [4]RBTCR
}

func (*FSMC_Bank1_Periph) ACCMOD 

func (p *FSMC_Bank1_Periph) ACCMOD(n int) RMBTR

func (*FSMC_Bank1_Periph) ADDHLD 

func (p *FSMC_Bank1_Periph) ADDHLD(n int) RMBTR

func (*FSMC_Bank1_Periph) ADDSET 

func (p *FSMC_Bank1_Periph) ADDSET(n int) RMBTR

func (*FSMC_Bank1_Periph) ASYNCWAIT 

func (p *FSMC_Bank1_Periph) ASYNCWAIT(n int) RMBCR

func (*FSMC_Bank1_Periph) BURSTEN 

func (p *FSMC_Bank1_Periph) BURSTEN(n int) RMBCR

func (*FSMC_Bank1_Periph) BUSTURN 

func (p *FSMC_Bank1_Periph) BUSTURN(n int) RMBTR

func (*FSMC_Bank1_Periph) BaseAddr 

func (p *FSMC_Bank1_Periph) BaseAddr() uintptr

func (*FSMC_Bank1_Periph) CBURSTRW 

func (p *FSMC_Bank1_Periph) CBURSTRW(n int) RMBCR

func (*FSMC_Bank1_Periph) CLKDIV 

func (p *FSMC_Bank1_Periph) CLKDIV(n int) RMBTR

func (*FSMC_Bank1_Periph) DATAST 

func (p *FSMC_Bank1_Periph) DATAST(n int) RMBTR

func (*FSMC_Bank1_Periph) DATLAT 

func (p *FSMC_Bank1_Periph) DATLAT(n int) RMBTR

func (*FSMC_Bank1_Periph) EXTMOD 

func (p *FSMC_Bank1_Periph) EXTMOD(n int) RMBCR

func (*FSMC_Bank1_Periph) FACCEN 

func (p *FSMC_Bank1_Periph) FACCEN(n int) RMBCR

func (*FSMC_Bank1_Periph) MBKEN 

func (p *FSMC_Bank1_Periph) MBKEN(n int) RMBCR

func (*FSMC_Bank1_Periph) MTYP 

func (p *FSMC_Bank1_Periph) MTYP(n int) RMBCR

func (*FSMC_Bank1_Periph) MUXEN 

func (p *FSMC_Bank1_Periph) MUXEN(n int) RMBCR

func (*FSMC_Bank1_Periph) MWID 

func (p *FSMC_Bank1_Periph) MWID(n int) RMBCR

func (*FSMC_Bank1_Periph) WAITCFG 

func (p *FSMC_Bank1_Periph) WAITCFG(n int) RMBCR

func (*FSMC_Bank1_Periph) WAITEN 

func (p *FSMC_Bank1_Periph) WAITEN(n int) RMBCR

func (*FSMC_Bank1_Periph) WAITPOL 

func (p *FSMC_Bank1_Periph) WAITPOL(n int) RMBCR

func (*FSMC_Bank1_Periph) WRAPMOD 

func (p *FSMC_Bank1_Periph) WRAPMOD(n int) RMBCR

func (*FSMC_Bank1_Periph) WREN 

func (p *FSMC_Bank1_Periph) WREN(n int) RMBCR

type FSMC_Bank2_Periph 

type FSMC_Bank2_Periph struct {
	PCR2  RPCR2
	SR2   RSR2
	PMEM2 RPMEM2
	PATT2 RPATT2

	ECCR2 RECCR2
	// contains filtered or unexported fields
}

func (*FSMC_Bank2_Periph) ATTHIZ2 

func (p *FSMC_Bank2_Periph) ATTHIZ2() RMPATT2

func (*FSMC_Bank2_Periph) ATTHOLD2 

func (p *FSMC_Bank2_Periph) ATTHOLD2() RMPATT2

func (*FSMC_Bank2_Periph) ATTSET2 

func (p *FSMC_Bank2_Periph) ATTSET2() RMPATT2

func (*FSMC_Bank2_Periph) ATTWAIT2 

func (p *FSMC_Bank2_Periph) ATTWAIT2() RMPATT2

func (*FSMC_Bank2_Periph) BaseAddr 

func (p *FSMC_Bank2_Periph) BaseAddr() uintptr

func (*FSMC_Bank2_Periph) ECC2 

func (p *FSMC_Bank2_Periph) ECC2() RMECCR2

func (*FSMC_Bank2_Periph) ECCEN 

func (p *FSMC_Bank2_Periph) ECCEN() RMPCR2

func (*FSMC_Bank2_Periph) ECCPS 

func (p *FSMC_Bank2_Periph) ECCPS() RMPCR2

func (*FSMC_Bank2_Periph) FEMPT 

func (p *FSMC_Bank2_Periph) FEMPT() RMSR2

func (*FSMC_Bank2_Periph) IFEN 

func (p *FSMC_Bank2_Periph) IFEN() RMSR2

func (*FSMC_Bank2_Periph) IFS 

func (p *FSMC_Bank2_Periph) IFS() RMSR2

func (*FSMC_Bank2_Periph) ILEN 

func (p *FSMC_Bank2_Periph) ILEN() RMSR2

func (*FSMC_Bank2_Periph) ILS 

func (p *FSMC_Bank2_Periph) ILS() RMSR2

func (*FSMC_Bank2_Periph) IREN 

func (p *FSMC_Bank2_Periph) IREN() RMSR2

func (*FSMC_Bank2_Periph) IRS 

func (p *FSMC_Bank2_Periph) IRS() RMSR2

func (*FSMC_Bank2_Periph) MEMHIZ2 

func (p *FSMC_Bank2_Periph) MEMHIZ2() RMPMEM2

func (*FSMC_Bank2_Periph) MEMHOLD2 

func (p *FSMC_Bank2_Periph) MEMHOLD2() RMPMEM2

func (*FSMC_Bank2_Periph) MEMSET2 

func (p *FSMC_Bank2_Periph) MEMSET2() RMPMEM2

func (*FSMC_Bank2_Periph) MEMWAIT2 

func (p *FSMC_Bank2_Periph) MEMWAIT2() RMPMEM2

func (*FSMC_Bank2_Periph) PBKEN 

func (p *FSMC_Bank2_Periph) PBKEN() RMPCR2

func (*FSMC_Bank2_Periph) PTYP 

func (p *FSMC_Bank2_Periph) PTYP() RMPCR2

func (*FSMC_Bank2_Periph) PWAITEN 

func (p *FSMC_Bank2_Periph) PWAITEN() RMPCR2

func (*FSMC_Bank2_Periph) PWID 

func (p *FSMC_Bank2_Periph) PWID() RMPCR2

func (*FSMC_Bank2_Periph) TAR 

func (p *FSMC_Bank2_Periph) TAR() RMPCR2

func (*FSMC_Bank2_Periph) TCLR 

func (p *FSMC_Bank2_Periph) TCLR() RMPCR2

type FSMC_Bank3_Periph 

type FSMC_Bank3_Periph struct {
	PCR3  RPCR3
	SR3   RSR3
	PMEM3 RPMEM3
	PATT3 RPATT3

	ECCR3 RECCR3
	// contains filtered or unexported fields
}

func (*FSMC_Bank3_Periph) ATTHIZ3 

func (p *FSMC_Bank3_Periph) ATTHIZ3() RMPATT3

func (*FSMC_Bank3_Periph) ATTHOLD3 

func (p *FSMC_Bank3_Periph) ATTHOLD3() RMPATT3

func (*FSMC_Bank3_Periph) ATTSET3 

func (p *FSMC_Bank3_Periph) ATTSET3() RMPATT3

func (*FSMC_Bank3_Periph) ATTWAIT3 

func (p *FSMC_Bank3_Periph) ATTWAIT3() RMPATT3

func (*FSMC_Bank3_Periph) BaseAddr 

func (p *FSMC_Bank3_Periph) BaseAddr() uintptr

func (*FSMC_Bank3_Periph) ECC3 

func (p *FSMC_Bank3_Periph) ECC3() RMECCR3

func (*FSMC_Bank3_Periph) ECCEN 

func (p *FSMC_Bank3_Periph) ECCEN() RMPCR3

func (*FSMC_Bank3_Periph) ECCPS 

func (p *FSMC_Bank3_Periph) ECCPS() RMPCR3

func (*FSMC_Bank3_Periph) FEMPT 

func (p *FSMC_Bank3_Periph) FEMPT() RMSR3

func (*FSMC_Bank3_Periph) IFEN 

func (p *FSMC_Bank3_Periph) IFEN() RMSR3

func (*FSMC_Bank3_Periph) IFS 

func (p *FSMC_Bank3_Periph) IFS() RMSR3

func (*FSMC_Bank3_Periph) ILEN 

func (p *FSMC_Bank3_Periph) ILEN() RMSR3

func (*FSMC_Bank3_Periph) ILS 

func (p *FSMC_Bank3_Periph) ILS() RMSR3

func (*FSMC_Bank3_Periph) IREN 

func (p *FSMC_Bank3_Periph) IREN() RMSR3

func (*FSMC_Bank3_Periph) IRS 

func (p *FSMC_Bank3_Periph) IRS() RMSR3

func (*FSMC_Bank3_Periph) MEMHIZ3 

func (p *FSMC_Bank3_Periph) MEMHIZ3() RMPMEM3

func (*FSMC_Bank3_Periph) MEMHOLD3 

func (p *FSMC_Bank3_Periph) MEMHOLD3() RMPMEM3

func (*FSMC_Bank3_Periph) MEMSET3 

func (p *FSMC_Bank3_Periph) MEMSET3() RMPMEM3

func (*FSMC_Bank3_Periph) MEMWAIT3 

func (p *FSMC_Bank3_Periph) MEMWAIT3() RMPMEM3

func (*FSMC_Bank3_Periph) PBKEN 

func (p *FSMC_Bank3_Periph) PBKEN() RMPCR3

func (*FSMC_Bank3_Periph) PTYP 

func (p *FSMC_Bank3_Periph) PTYP() RMPCR3

func (*FSMC_Bank3_Periph) PWAITEN 

func (p *FSMC_Bank3_Periph) PWAITEN() RMPCR3

func (*FSMC_Bank3_Periph) PWID 

func (p *FSMC_Bank3_Periph) PWID() RMPCR3

func (*FSMC_Bank3_Periph) TAR 

func (p *FSMC_Bank3_Periph) TAR() RMPCR3

func (*FSMC_Bank3_Periph) TCLR 

func (p *FSMC_Bank3_Periph) TCLR() RMPCR3

type FSMC_Bank4_Periph 

type FSMC_Bank4_Periph struct {
	PCR4  RPCR4
	SR4   RSR4
	PMEM4 RPMEM4
	PATT4 RPATT4
	PIO4  RPIO4
}

func (*FSMC_Bank4_Periph) ATTHIZ4 

func (p *FSMC_Bank4_Periph) ATTHIZ4() RMPATT4

func (*FSMC_Bank4_Periph) ATTHOLD4 

func (p *FSMC_Bank4_Periph) ATTHOLD4() RMPATT4

func (*FSMC_Bank4_Periph) ATTSET4 

func (p *FSMC_Bank4_Periph) ATTSET4() RMPATT4

func (*FSMC_Bank4_Periph) ATTWAIT4 

func (p *FSMC_Bank4_Periph) ATTWAIT4() RMPATT4

func (*FSMC_Bank4_Periph) BaseAddr 

func (p *FSMC_Bank4_Periph) BaseAddr() uintptr

func (*FSMC_Bank4_Periph) ECCEN 

func (p *FSMC_Bank4_Periph) ECCEN() RMPCR4

func (*FSMC_Bank4_Periph) ECCPS 

func (p *FSMC_Bank4_Periph) ECCPS() RMPCR4

func (*FSMC_Bank4_Periph) FEMPT 

func (p *FSMC_Bank4_Periph) FEMPT() RMSR4

func (*FSMC_Bank4_Periph) IFEN 

func (p *FSMC_Bank4_Periph) IFEN() RMSR4

func (*FSMC_Bank4_Periph) IFS 

func (p *FSMC_Bank4_Periph) IFS() RMSR4

func (*FSMC_Bank4_Periph) ILEN 

func (p *FSMC_Bank4_Periph) ILEN() RMSR4

func (*FSMC_Bank4_Periph) ILS 

func (p *FSMC_Bank4_Periph) ILS() RMSR4

func (*FSMC_Bank4_Periph) IOHIZ4 

func (p *FSMC_Bank4_Periph) IOHIZ4() RMPIO4

func (*FSMC_Bank4_Periph) IOHOLD4 

func (p *FSMC_Bank4_Periph) IOHOLD4() RMPIO4

func (*FSMC_Bank4_Periph) IOSET4 

func (p *FSMC_Bank4_Periph) IOSET4() RMPIO4

func (*FSMC_Bank4_Periph) IOWAIT4 

func (p *FSMC_Bank4_Periph) IOWAIT4() RMPIO4

func (*FSMC_Bank4_Periph) IREN 

func (p *FSMC_Bank4_Periph) IREN() RMSR4

func (*FSMC_Bank4_Periph) IRS 

func (p *FSMC_Bank4_Periph) IRS() RMSR4

func (*FSMC_Bank4_Periph) MEMHIZ4 

func (p *FSMC_Bank4_Periph) MEMHIZ4() RMPMEM4

func (*FSMC_Bank4_Periph) MEMHOLD4 

func (p *FSMC_Bank4_Periph) MEMHOLD4() RMPMEM4

func (*FSMC_Bank4_Periph) MEMSET4 

func (p *FSMC_Bank4_Periph) MEMSET4() RMPMEM4

func (*FSMC_Bank4_Periph) MEMWAIT4 

func (p *FSMC_Bank4_Periph) MEMWAIT4() RMPMEM4

func (*FSMC_Bank4_Periph) PBKEN 

func (p *FSMC_Bank4_Periph) PBKEN() RMPCR4

func (*FSMC_Bank4_Periph) PTYP 

func (p *FSMC_Bank4_Periph) PTYP() RMPCR4

func (*FSMC_Bank4_Periph) PWAITEN 

func (p *FSMC_Bank4_Periph) PWAITEN() RMPCR4

func (*FSMC_Bank4_Periph) PWID 

func (p *FSMC_Bank4_Periph) PWID() RMPCR4

func (*FSMC_Bank4_Periph) TAR 

func (p *FSMC_Bank4_Periph) TAR() RMPCR4

func (*FSMC_Bank4_Periph) TCLR 

func (p *FSMC_Bank4_Periph) TCLR() RMPCR4

type PATT2 

type PATT2 uint32
const (
	ATTSET2    PATT2 = 0xFF << 0  //+ ATTSET2[7:0] bits (Attribute memory 2 setup time).
	ATTSET2_0  PATT2 = 0x01 << 0  //  Bit 0.
	ATTSET2_1  PATT2 = 0x02 << 0  //  Bit 1.
	ATTSET2_2  PATT2 = 0x04 << 0  //  Bit 2.
	ATTSET2_3  PATT2 = 0x08 << 0  //  Bit 3.
	ATTSET2_4  PATT2 = 0x10 << 0  //  Bit 4.
	ATTSET2_5  PATT2 = 0x20 << 0  //  Bit 5.
	ATTSET2_6  PATT2 = 0x40 << 0  //  Bit 6.
	ATTSET2_7  PATT2 = 0x80 << 0  //  Bit 7.
	ATTWAIT2   PATT2 = 0xFF << 8  //+ ATTWAIT2[7:0] bits (Attribute memory 2 wait time).
	ATTWAIT2_0 PATT2 = 0x01 << 8  //  Bit 0.
	ATTWAIT2_1 PATT2 = 0x02 << 8  //  Bit 1.
	ATTWAIT2_2 PATT2 = 0x04 << 8  //  Bit 2.
	ATTWAIT2_3 PATT2 = 0x08 << 8  //  Bit 3.
	ATTWAIT2_4 PATT2 = 0x10 << 8  //  Bit 4.
	ATTWAIT2_5 PATT2 = 0x20 << 8  //  Bit 5.
	ATTWAIT2_6 PATT2 = 0x40 << 8  //  Bit 6.
	ATTWAIT2_7 PATT2 = 0x80 << 8  //  Bit 7.
	ATTHOLD2   PATT2 = 0xFF << 16 //+ ATTHOLD2[7:0] bits (Attribute memory 2 hold time).
	ATTHOLD2_0 PATT2 = 0x01 << 16 //  Bit 0.
	ATTHOLD2_1 PATT2 = 0x02 << 16 //  Bit 1.
	ATTHOLD2_2 PATT2 = 0x04 << 16 //  Bit 2.
	ATTHOLD2_3 PATT2 = 0x08 << 16 //  Bit 3.
	ATTHOLD2_4 PATT2 = 0x10 << 16 //  Bit 4.
	ATTHOLD2_5 PATT2 = 0x20 << 16 //  Bit 5.
	ATTHOLD2_6 PATT2 = 0x40 << 16 //  Bit 6.
	ATTHOLD2_7 PATT2 = 0x80 << 16 //  Bit 7.
	ATTHIZ2    PATT2 = 0xFF << 24 //+ ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time).
	ATTHIZ2_0  PATT2 = 0x01 << 24 //  Bit 0.
	ATTHIZ2_1  PATT2 = 0x02 << 24 //  Bit 1.
	ATTHIZ2_2  PATT2 = 0x04 << 24 //  Bit 2.
	ATTHIZ2_3  PATT2 = 0x08 << 24 //  Bit 3.
	ATTHIZ2_4  PATT2 = 0x10 << 24 //  Bit 4.
	ATTHIZ2_5  PATT2 = 0x20 << 24 //  Bit 5.
	ATTHIZ2_6  PATT2 = 0x40 << 24 //  Bit 6.
	ATTHIZ2_7  PATT2 = 0x80 << 24 //  Bit 7.
)

func (PATT2) Field 

func (b PATT2) Field(mask PATT2) int

func (PATT2) J 

func (mask PATT2) J(v int) PATT2

type PATT3 

type PATT3 uint32
const (
	ATTSET3    PATT3 = 0xFF << 0  //+ ATTSET3[7:0] bits (Attribute memory 3 setup time).
	ATTSET3_0  PATT3 = 0x01 << 0  //  Bit 0.
	ATTSET3_1  PATT3 = 0x02 << 0  //  Bit 1.
	ATTSET3_2  PATT3 = 0x04 << 0  //  Bit 2.
	ATTSET3_3  PATT3 = 0x08 << 0  //  Bit 3.
	ATTSET3_4  PATT3 = 0x10 << 0  //  Bit 4.
	ATTSET3_5  PATT3 = 0x20 << 0  //  Bit 5.
	ATTSET3_6  PATT3 = 0x40 << 0  //  Bit 6.
	ATTSET3_7  PATT3 = 0x80 << 0  //  Bit 7.
	ATTWAIT3   PATT3 = 0xFF << 8  //+ ATTWAIT3[7:0] bits (Attribute memory 3 wait time).
	ATTWAIT3_0 PATT3 = 0x01 << 8  //  Bit 0.
	ATTWAIT3_1 PATT3 = 0x02 << 8  //  Bit 1.
	ATTWAIT3_2 PATT3 = 0x04 << 8  //  Bit 2.
	ATTWAIT3_3 PATT3 = 0x08 << 8  //  Bit 3.
	ATTWAIT3_4 PATT3 = 0x10 << 8  //  Bit 4.
	ATTWAIT3_5 PATT3 = 0x20 << 8  //  Bit 5.
	ATTWAIT3_6 PATT3 = 0x40 << 8  //  Bit 6.
	ATTWAIT3_7 PATT3 = 0x80 << 8  //  Bit 7.
	ATTHOLD3   PATT3 = 0xFF << 16 //+ ATTHOLD3[7:0] bits (Attribute memory 3 hold time).
	ATTHOLD3_0 PATT3 = 0x01 << 16 //  Bit 0.
	ATTHOLD3_1 PATT3 = 0x02 << 16 //  Bit 1.
	ATTHOLD3_2 PATT3 = 0x04 << 16 //  Bit 2.
	ATTHOLD3_3 PATT3 = 0x08 << 16 //  Bit 3.
	ATTHOLD3_4 PATT3 = 0x10 << 16 //  Bit 4.
	ATTHOLD3_5 PATT3 = 0x20 << 16 //  Bit 5.
	ATTHOLD3_6 PATT3 = 0x40 << 16 //  Bit 6.
	ATTHOLD3_7 PATT3 = 0x80 << 16 //  Bit 7.
	ATTHIZ3    PATT3 = 0xFF << 24 //+ ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time).
	ATTHIZ3_0  PATT3 = 0x01 << 24 //  Bit 0.
	ATTHIZ3_1  PATT3 = 0x02 << 24 //  Bit 1.
	ATTHIZ3_2  PATT3 = 0x04 << 24 //  Bit 2.
	ATTHIZ3_3  PATT3 = 0x08 << 24 //  Bit 3.
	ATTHIZ3_4  PATT3 = 0x10 << 24 //  Bit 4.
	ATTHIZ3_5  PATT3 = 0x20 << 24 //  Bit 5.
	ATTHIZ3_6  PATT3 = 0x40 << 24 //  Bit 6.
	ATTHIZ3_7  PATT3 = 0x80 << 24 //  Bit 7.
)

func (PATT3) Field 

func (b PATT3) Field(mask PATT3) int

func (PATT3) J 

func (mask PATT3) J(v int) PATT3

type PATT4 

type PATT4 uint32
const (
	ATTSET4    PATT4 = 0xFF << 0  //+ ATTSET4[7:0] bits (Attribute memory 4 setup time).
	ATTSET4_0  PATT4 = 0x01 << 0  //  Bit 0.
	ATTSET4_1  PATT4 = 0x02 << 0  //  Bit 1.
	ATTSET4_2  PATT4 = 0x04 << 0  //  Bit 2.
	ATTSET4_3  PATT4 = 0x08 << 0  //  Bit 3.
	ATTSET4_4  PATT4 = 0x10 << 0  //  Bit 4.
	ATTSET4_5  PATT4 = 0x20 << 0  //  Bit 5.
	ATTSET4_6  PATT4 = 0x40 << 0  //  Bit 6.
	ATTSET4_7  PATT4 = 0x80 << 0  //  Bit 7.
	ATTWAIT4   PATT4 = 0xFF << 8  //+ ATTWAIT4[7:0] bits (Attribute memory 4 wait time).
	ATTWAIT4_0 PATT4 = 0x01 << 8  //  Bit 0.
	ATTWAIT4_1 PATT4 = 0x02 << 8  //  Bit 1.
	ATTWAIT4_2 PATT4 = 0x04 << 8  //  Bit 2.
	ATTWAIT4_3 PATT4 = 0x08 << 8  //  Bit 3.
	ATTWAIT4_4 PATT4 = 0x10 << 8  //  Bit 4.
	ATTWAIT4_5 PATT4 = 0x20 << 8  //  Bit 5.
	ATTWAIT4_6 PATT4 = 0x40 << 8  //  Bit 6.
	ATTWAIT4_7 PATT4 = 0x80 << 8  //  Bit 7.
	ATTHOLD4   PATT4 = 0xFF << 16 //+ ATTHOLD4[7:0] bits (Attribute memory 4 hold time).
	ATTHOLD4_0 PATT4 = 0x01 << 16 //  Bit 0.
	ATTHOLD4_1 PATT4 = 0x02 << 16 //  Bit 1.
	ATTHOLD4_2 PATT4 = 0x04 << 16 //  Bit 2.
	ATTHOLD4_3 PATT4 = 0x08 << 16 //  Bit 3.
	ATTHOLD4_4 PATT4 = 0x10 << 16 //  Bit 4.
	ATTHOLD4_5 PATT4 = 0x20 << 16 //  Bit 5.
	ATTHOLD4_6 PATT4 = 0x40 << 16 //  Bit 6.
	ATTHOLD4_7 PATT4 = 0x80 << 16 //  Bit 7.
	ATTHIZ4    PATT4 = 0xFF << 24 //+ ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time).
	ATTHIZ4_0  PATT4 = 0x01 << 24 //  Bit 0.
	ATTHIZ4_1  PATT4 = 0x02 << 24 //  Bit 1.
	ATTHIZ4_2  PATT4 = 0x04 << 24 //  Bit 2.
	ATTHIZ4_3  PATT4 = 0x08 << 24 //  Bit 3.
	ATTHIZ4_4  PATT4 = 0x10 << 24 //  Bit 4.
	ATTHIZ4_5  PATT4 = 0x20 << 24 //  Bit 5.
	ATTHIZ4_6  PATT4 = 0x40 << 24 //  Bit 6.
	ATTHIZ4_7  PATT4 = 0x80 << 24 //  Bit 7.
)

func (PATT4) Field 

func (b PATT4) Field(mask PATT4) int

func (PATT4) J 

func (mask PATT4) J(v int) PATT4

type PCR2 

type PCR2 uint32
const (
	PWAITEN PCR2 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR2 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR2 = 0x01 << 3  //+ Memory type.
	PWID    PCR2 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	PWID_0  PCR2 = 0x01 << 4  //  Bit 0.
	PWID_1  PCR2 = 0x02 << 4  //  Bit 1.
	ECCEN   PCR2 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR2 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TCLR_0  PCR2 = 0x01 << 9  //  Bit 0.
	TCLR_1  PCR2 = 0x02 << 9  //  Bit 1.
	TCLR_2  PCR2 = 0x04 << 9  //  Bit 2.
	TCLR_3  PCR2 = 0x08 << 9  //  Bit 3.
	TAR     PCR2 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	TAR_0   PCR2 = 0x01 << 13 //  Bit 0.
	TAR_1   PCR2 = 0x02 << 13 //  Bit 1.
	TAR_2   PCR2 = 0x04 << 13 //  Bit 2.
	TAR_3   PCR2 = 0x08 << 13 //  Bit 3.
	ECCPS   PCR2 = 0x07 << 17 //+ ECCPS[1:0] bits (ECC page size).
	ECCPS_0 PCR2 = 0x01 << 17 //  Bit 0.
	ECCPS_1 PCR2 = 0x02 << 17 //  Bit 1.
	ECCPS_2 PCR2 = 0x04 << 17 //  Bit 2.
)

func (PCR2) Field 

func (b PCR2) Field(mask PCR2) int

func (PCR2) J 

func (mask PCR2) J(v int) PCR2

type PCR3 

type PCR3 uint32
const (
	PWAITEN PCR3 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR3 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR3 = 0x01 << 3  //+ Memory type.
	PWID    PCR3 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	PWID_0  PCR3 = 0x01 << 4  //  Bit 0.
	PWID_1  PCR3 = 0x02 << 4  //  Bit 1.
	ECCEN   PCR3 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR3 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TCLR_0  PCR3 = 0x01 << 9  //  Bit 0.
	TCLR_1  PCR3 = 0x02 << 9  //  Bit 1.
	TCLR_2  PCR3 = 0x04 << 9  //  Bit 2.
	TCLR_3  PCR3 = 0x08 << 9  //  Bit 3.
	TAR     PCR3 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	TAR_0   PCR3 = 0x01 << 13 //  Bit 0.
	TAR_1   PCR3 = 0x02 << 13 //  Bit 1.
	TAR_2   PCR3 = 0x04 << 13 //  Bit 2.
	TAR_3   PCR3 = 0x08 << 13 //  Bit 3.
	ECCPS   PCR3 = 0x07 << 17 //+ ECCPS[2:0] bits (ECC page size).
	ECCPS_0 PCR3 = 0x01 << 17 //  Bit 0.
	ECCPS_1 PCR3 = 0x02 << 17 //  Bit 1.
	ECCPS_2 PCR3 = 0x04 << 17 //  Bit 2.
)

func (PCR3) Field 

func (b PCR3) Field(mask PCR3) int

func (PCR3) J 

func (mask PCR3) J(v int) PCR3

type PCR4 

type PCR4 uint32
const (
	PWAITEN PCR4 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR4 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR4 = 0x01 << 3  //+ Memory type.
	PWID    PCR4 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	PWID_0  PCR4 = 0x01 << 4  //  Bit 0.
	PWID_1  PCR4 = 0x02 << 4  //  Bit 1.
	ECCEN   PCR4 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR4 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TCLR_0  PCR4 = 0x01 << 9  //  Bit 0.
	TCLR_1  PCR4 = 0x02 << 9  //  Bit 1.
	TCLR_2  PCR4 = 0x04 << 9  //  Bit 2.
	TCLR_3  PCR4 = 0x08 << 9  //  Bit 3.
	TAR     PCR4 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	TAR_0   PCR4 = 0x01 << 13 //  Bit 0.
	TAR_1   PCR4 = 0x02 << 13 //  Bit 1.
	TAR_2   PCR4 = 0x04 << 13 //  Bit 2.
	TAR_3   PCR4 = 0x08 << 13 //  Bit 3.
	ECCPS   PCR4 = 0x07 << 17 //+ ECCPS[2:0] bits (ECC page size).
	ECCPS_0 PCR4 = 0x01 << 17 //  Bit 0.
	ECCPS_1 PCR4 = 0x02 << 17 //  Bit 1.
	ECCPS_2 PCR4 = 0x04 << 17 //  Bit 2.
)

func (PCR4) Field 

func (b PCR4) Field(mask PCR4) int

func (PCR4) J 

func (mask PCR4) J(v int) PCR4

type PIO4 

type PIO4 uint32
const (
	IOSET4    PIO4 = 0xFF << 0  //+ IOSET4[7:0] bits (I/O 4 setup time).
	IOSET4_0  PIO4 = 0x01 << 0  //  Bit 0.
	IOSET4_1  PIO4 = 0x02 << 0  //  Bit 1.
	IOSET4_2  PIO4 = 0x04 << 0  //  Bit 2.
	IOSET4_3  PIO4 = 0x08 << 0  //  Bit 3.
	IOSET4_4  PIO4 = 0x10 << 0  //  Bit 4.
	IOSET4_5  PIO4 = 0x20 << 0  //  Bit 5.
	IOSET4_6  PIO4 = 0x40 << 0  //  Bit 6.
	IOSET4_7  PIO4 = 0x80 << 0  //  Bit 7.
	IOWAIT4   PIO4 = 0xFF << 8  //+ IOWAIT4[7:0] bits (I/O 4 wait time).
	IOWAIT4_0 PIO4 = 0x01 << 8  //  Bit 0.
	IOWAIT4_1 PIO4 = 0x02 << 8  //  Bit 1.
	IOWAIT4_2 PIO4 = 0x04 << 8  //  Bit 2.
	IOWAIT4_3 PIO4 = 0x08 << 8  //  Bit 3.
	IOWAIT4_4 PIO4 = 0x10 << 8  //  Bit 4.
	IOWAIT4_5 PIO4 = 0x20 << 8  //  Bit 5.
	IOWAIT4_6 PIO4 = 0x40 << 8  //  Bit 6.
	IOWAIT4_7 PIO4 = 0x80 << 8  //  Bit 7.
	IOHOLD4   PIO4 = 0xFF << 16 //+ IOHOLD4[7:0] bits (I/O 4 hold time).
	IOHOLD4_0 PIO4 = 0x01 << 16 //  Bit 0.
	IOHOLD4_1 PIO4 = 0x02 << 16 //  Bit 1.
	IOHOLD4_2 PIO4 = 0x04 << 16 //  Bit 2.
	IOHOLD4_3 PIO4 = 0x08 << 16 //  Bit 3.
	IOHOLD4_4 PIO4 = 0x10 << 16 //  Bit 4.
	IOHOLD4_5 PIO4 = 0x20 << 16 //  Bit 5.
	IOHOLD4_6 PIO4 = 0x40 << 16 //  Bit 6.
	IOHOLD4_7 PIO4 = 0x80 << 16 //  Bit 7.
	IOHIZ4    PIO4 = 0xFF << 24 //+ IOHIZ4[7:0] bits (I/O 4 databus HiZ time).
	IOHIZ4_0  PIO4 = 0x01 << 24 //  Bit 0.
	IOHIZ4_1  PIO4 = 0x02 << 24 //  Bit 1.
	IOHIZ4_2  PIO4 = 0x04 << 24 //  Bit 2.
	IOHIZ4_3  PIO4 = 0x08 << 24 //  Bit 3.
	IOHIZ4_4  PIO4 = 0x10 << 24 //  Bit 4.
	IOHIZ4_5  PIO4 = 0x20 << 24 //  Bit 5.
	IOHIZ4_6  PIO4 = 0x40 << 24 //  Bit 6.
	IOHIZ4_7  PIO4 = 0x80 << 24 //  Bit 7.
)

func (PIO4) Field 

func (b PIO4) Field(mask PIO4) int

func (PIO4) J 

func (mask PIO4) J(v int) PIO4

type PMEM2 

type PMEM2 uint32
const (
	MEMSET2    PMEM2 = 0xFF << 0  //+ MEMSET2[7:0] bits (Common memory 2 setup time).
	MEMSET2_0  PMEM2 = 0x01 << 0  //  Bit 0.
	MEMSET2_1  PMEM2 = 0x02 << 0  //  Bit 1.
	MEMSET2_2  PMEM2 = 0x04 << 0  //  Bit 2.
	MEMSET2_3  PMEM2 = 0x08 << 0  //  Bit 3.
	MEMSET2_4  PMEM2 = 0x10 << 0  //  Bit 4.
	MEMSET2_5  PMEM2 = 0x20 << 0  //  Bit 5.
	MEMSET2_6  PMEM2 = 0x40 << 0  //  Bit 6.
	MEMSET2_7  PMEM2 = 0x80 << 0  //  Bit 7.
	MEMWAIT2   PMEM2 = 0xFF << 8  //+ MEMWAIT2[7:0] bits (Common memory 2 wait time).
	MEMWAIT2_0 PMEM2 = 0x01 << 8  //  Bit 0.
	MEMWAIT2_1 PMEM2 = 0x02 << 8  //  Bit 1.
	MEMWAIT2_2 PMEM2 = 0x04 << 8  //  Bit 2.
	MEMWAIT2_3 PMEM2 = 0x08 << 8  //  Bit 3.
	MEMWAIT2_4 PMEM2 = 0x10 << 8  //  Bit 4.
	MEMWAIT2_5 PMEM2 = 0x20 << 8  //  Bit 5.
	MEMWAIT2_6 PMEM2 = 0x40 << 8  //  Bit 6.
	MEMWAIT2_7 PMEM2 = 0x80 << 8  //  Bit 7.
	MEMHOLD2   PMEM2 = 0xFF << 16 //+ MEMHOLD2[7:0] bits (Common memory 2 hold time).
	MEMHOLD2_0 PMEM2 = 0x01 << 16 //  Bit 0.
	MEMHOLD2_1 PMEM2 = 0x02 << 16 //  Bit 1.
	MEMHOLD2_2 PMEM2 = 0x04 << 16 //  Bit 2.
	MEMHOLD2_3 PMEM2 = 0x08 << 16 //  Bit 3.
	MEMHOLD2_4 PMEM2 = 0x10 << 16 //  Bit 4.
	MEMHOLD2_5 PMEM2 = 0x20 << 16 //  Bit 5.
	MEMHOLD2_6 PMEM2 = 0x40 << 16 //  Bit 6.
	MEMHOLD2_7 PMEM2 = 0x80 << 16 //  Bit 7.
	MEMHIZ2    PMEM2 = 0xFF << 24 //+ MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time).
	MEMHIZ2_0  PMEM2 = 0x01 << 24 //  Bit 0.
	MEMHIZ2_1  PMEM2 = 0x02 << 24 //  Bit 1.
	MEMHIZ2_2  PMEM2 = 0x04 << 24 //  Bit 2.
	MEMHIZ2_3  PMEM2 = 0x08 << 24 //  Bit 3.
	MEMHIZ2_4  PMEM2 = 0x10 << 24 //  Bit 4.
	MEMHIZ2_5  PMEM2 = 0x20 << 24 //  Bit 5.
	MEMHIZ2_6  PMEM2 = 0x40 << 24 //  Bit 6.
	MEMHIZ2_7  PMEM2 = 0x80 << 24 //  Bit 7.
)

func (PMEM2) Field 

func (b PMEM2) Field(mask PMEM2) int

func (PMEM2) J 

func (mask PMEM2) J(v int) PMEM2

type PMEM3 

type PMEM3 uint32
const (
	MEMSET3    PMEM3 = 0xFF << 0  //+ MEMSET3[7:0] bits (Common memory 3 setup time).
	MEMSET3_0  PMEM3 = 0x01 << 0  //  Bit 0.
	MEMSET3_1  PMEM3 = 0x02 << 0  //  Bit 1.
	MEMSET3_2  PMEM3 = 0x04 << 0  //  Bit 2.
	MEMSET3_3  PMEM3 = 0x08 << 0  //  Bit 3.
	MEMSET3_4  PMEM3 = 0x10 << 0  //  Bit 4.
	MEMSET3_5  PMEM3 = 0x20 << 0  //  Bit 5.
	MEMSET3_6  PMEM3 = 0x40 << 0  //  Bit 6.
	MEMSET3_7  PMEM3 = 0x80 << 0  //  Bit 7.
	MEMWAIT3   PMEM3 = 0xFF << 8  //+ MEMWAIT3[7:0] bits (Common memory 3 wait time).
	MEMWAIT3_0 PMEM3 = 0x01 << 8  //  Bit 0.
	MEMWAIT3_1 PMEM3 = 0x02 << 8  //  Bit 1.
	MEMWAIT3_2 PMEM3 = 0x04 << 8  //  Bit 2.
	MEMWAIT3_3 PMEM3 = 0x08 << 8  //  Bit 3.
	MEMWAIT3_4 PMEM3 = 0x10 << 8  //  Bit 4.
	MEMWAIT3_5 PMEM3 = 0x20 << 8  //  Bit 5.
	MEMWAIT3_6 PMEM3 = 0x40 << 8  //  Bit 6.
	MEMWAIT3_7 PMEM3 = 0x80 << 8  //  Bit 7.
	MEMHOLD3   PMEM3 = 0xFF << 16 //+ MEMHOLD3[7:0] bits (Common memory 3 hold time).
	MEMHOLD3_0 PMEM3 = 0x01 << 16 //  Bit 0.
	MEMHOLD3_1 PMEM3 = 0x02 << 16 //  Bit 1.
	MEMHOLD3_2 PMEM3 = 0x04 << 16 //  Bit 2.
	MEMHOLD3_3 PMEM3 = 0x08 << 16 //  Bit 3.
	MEMHOLD3_4 PMEM3 = 0x10 << 16 //  Bit 4.
	MEMHOLD3_5 PMEM3 = 0x20 << 16 //  Bit 5.
	MEMHOLD3_6 PMEM3 = 0x40 << 16 //  Bit 6.
	MEMHOLD3_7 PMEM3 = 0x80 << 16 //  Bit 7.
	MEMHIZ3    PMEM3 = 0xFF << 24 //+ MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time).
	MEMHIZ3_0  PMEM3 = 0x01 << 24 //  Bit 0.
	MEMHIZ3_1  PMEM3 = 0x02 << 24 //  Bit 1.
	MEMHIZ3_2  PMEM3 = 0x04 << 24 //  Bit 2.
	MEMHIZ3_3  PMEM3 = 0x08 << 24 //  Bit 3.
	MEMHIZ3_4  PMEM3 = 0x10 << 24 //  Bit 4.
	MEMHIZ3_5  PMEM3 = 0x20 << 24 //  Bit 5.
	MEMHIZ3_6  PMEM3 = 0x40 << 24 //  Bit 6.
	MEMHIZ3_7  PMEM3 = 0x80 << 24 //  Bit 7.
)

func (PMEM3) Field 

func (b PMEM3) Field(mask PMEM3) int

func (PMEM3) J 

func (mask PMEM3) J(v int) PMEM3

type PMEM4 

type PMEM4 uint32
const (
	MEMSET4    PMEM4 = 0xFF << 0  //+ MEMSET4[7:0] bits (Common memory 4 setup time).
	MEMSET4_0  PMEM4 = 0x01 << 0  //  Bit 0.
	MEMSET4_1  PMEM4 = 0x02 << 0  //  Bit 1.
	MEMSET4_2  PMEM4 = 0x04 << 0  //  Bit 2.
	MEMSET4_3  PMEM4 = 0x08 << 0  //  Bit 3.
	MEMSET4_4  PMEM4 = 0x10 << 0  //  Bit 4.
	MEMSET4_5  PMEM4 = 0x20 << 0  //  Bit 5.
	MEMSET4_6  PMEM4 = 0x40 << 0  //  Bit 6.
	MEMSET4_7  PMEM4 = 0x80 << 0  //  Bit 7.
	MEMWAIT4   PMEM4 = 0xFF << 8  //+ MEMWAIT4[7:0] bits (Common memory 4 wait time).
	MEMWAIT4_0 PMEM4 = 0x01 << 8  //  Bit 0.
	MEMWAIT4_1 PMEM4 = 0x02 << 8  //  Bit 1.
	MEMWAIT4_2 PMEM4 = 0x04 << 8  //  Bit 2.
	MEMWAIT4_3 PMEM4 = 0x08 << 8  //  Bit 3.
	MEMWAIT4_4 PMEM4 = 0x10 << 8  //  Bit 4.
	MEMWAIT4_5 PMEM4 = 0x20 << 8  //  Bit 5.
	MEMWAIT4_6 PMEM4 = 0x40 << 8  //  Bit 6.
	MEMWAIT4_7 PMEM4 = 0x80 << 8  //  Bit 7.
	MEMHOLD4   PMEM4 = 0xFF << 16 //+ MEMHOLD4[7:0] bits (Common memory 4 hold time).
	MEMHOLD4_0 PMEM4 = 0x01 << 16 //  Bit 0.
	MEMHOLD4_1 PMEM4 = 0x02 << 16 //  Bit 1.
	MEMHOLD4_2 PMEM4 = 0x04 << 16 //  Bit 2.
	MEMHOLD4_3 PMEM4 = 0x08 << 16 //  Bit 3.
	MEMHOLD4_4 PMEM4 = 0x10 << 16 //  Bit 4.
	MEMHOLD4_5 PMEM4 = 0x20 << 16 //  Bit 5.
	MEMHOLD4_6 PMEM4 = 0x40 << 16 //  Bit 6.
	MEMHOLD4_7 PMEM4 = 0x80 << 16 //  Bit 7.
	MEMHIZ4    PMEM4 = 0xFF << 24 //+ MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time).
	MEMHIZ4_0  PMEM4 = 0x01 << 24 //  Bit 0.
	MEMHIZ4_1  PMEM4 = 0x02 << 24 //  Bit 1.
	MEMHIZ4_2  PMEM4 = 0x04 << 24 //  Bit 2.
	MEMHIZ4_3  PMEM4 = 0x08 << 24 //  Bit 3.
	MEMHIZ4_4  PMEM4 = 0x10 << 24 //  Bit 4.
	MEMHIZ4_5  PMEM4 = 0x20 << 24 //  Bit 5.
	MEMHIZ4_6  PMEM4 = 0x40 << 24 //  Bit 6.
	MEMHIZ4_7  PMEM4 = 0x80 << 24 //  Bit 7.
)

func (PMEM4) Field 

func (b PMEM4) Field(mask PMEM4) int

func (PMEM4) J 

func (mask PMEM4) J(v int) PMEM4

type RBCR 

type RBCR struct{ mmio.U32 }

func (*RBCR) AtomicClearBits 

func (r *RBCR) AtomicClearBits(mask BCR)

func (*RBCR) AtomicSetBits 

func (r *RBCR) AtomicSetBits(mask BCR)

func (*RBCR) AtomicStoreBits 

func (r *RBCR) AtomicStoreBits(mask, b BCR)

func (*RBCR) Bits 

func (r *RBCR) Bits(mask BCR) BCR

func (*RBCR) ClearBits 

func (r *RBCR) ClearBits(mask BCR)

func (*RBCR) Load 

func (r *RBCR) Load() BCR

func (*RBCR) SetBits 

func (r *RBCR) SetBits(mask BCR)

func (*RBCR) Store 

func (r *RBCR) Store(b BCR)

func (*RBCR) StoreBits 

func (r *RBCR) StoreBits(mask, b BCR)

type RBTCR 

type RBTCR struct {
	BCR RBCR
	BTR RBTR
}

type RBTR 

type RBTR struct{ mmio.U32 }

func (*RBTR) AtomicClearBits 

func (r *RBTR) AtomicClearBits(mask BTR)

func (*RBTR) AtomicSetBits 

func (r *RBTR) AtomicSetBits(mask BTR)

func (*RBTR) AtomicStoreBits 

func (r *RBTR) AtomicStoreBits(mask, b BTR)

func (*RBTR) Bits 

func (r *RBTR) Bits(mask BTR) BTR

func (*RBTR) ClearBits 

func (r *RBTR) ClearBits(mask BTR)

func (*RBTR) Load 

func (r *RBTR) Load() BTR

func (*RBTR) SetBits 

func (r *RBTR) SetBits(mask BTR)

func (*RBTR) Store 

func (r *RBTR) Store(b BTR)

func (*RBTR) StoreBits 

func (r *RBTR) StoreBits(mask, b BTR)

type RBWTR 

type RBWTR struct{ mmio.U32 }

func (*RBWTR) AtomicClearBits 

func (r *RBWTR) AtomicClearBits(mask BWTR)

func (*RBWTR) AtomicSetBits 

func (r *RBWTR) AtomicSetBits(mask BWTR)

func (*RBWTR) AtomicStoreBits 

func (r *RBWTR) AtomicStoreBits(mask, b BWTR)

func (*RBWTR) Bits 

func (r *RBWTR) Bits(mask BWTR) BWTR

func (*RBWTR) ClearBits 

func (r *RBWTR) ClearBits(mask BWTR)

func (*RBWTR) Load 

func (r *RBWTR) Load() BWTR

func (*RBWTR) SetBits 

func (r *RBWTR) SetBits(mask BWTR)

func (*RBWTR) Store 

func (r *RBWTR) Store(b BWTR)

func (*RBWTR) StoreBits 

func (r *RBWTR) StoreBits(mask, b BWTR)

type RECCR2 

type RECCR2 struct{ mmio.U32 }

func (*RECCR2) AtomicClearBits 

func (r *RECCR2) AtomicClearBits(mask ECCR2)

func (*RECCR2) AtomicSetBits 

func (r *RECCR2) AtomicSetBits(mask ECCR2)

func (*RECCR2) AtomicStoreBits 

func (r *RECCR2) AtomicStoreBits(mask, b ECCR2)

func (*RECCR2) Bits 

func (r *RECCR2) Bits(mask ECCR2) ECCR2

func (*RECCR2) ClearBits 

func (r *RECCR2) ClearBits(mask ECCR2)

func (*RECCR2) Load 

func (r *RECCR2) Load() ECCR2

func (*RECCR2) SetBits 

func (r *RECCR2) SetBits(mask ECCR2)

func (*RECCR2) Store 

func (r *RECCR2) Store(b ECCR2)

func (*RECCR2) StoreBits 

func (r *RECCR2) StoreBits(mask, b ECCR2)

type RECCR3 

type RECCR3 struct{ mmio.U32 }

func (*RECCR3) AtomicClearBits 

func (r *RECCR3) AtomicClearBits(mask ECCR3)

func (*RECCR3) AtomicSetBits 

func (r *RECCR3) AtomicSetBits(mask ECCR3)

func (*RECCR3) AtomicStoreBits 

func (r *RECCR3) AtomicStoreBits(mask, b ECCR3)

func (*RECCR3) Bits 

func (r *RECCR3) Bits(mask ECCR3) ECCR3

func (*RECCR3) ClearBits 

func (r *RECCR3) ClearBits(mask ECCR3)

func (*RECCR3) Load 

func (r *RECCR3) Load() ECCR3

func (*RECCR3) SetBits 

func (r *RECCR3) SetBits(mask ECCR3)

func (*RECCR3) Store 

func (r *RECCR3) Store(b ECCR3)

func (*RECCR3) StoreBits 

func (r *RECCR3) StoreBits(mask, b ECCR3)

type RMBCR 

type RMBCR struct{ mmio.UM32 }

func (RMBCR) Load 

func (rm RMBCR) Load() BCR

func (RMBCR) Store 

func (rm RMBCR) Store(b BCR)

type RMBTR 

type RMBTR struct{ mmio.UM32 }

func (RMBTR) Load 

func (rm RMBTR) Load() BTR

func (RMBTR) Store 

func (rm RMBTR) Store(b BTR)

type RMBWTR 

type RMBWTR struct{ mmio.UM32 }

func (RMBWTR) Load 

func (rm RMBWTR) Load() BWTR

func (RMBWTR) Store 

func (rm RMBWTR) Store(b BWTR)

type RMECCR2 

type RMECCR2 struct{ mmio.UM32 }

func (RMECCR2) Load 

func (rm RMECCR2) Load() ECCR2

func (RMECCR2) Store 

func (rm RMECCR2) Store(b ECCR2)

type RMECCR3 

type RMECCR3 struct{ mmio.UM32 }

func (RMECCR3) Load 

func (rm RMECCR3) Load() ECCR3

func (RMECCR3) Store 

func (rm RMECCR3) Store(b ECCR3)

type RMPATT2 

type RMPATT2 struct{ mmio.UM32 }

func (RMPATT2) Load 

func (rm RMPATT2) Load() PATT2

func (RMPATT2) Store 

func (rm RMPATT2) Store(b PATT2)

type RMPATT3 

type RMPATT3 struct{ mmio.UM32 }

func (RMPATT3) Load 

func (rm RMPATT3) Load() PATT3

func (RMPATT3) Store 

func (rm RMPATT3) Store(b PATT3)

type RMPATT4 

type RMPATT4 struct{ mmio.UM32 }

func (RMPATT4) Load 

func (rm RMPATT4) Load() PATT4

func (RMPATT4) Store 

func (rm RMPATT4) Store(b PATT4)

type RMPCR2 

type RMPCR2 struct{ mmio.UM32 }

func (RMPCR2) Load 

func (rm RMPCR2) Load() PCR2

func (RMPCR2) Store 

func (rm RMPCR2) Store(b PCR2)

type RMPCR3 

type RMPCR3 struct{ mmio.UM32 }

func (RMPCR3) Load 

func (rm RMPCR3) Load() PCR3

func (RMPCR3) Store 

func (rm RMPCR3) Store(b PCR3)

type RMPCR4 

type RMPCR4 struct{ mmio.UM32 }

func (RMPCR4) Load 

func (rm RMPCR4) Load() PCR4

func (RMPCR4) Store 

func (rm RMPCR4) Store(b PCR4)

type RMPIO4 

type RMPIO4 struct{ mmio.UM32 }

func (RMPIO4) Load 

func (rm RMPIO4) Load() PIO4

func (RMPIO4) Store 

func (rm RMPIO4) Store(b PIO4)

type RMPMEM2 

type RMPMEM2 struct{ mmio.UM32 }

func (RMPMEM2) Load 

func (rm RMPMEM2) Load() PMEM2

func (RMPMEM2) Store 

func (rm RMPMEM2) Store(b PMEM2)

type RMPMEM3 

type RMPMEM3 struct{ mmio.UM32 }

func (RMPMEM3) Load 

func (rm RMPMEM3) Load() PMEM3

func (RMPMEM3) Store 

func (rm RMPMEM3) Store(b PMEM3)

type RMPMEM4 

type RMPMEM4 struct{ mmio.UM32 }

func (RMPMEM4) Load 

func (rm RMPMEM4) Load() PMEM4

func (RMPMEM4) Store 

func (rm RMPMEM4) Store(b PMEM4)

type RMSR2 

type RMSR2 struct{ mmio.UM32 }

func (RMSR2) Load 

func (rm RMSR2) Load() SR2

func (RMSR2) Store 

func (rm RMSR2) Store(b SR2)

type RMSR3 

type RMSR3 struct{ mmio.UM32 }

func (RMSR3) Load 

func (rm RMSR3) Load() SR3

func (RMSR3) Store 

func (rm RMSR3) Store(b SR3)

type RMSR4 

type RMSR4 struct{ mmio.UM32 }

func (RMSR4) Load 

func (rm RMSR4) Load() SR4

func (RMSR4) Store 

func (rm RMSR4) Store(b SR4)

type RPATT2 

type RPATT2 struct{ mmio.U32 }

func (*RPATT2) AtomicClearBits 

func (r *RPATT2) AtomicClearBits(mask PATT2)

func (*RPATT2) AtomicSetBits 

func (r *RPATT2) AtomicSetBits(mask PATT2)

func (*RPATT2) AtomicStoreBits 

func (r *RPATT2) AtomicStoreBits(mask, b PATT2)

func (*RPATT2) Bits 

func (r *RPATT2) Bits(mask PATT2) PATT2

func (*RPATT2) ClearBits 

func (r *RPATT2) ClearBits(mask PATT2)

func (*RPATT2) Load 

func (r *RPATT2) Load() PATT2

func (*RPATT2) SetBits 

func (r *RPATT2) SetBits(mask PATT2)

func (*RPATT2) Store 

func (r *RPATT2) Store(b PATT2)

func (*RPATT2) StoreBits 

func (r *RPATT2) StoreBits(mask, b PATT2)

type RPATT3 

type RPATT3 struct{ mmio.U32 }

func (*RPATT3) AtomicClearBits 

func (r *RPATT3) AtomicClearBits(mask PATT3)

func (*RPATT3) AtomicSetBits 

func (r *RPATT3) AtomicSetBits(mask PATT3)

func (*RPATT3) AtomicStoreBits 

func (r *RPATT3) AtomicStoreBits(mask, b PATT3)

func (*RPATT3) Bits 

func (r *RPATT3) Bits(mask PATT3) PATT3

func (*RPATT3) ClearBits 

func (r *RPATT3) ClearBits(mask PATT3)

func (*RPATT3) Load 

func (r *RPATT3) Load() PATT3

func (*RPATT3) SetBits 

func (r *RPATT3) SetBits(mask PATT3)

func (*RPATT3) Store 

func (r *RPATT3) Store(b PATT3)

func (*RPATT3) StoreBits 

func (r *RPATT3) StoreBits(mask, b PATT3)

type RPATT4 

type RPATT4 struct{ mmio.U32 }

func (*RPATT4) AtomicClearBits 

func (r *RPATT4) AtomicClearBits(mask PATT4)

func (*RPATT4) AtomicSetBits 

func (r *RPATT4) AtomicSetBits(mask PATT4)

func (*RPATT4) AtomicStoreBits 

func (r *RPATT4) AtomicStoreBits(mask, b PATT4)

func (*RPATT4) Bits 

func (r *RPATT4) Bits(mask PATT4) PATT4

func (*RPATT4) ClearBits 

func (r *RPATT4) ClearBits(mask PATT4)

func (*RPATT4) Load 

func (r *RPATT4) Load() PATT4

func (*RPATT4) SetBits 

func (r *RPATT4) SetBits(mask PATT4)

func (*RPATT4) Store 

func (r *RPATT4) Store(b PATT4)

func (*RPATT4) StoreBits 

func (r *RPATT4) StoreBits(mask, b PATT4)

type RPCR2 

type RPCR2 struct{ mmio.U32 }

func (*RPCR2) AtomicClearBits 

func (r *RPCR2) AtomicClearBits(mask PCR2)

func (*RPCR2) AtomicSetBits 

func (r *RPCR2) AtomicSetBits(mask PCR2)

func (*RPCR2) AtomicStoreBits 

func (r *RPCR2) AtomicStoreBits(mask, b PCR2)

func (*RPCR2) Bits 

func (r *RPCR2) Bits(mask PCR2) PCR2

func (*RPCR2) ClearBits 

func (r *RPCR2) ClearBits(mask PCR2)

func (*RPCR2) Load 

func (r *RPCR2) Load() PCR2

func (*RPCR2) SetBits 

func (r *RPCR2) SetBits(mask PCR2)

func (*RPCR2) Store 

func (r *RPCR2) Store(b PCR2)

func (*RPCR2) StoreBits 

func (r *RPCR2) StoreBits(mask, b PCR2)

type RPCR3 

type RPCR3 struct{ mmio.U32 }

func (*RPCR3) AtomicClearBits 

func (r *RPCR3) AtomicClearBits(mask PCR3)

func (*RPCR3) AtomicSetBits 

func (r *RPCR3) AtomicSetBits(mask PCR3)

func (*RPCR3) AtomicStoreBits 

func (r *RPCR3) AtomicStoreBits(mask, b PCR3)

func (*RPCR3) Bits 

func (r *RPCR3) Bits(mask PCR3) PCR3

func (*RPCR3) ClearBits 

func (r *RPCR3) ClearBits(mask PCR3)

func (*RPCR3) Load 

func (r *RPCR3) Load() PCR3

func (*RPCR3) SetBits 

func (r *RPCR3) SetBits(mask PCR3)

func (*RPCR3) Store 

func (r *RPCR3) Store(b PCR3)

func (*RPCR3) StoreBits 

func (r *RPCR3) StoreBits(mask, b PCR3)

type RPCR4 

type RPCR4 struct{ mmio.U32 }

func (*RPCR4) AtomicClearBits 

func (r *RPCR4) AtomicClearBits(mask PCR4)

func (*RPCR4) AtomicSetBits 

func (r *RPCR4) AtomicSetBits(mask PCR4)

func (*RPCR4) AtomicStoreBits 

func (r *RPCR4) AtomicStoreBits(mask, b PCR4)

func (*RPCR4) Bits 

func (r *RPCR4) Bits(mask PCR4) PCR4

func (*RPCR4) ClearBits 

func (r *RPCR4) ClearBits(mask PCR4)

func (*RPCR4) Load 

func (r *RPCR4) Load() PCR4

func (*RPCR4) SetBits 

func (r *RPCR4) SetBits(mask PCR4)

func (*RPCR4) Store 

func (r *RPCR4) Store(b PCR4)

func (*RPCR4) StoreBits 

func (r *RPCR4) StoreBits(mask, b PCR4)

type RPIO4 

type RPIO4 struct{ mmio.U32 }

func (*RPIO4) AtomicClearBits 

func (r *RPIO4) AtomicClearBits(mask PIO4)

func (*RPIO4) AtomicSetBits 

func (r *RPIO4) AtomicSetBits(mask PIO4)

func (*RPIO4) AtomicStoreBits 

func (r *RPIO4) AtomicStoreBits(mask, b PIO4)

func (*RPIO4) Bits 

func (r *RPIO4) Bits(mask PIO4) PIO4

func (*RPIO4) ClearBits 

func (r *RPIO4) ClearBits(mask PIO4)

func (*RPIO4) Load 

func (r *RPIO4) Load() PIO4

func (*RPIO4) SetBits 

func (r *RPIO4) SetBits(mask PIO4)

func (*RPIO4) Store 

func (r *RPIO4) Store(b PIO4)

func (*RPIO4) StoreBits 

func (r *RPIO4) StoreBits(mask, b PIO4)

type RPMEM2 

type RPMEM2 struct{ mmio.U32 }

func (*RPMEM2) AtomicClearBits 

func (r *RPMEM2) AtomicClearBits(mask PMEM2)

func (*RPMEM2) AtomicSetBits 

func (r *RPMEM2) AtomicSetBits(mask PMEM2)

func (*RPMEM2) AtomicStoreBits 

func (r *RPMEM2) AtomicStoreBits(mask, b PMEM2)

func (*RPMEM2) Bits 

func (r *RPMEM2) Bits(mask PMEM2) PMEM2

func (*RPMEM2) ClearBits 

func (r *RPMEM2) ClearBits(mask PMEM2)

func (*RPMEM2) Load 

func (r *RPMEM2) Load() PMEM2

func (*RPMEM2) SetBits 

func (r *RPMEM2) SetBits(mask PMEM2)

func (*RPMEM2) Store 

func (r *RPMEM2) Store(b PMEM2)

func (*RPMEM2) StoreBits 

func (r *RPMEM2) StoreBits(mask, b PMEM2)

type RPMEM3 

type RPMEM3 struct{ mmio.U32 }

func (*RPMEM3) AtomicClearBits 

func (r *RPMEM3) AtomicClearBits(mask PMEM3)

func (*RPMEM3) AtomicSetBits 

func (r *RPMEM3) AtomicSetBits(mask PMEM3)

func (*RPMEM3) AtomicStoreBits 

func (r *RPMEM3) AtomicStoreBits(mask, b PMEM3)

func (*RPMEM3) Bits 

func (r *RPMEM3) Bits(mask PMEM3) PMEM3

func (*RPMEM3) ClearBits 

func (r *RPMEM3) ClearBits(mask PMEM3)

func (*RPMEM3) Load 

func (r *RPMEM3) Load() PMEM3

func (*RPMEM3) SetBits 

func (r *RPMEM3) SetBits(mask PMEM3)

func (*RPMEM3) Store 

func (r *RPMEM3) Store(b PMEM3)

func (*RPMEM3) StoreBits 

func (r *RPMEM3) StoreBits(mask, b PMEM3)

type RPMEM4 

type RPMEM4 struct{ mmio.U32 }

func (*RPMEM4) AtomicClearBits 

func (r *RPMEM4) AtomicClearBits(mask PMEM4)

func (*RPMEM4) AtomicSetBits 

func (r *RPMEM4) AtomicSetBits(mask PMEM4)

func (*RPMEM4) AtomicStoreBits 

func (r *RPMEM4) AtomicStoreBits(mask, b PMEM4)

func (*RPMEM4) Bits 

func (r *RPMEM4) Bits(mask PMEM4) PMEM4

func (*RPMEM4) ClearBits 

func (r *RPMEM4) ClearBits(mask PMEM4)

func (*RPMEM4) Load 

func (r *RPMEM4) Load() PMEM4

func (*RPMEM4) SetBits 

func (r *RPMEM4) SetBits(mask PMEM4)

func (*RPMEM4) Store 

func (r *RPMEM4) Store(b PMEM4)

func (*RPMEM4) StoreBits 

func (r *RPMEM4) StoreBits(mask, b PMEM4)

type RSR2 

type RSR2 struct{ mmio.U32 }

func (*RSR2) AtomicClearBits 

func (r *RSR2) AtomicClearBits(mask SR2)

func (*RSR2) AtomicSetBits 

func (r *RSR2) AtomicSetBits(mask SR2)

func (*RSR2) AtomicStoreBits 

func (r *RSR2) AtomicStoreBits(mask, b SR2)

func (*RSR2) Bits 

func (r *RSR2) Bits(mask SR2) SR2

func (*RSR2) ClearBits 

func (r *RSR2) ClearBits(mask SR2)

func (*RSR2) Load 

func (r *RSR2) Load() SR2

func (*RSR2) SetBits 

func (r *RSR2) SetBits(mask SR2)

func (*RSR2) Store 

func (r *RSR2) Store(b SR2)

func (*RSR2) StoreBits 

func (r *RSR2) StoreBits(mask, b SR2)

type RSR3 

type RSR3 struct{ mmio.U32 }

func (*RSR3) AtomicClearBits 

func (r *RSR3) AtomicClearBits(mask SR3)

func (*RSR3) AtomicSetBits 

func (r *RSR3) AtomicSetBits(mask SR3)

func (*RSR3) AtomicStoreBits 

func (r *RSR3) AtomicStoreBits(mask, b SR3)

func (*RSR3) Bits 

func (r *RSR3) Bits(mask SR3) SR3

func (*RSR3) ClearBits 

func (r *RSR3) ClearBits(mask SR3)

func (*RSR3) Load 

func (r *RSR3) Load() SR3

func (*RSR3) SetBits 

func (r *RSR3) SetBits(mask SR3)

func (*RSR3) Store 

func (r *RSR3) Store(b SR3)

func (*RSR3) StoreBits 

func (r *RSR3) StoreBits(mask, b SR3)

type RSR4 

type RSR4 struct{ mmio.U32 }

func (*RSR4) AtomicClearBits 

func (r *RSR4) AtomicClearBits(mask SR4)

func (*RSR4) AtomicSetBits 

func (r *RSR4) AtomicSetBits(mask SR4)

func (*RSR4) AtomicStoreBits 

func (r *RSR4) AtomicStoreBits(mask, b SR4)

func (*RSR4) Bits 

func (r *RSR4) Bits(mask SR4) SR4

func (*RSR4) ClearBits 

func (r *RSR4) ClearBits(mask SR4)

func (*RSR4) Load 

func (r *RSR4) Load() SR4

func (*RSR4) SetBits 

func (r *RSR4) SetBits(mask SR4)

func (*RSR4) Store 

func (r *RSR4) Store(b SR4)

func (*RSR4) StoreBits 

func (r *RSR4) StoreBits(mask, b SR4)

type SR2 

type SR2 uint32
const (
	IRS   SR2 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR2 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR2 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR2 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR2 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR2 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR2 = 0x01 << 6 //+ FIFO empty.
)

func (SR2) Field 

func (b SR2) Field(mask SR2) int

func (SR2) J 

func (mask SR2) J(v int) SR2

type SR3 

type SR3 uint32
const (
	IRS   SR3 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR3 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR3 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR3 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR3 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR3 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR3 = 0x01 << 6 //+ FIFO empty.
)

func (SR3) Field 

func (b SR3) Field(mask SR3) int

func (SR3) J 

func (mask SR3) J(v int) SR3

type SR4 

type SR4 uint32
const (
	IRS   SR4 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR4 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR4 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR4 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR4 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR4 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR4 = 0x01 << 6 //+ FIFO empty.
)

func (SR4) Field 

func (b SR4) Field(mask SR4) int

func (SR4) J 

func (mask SR4) J(v int) SR4

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