Documentation
¶
Overview ¶
Package rcc provides interface to Reset and Clock Control.
Peripheral: RCC_Periph Reset and Clock Control. Instances:
RCC mmap.RCC_BASE
Registers:
0x00 32 CR Clock control register. 0x04 32 CFGR Clock configuration register. 0x08 32 CIR Clock interrupt register. 0x0C 32 APB2RSTR APB2 peripheral reset register. 0x10 32 APB1RSTR APB1 peripheral reset register. 0x14 32 AHBENR AHB peripheral clock register. 0x18 32 APB2ENR APB2 peripheral clock enable register. 0x1C 32 APB1ENR APB1 peripheral clock enable register. 0x20 32 BDCR Backup domain control register. 0x24 32 CSR Clock control & status register. 0x28 32 AHBRSTR AHB peripheral reset register. 0x2C 32 CFGR2 Clock configuration register 2. 0x30 32 CFGR3 Clock configuration register 3. 0x34 32 CR2 Clock control register 2.
Import:
stm32/o/f030x6/mmap
Index ¶
- Constants
- Variables
- type AHBENR
- type AHBRSTR
- type APB1ENR
- type APB1RSTR
- type APB2ENR
- type APB2RSTR
- type BDCR
- type CFGR
- type CFGR2
- type CFGR3
- type CIR
- type CR
- type CR2
- type CSR
- type RAHBENR
- func (r *RAHBENR) AtomicClearBits(mask AHBENR)
- func (r *RAHBENR) AtomicSetBits(mask AHBENR)
- func (r *RAHBENR) AtomicStoreBits(mask, b AHBENR)
- func (r *RAHBENR) Bits(mask AHBENR) AHBENR
- func (r *RAHBENR) ClearBits(mask AHBENR)
- func (r *RAHBENR) Load() AHBENR
- func (r *RAHBENR) SetBits(mask AHBENR)
- func (r *RAHBENR) Store(b AHBENR)
- func (r *RAHBENR) StoreBits(mask, b AHBENR)
- type RAHBRSTR
- func (r *RAHBRSTR) AtomicClearBits(mask AHBRSTR)
- func (r *RAHBRSTR) AtomicSetBits(mask AHBRSTR)
- func (r *RAHBRSTR) AtomicStoreBits(mask, b AHBRSTR)
- func (r *RAHBRSTR) Bits(mask AHBRSTR) AHBRSTR
- func (r *RAHBRSTR) ClearBits(mask AHBRSTR)
- func (r *RAHBRSTR) Load() AHBRSTR
- func (r *RAHBRSTR) SetBits(mask AHBRSTR)
- func (r *RAHBRSTR) Store(b AHBRSTR)
- func (r *RAHBRSTR) StoreBits(mask, b AHBRSTR)
- type RAPB1ENR
- func (r *RAPB1ENR) AtomicClearBits(mask APB1ENR)
- func (r *RAPB1ENR) AtomicSetBits(mask APB1ENR)
- func (r *RAPB1ENR) AtomicStoreBits(mask, b APB1ENR)
- func (r *RAPB1ENR) Bits(mask APB1ENR) APB1ENR
- func (r *RAPB1ENR) ClearBits(mask APB1ENR)
- func (r *RAPB1ENR) Load() APB1ENR
- func (r *RAPB1ENR) SetBits(mask APB1ENR)
- func (r *RAPB1ENR) Store(b APB1ENR)
- func (r *RAPB1ENR) StoreBits(mask, b APB1ENR)
- type RAPB1RSTR
- func (r *RAPB1RSTR) AtomicClearBits(mask APB1RSTR)
- func (r *RAPB1RSTR) AtomicSetBits(mask APB1RSTR)
- func (r *RAPB1RSTR) AtomicStoreBits(mask, b APB1RSTR)
- func (r *RAPB1RSTR) Bits(mask APB1RSTR) APB1RSTR
- func (r *RAPB1RSTR) ClearBits(mask APB1RSTR)
- func (r *RAPB1RSTR) Load() APB1RSTR
- func (r *RAPB1RSTR) SetBits(mask APB1RSTR)
- func (r *RAPB1RSTR) Store(b APB1RSTR)
- func (r *RAPB1RSTR) StoreBits(mask, b APB1RSTR)
- type RAPB2ENR
- func (r *RAPB2ENR) AtomicClearBits(mask APB2ENR)
- func (r *RAPB2ENR) AtomicSetBits(mask APB2ENR)
- func (r *RAPB2ENR) AtomicStoreBits(mask, b APB2ENR)
- func (r *RAPB2ENR) Bits(mask APB2ENR) APB2ENR
- func (r *RAPB2ENR) ClearBits(mask APB2ENR)
- func (r *RAPB2ENR) Load() APB2ENR
- func (r *RAPB2ENR) SetBits(mask APB2ENR)
- func (r *RAPB2ENR) Store(b APB2ENR)
- func (r *RAPB2ENR) StoreBits(mask, b APB2ENR)
- type RAPB2RSTR
- func (r *RAPB2RSTR) AtomicClearBits(mask APB2RSTR)
- func (r *RAPB2RSTR) AtomicSetBits(mask APB2RSTR)
- func (r *RAPB2RSTR) AtomicStoreBits(mask, b APB2RSTR)
- func (r *RAPB2RSTR) Bits(mask APB2RSTR) APB2RSTR
- func (r *RAPB2RSTR) ClearBits(mask APB2RSTR)
- func (r *RAPB2RSTR) Load() APB2RSTR
- func (r *RAPB2RSTR) SetBits(mask APB2RSTR)
- func (r *RAPB2RSTR) Store(b APB2RSTR)
- func (r *RAPB2RSTR) StoreBits(mask, b APB2RSTR)
- type RBDCR
- func (r *RBDCR) AtomicClearBits(mask BDCR)
- func (r *RBDCR) AtomicSetBits(mask BDCR)
- func (r *RBDCR) AtomicStoreBits(mask, b BDCR)
- func (r *RBDCR) Bits(mask BDCR) BDCR
- func (r *RBDCR) ClearBits(mask BDCR)
- func (r *RBDCR) Load() BDCR
- func (r *RBDCR) SetBits(mask BDCR)
- func (r *RBDCR) Store(b BDCR)
- func (r *RBDCR) StoreBits(mask, b BDCR)
- type RCC_Periph
- func (p *RCC_Periph) ADCEN() RMAPB2ENR
- func (p *RCC_Periph) ADCPRE() RMCFGR
- func (p *RCC_Periph) ADCRST() RMAPB2RSTR
- func (p *RCC_Periph) BDRST() RMBDCR
- func (p *RCC_Periph) BaseAddr() uintptr
- func (p *RCC_Periph) CRCEN() RMAHBENR
- func (p *RCC_Periph) CSSC() RMCIR
- func (p *RCC_Periph) CSSF() RMCIR
- func (p *RCC_Periph) CSSON() RMCR
- func (p *RCC_Periph) DBGMCUEN() RMAPB2ENR
- func (p *RCC_Periph) DBGMCURST() RMAPB2RSTR
- func (p *RCC_Periph) DMAEN() RMAHBENR
- func (p *RCC_Periph) FLITFEN() RMAHBENR
- func (p *RCC_Periph) GPIOAEN() RMAHBENR
- func (p *RCC_Periph) GPIOARST() RMAHBRSTR
- func (p *RCC_Periph) GPIOBEN() RMAHBENR
- func (p *RCC_Periph) GPIOBRST() RMAHBRSTR
- func (p *RCC_Periph) GPIOCEN() RMAHBENR
- func (p *RCC_Periph) GPIOCRST() RMAHBRSTR
- func (p *RCC_Periph) GPIODEN() RMAHBENR
- func (p *RCC_Periph) GPIODRST() RMAHBRSTR
- func (p *RCC_Periph) GPIOFEN() RMAHBENR
- func (p *RCC_Periph) GPIOFRST() RMAHBRSTR
- func (p *RCC_Periph) HPRE() RMCFGR
- func (p *RCC_Periph) HSEBYP() RMCR
- func (p *RCC_Periph) HSEON() RMCR
- func (p *RCC_Periph) HSERDY() RMCR
- func (p *RCC_Periph) HSERDYC() RMCIR
- func (p *RCC_Periph) HSERDYF() RMCIR
- func (p *RCC_Periph) HSERDYIE() RMCIR
- func (p *RCC_Periph) HSI14CAL() RMCR2
- func (p *RCC_Periph) HSI14DIS() RMCR2
- func (p *RCC_Periph) HSI14ON() RMCR2
- func (p *RCC_Periph) HSI14RDY() RMCR2
- func (p *RCC_Periph) HSI14RDYC() RMCIR
- func (p *RCC_Periph) HSI14RDYF() RMCIR
- func (p *RCC_Periph) HSI14RDYIE() RMCIR
- func (p *RCC_Periph) HSI14TRIM() RMCR2
- func (p *RCC_Periph) HSICAL() RMCR
- func (p *RCC_Periph) HSION() RMCR
- func (p *RCC_Periph) HSIRDY() RMCR
- func (p *RCC_Periph) HSIRDYC() RMCIR
- func (p *RCC_Periph) HSIRDYF() RMCIR
- func (p *RCC_Periph) HSIRDYIE() RMCIR
- func (p *RCC_Periph) HSITRIM() RMCR
- func (p *RCC_Periph) I2C1EN() RMAPB1ENR
- func (p *RCC_Periph) I2C1RST() RMAPB1RSTR
- func (p *RCC_Periph) I2C1SW() RMCFGR3
- func (p *RCC_Periph) IWDGRSTF() RMCSR
- func (p *RCC_Periph) LPWRRSTF() RMCSR
- func (p *RCC_Periph) LSEBYP() RMBDCR
- func (p *RCC_Periph) LSEDRV() RMBDCR
- func (p *RCC_Periph) LSEON() RMBDCR
- func (p *RCC_Periph) LSERDY() RMBDCR
- func (p *RCC_Periph) LSERDYC() RMCIR
- func (p *RCC_Periph) LSERDYF() RMCIR
- func (p *RCC_Periph) LSERDYIE() RMCIR
- func (p *RCC_Periph) LSION() RMCSR
- func (p *RCC_Periph) LSIRDY() RMCSR
- func (p *RCC_Periph) LSIRDYC() RMCIR
- func (p *RCC_Periph) LSIRDYF() RMCIR
- func (p *RCC_Periph) LSIRDYIE() RMCIR
- func (p *RCC_Periph) MCO() RMCFGR
- func (p *RCC_Periph) MCOPRE() RMCFGR
- func (p *RCC_Periph) OBLRSTF() RMCSR
- func (p *RCC_Periph) PINRSTF() RMCSR
- func (p *RCC_Periph) PLLMUL() RMCFGR
- func (p *RCC_Periph) PLLNODIV() RMCFGR
- func (p *RCC_Periph) PLLON() RMCR
- func (p *RCC_Periph) PLLRDY() RMCR
- func (p *RCC_Periph) PLLRDYC() RMCIR
- func (p *RCC_Periph) PLLRDYF() RMCIR
- func (p *RCC_Periph) PLLRDYIE() RMCIR
- func (p *RCC_Periph) PLLSRC() RMCFGR
- func (p *RCC_Periph) PLLXTPRE() RMCFGR
- func (p *RCC_Periph) PORRSTF() RMCSR
- func (p *RCC_Periph) PPRE() RMCFGR
- func (p *RCC_Periph) PREDIV() RMCFGR2
- func (p *RCC_Periph) PWREN() RMAPB1ENR
- func (p *RCC_Periph) PWRRST() RMAPB1RSTR
- func (p *RCC_Periph) RMVF() RMCSR
- func (p *RCC_Periph) RTCEN() RMBDCR
- func (p *RCC_Periph) RTCSEL() RMBDCR
- func (p *RCC_Periph) SFTRSTF() RMCSR
- func (p *RCC_Periph) SPI1EN() RMAPB2ENR
- func (p *RCC_Periph) SPI1RST() RMAPB2RSTR
- func (p *RCC_Periph) SRAMEN() RMAHBENR
- func (p *RCC_Periph) SW() RMCFGR
- func (p *RCC_Periph) SWS() RMCFGR
- func (p *RCC_Periph) SYSCFGCOMPEN() RMAPB2ENR
- func (p *RCC_Periph) SYSCFGRST() RMAPB2RSTR
- func (p *RCC_Periph) TIM14EN() RMAPB1ENR
- func (p *RCC_Periph) TIM14RST() RMAPB1RSTR
- func (p *RCC_Periph) TIM16EN() RMAPB2ENR
- func (p *RCC_Periph) TIM16RST() RMAPB2RSTR
- func (p *RCC_Periph) TIM17EN() RMAPB2ENR
- func (p *RCC_Periph) TIM17RST() RMAPB2RSTR
- func (p *RCC_Periph) TIM1EN() RMAPB2ENR
- func (p *RCC_Periph) TIM1RST() RMAPB2RSTR
- func (p *RCC_Periph) TIM3EN() RMAPB1ENR
- func (p *RCC_Periph) TIM3RST() RMAPB1RSTR
- func (p *RCC_Periph) USART1EN() RMAPB2ENR
- func (p *RCC_Periph) USART1RST() RMAPB2RSTR
- func (p *RCC_Periph) USART1SW() RMCFGR3
- func (p *RCC_Periph) V18PWRRSTF() RMCSR
- func (p *RCC_Periph) WWDGEN() RMAPB1ENR
- func (p *RCC_Periph) WWDGRST() RMAPB1RSTR
- func (p *RCC_Periph) WWDGRSTF() RMCSR
- type RCFGR
- func (r *RCFGR) AtomicClearBits(mask CFGR)
- func (r *RCFGR) AtomicSetBits(mask CFGR)
- func (r *RCFGR) AtomicStoreBits(mask, b CFGR)
- func (r *RCFGR) Bits(mask CFGR) CFGR
- func (r *RCFGR) ClearBits(mask CFGR)
- func (r *RCFGR) Load() CFGR
- func (r *RCFGR) SetBits(mask CFGR)
- func (r *RCFGR) Store(b CFGR)
- func (r *RCFGR) StoreBits(mask, b CFGR)
- type RCFGR2
- func (r *RCFGR2) AtomicClearBits(mask CFGR2)
- func (r *RCFGR2) AtomicSetBits(mask CFGR2)
- func (r *RCFGR2) AtomicStoreBits(mask, b CFGR2)
- func (r *RCFGR2) Bits(mask CFGR2) CFGR2
- func (r *RCFGR2) ClearBits(mask CFGR2)
- func (r *RCFGR2) Load() CFGR2
- func (r *RCFGR2) SetBits(mask CFGR2)
- func (r *RCFGR2) Store(b CFGR2)
- func (r *RCFGR2) StoreBits(mask, b CFGR2)
- type RCFGR3
- func (r *RCFGR3) AtomicClearBits(mask CFGR3)
- func (r *RCFGR3) AtomicSetBits(mask CFGR3)
- func (r *RCFGR3) AtomicStoreBits(mask, b CFGR3)
- func (r *RCFGR3) Bits(mask CFGR3) CFGR3
- func (r *RCFGR3) ClearBits(mask CFGR3)
- func (r *RCFGR3) Load() CFGR3
- func (r *RCFGR3) SetBits(mask CFGR3)
- func (r *RCFGR3) Store(b CFGR3)
- func (r *RCFGR3) StoreBits(mask, b CFGR3)
- type RCIR
- func (r *RCIR) AtomicClearBits(mask CIR)
- func (r *RCIR) AtomicSetBits(mask CIR)
- func (r *RCIR) AtomicStoreBits(mask, b CIR)
- func (r *RCIR) Bits(mask CIR) CIR
- func (r *RCIR) ClearBits(mask CIR)
- func (r *RCIR) Load() CIR
- func (r *RCIR) SetBits(mask CIR)
- func (r *RCIR) Store(b CIR)
- func (r *RCIR) StoreBits(mask, b CIR)
- type RCR
- type RCR2
- func (r *RCR2) AtomicClearBits(mask CR2)
- func (r *RCR2) AtomicSetBits(mask CR2)
- func (r *RCR2) AtomicStoreBits(mask, b CR2)
- func (r *RCR2) Bits(mask CR2) CR2
- func (r *RCR2) ClearBits(mask CR2)
- func (r *RCR2) Load() CR2
- func (r *RCR2) SetBits(mask CR2)
- func (r *RCR2) Store(b CR2)
- func (r *RCR2) StoreBits(mask, b CR2)
- type RCSR
- func (r *RCSR) AtomicClearBits(mask CSR)
- func (r *RCSR) AtomicSetBits(mask CSR)
- func (r *RCSR) AtomicStoreBits(mask, b CSR)
- func (r *RCSR) Bits(mask CSR) CSR
- func (r *RCSR) ClearBits(mask CSR)
- func (r *RCSR) Load() CSR
- func (r *RCSR) SetBits(mask CSR)
- func (r *RCSR) Store(b CSR)
- func (r *RCSR) StoreBits(mask, b CSR)
- type RMAHBENR
- type RMAHBRSTR
- type RMAPB1ENR
- type RMAPB1RSTR
- type RMAPB2ENR
- type RMAPB2RSTR
- type RMBDCR
- type RMCFGR
- type RMCFGR2
- type RMCFGR3
- type RMCIR
- type RMCR
- type RMCR2
- type RMCSR
Constants ¶
View Source
const ( HSIONn = 0 HSIRDYn = 1 HSITRIMn = 3 HSICALn = 8 HSEONn = 16 HSERDYn = 17 HSEBYPn = 18 CSSONn = 19 PLLONn = 24 PLLRDYn = 25 )
View Source
const ( SWn = 0 SWSn = 2 HPREn = 4 PPREn = 8 ADCPREn = 14 PLLSRCn = 16 PLLXTPREn = 17 PLLMULn = 18 MCOn = 24 MCOPREn = 28 PLLNODIVn = 31 )
View Source
const ( LSIRDYFn = 0 LSERDYFn = 1 HSIRDYFn = 2 HSERDYFn = 3 PLLRDYFn = 4 HSI14RDYFn = 5 CSSFn = 7 LSIRDYIEn = 8 LSERDYIEn = 9 HSIRDYIEn = 10 HSERDYIEn = 11 PLLRDYIEn = 12 HSI14RDYIEn = 13 LSIRDYCn = 16 LSERDYCn = 17 HSIRDYCn = 18 HSERDYCn = 19 PLLRDYCn = 20 HSI14RDYCn = 21 CSSCn = 23 )
View Source
const ( SYSCFGRSTn = 0 ADCRSTn = 9 TIM1RSTn = 11 SPI1RSTn = 12 USART1RSTn = 14 TIM16RSTn = 17 TIM17RSTn = 18 DBGMCURSTn = 22 )
View Source
const ( TIM3RSTn = 1 TIM14RSTn = 8 WWDGRSTn = 11 I2C1RSTn = 21 PWRRSTn = 28 )
View Source
const ( DMAENn = 0 SRAMENn = 2 FLITFENn = 4 CRCENn = 6 GPIOAENn = 17 GPIOBENn = 18 GPIOCENn = 19 GPIODENn = 20 GPIOFENn = 22 )
View Source
const ( SYSCFGCOMPENn = 0 ADCENn = 9 TIM1ENn = 11 SPI1ENn = 12 USART1ENn = 14 TIM16ENn = 17 TIM17ENn = 18 DBGMCUENn = 22 )
View Source
const ( TIM3ENn = 1 TIM14ENn = 8 WWDGENn = 11 I2C1ENn = 21 PWRENn = 28 )
View Source
const ( LSEONn = 0 LSERDYn = 1 LSEBYPn = 2 LSEDRVn = 3 RTCSELn = 8 RTCENn = 15 BDRSTn = 16 )
View Source
const ( LSIONn = 0 LSIRDYn = 1 V18PWRRSTFn = 23 RMVFn = 24 OBLRSTFn = 25 PINRSTFn = 26 PORRSTFn = 27 SFTRSTFn = 28 IWDGRSTFn = 29 WWDGRSTFn = 30 LPWRRSTFn = 31 )
View Source
const ( GPIOARSTn = 17 GPIOBRSTn = 18 GPIOCRSTn = 19 GPIODRSTn = 20 GPIOFRSTn = 22 )
View Source
const ( USART1SWn = 0 I2C1SWn = 4 )
View Source
const ( HSI14ONn = 0 HSI14RDYn = 1 HSI14DISn = 2 HSI14TRIMn = 3 HSI14CALn = 8 )
View Source
const (
PREDIVn = 0
)
Variables ¶
View Source
var RCC = (*RCC_Periph)(unsafe.Pointer(uintptr(mmap.RCC_BASE)))
Functions ¶
This section is empty.
Types ¶
type AHBENR ¶
type AHBENR uint32
const ( DMAEN AHBENR = 0x01 << 0 //+ DMA1 clock enable. SRAMEN AHBENR = 0x01 << 2 //+ SRAM interface clock enable. FLITFEN AHBENR = 0x01 << 4 //+ FLITF clock enable. CRCEN AHBENR = 0x01 << 6 //+ CRC clock enable. GPIOAEN AHBENR = 0x01 << 17 //+ GPIOA clock enable. GPIOBEN AHBENR = 0x01 << 18 //+ GPIOB clock enable. GPIOCEN AHBENR = 0x01 << 19 //+ GPIOC clock enable. GPIODEN AHBENR = 0x01 << 20 //+ GPIOD clock enable. GPIOFEN AHBENR = 0x01 << 22 //+ GPIOF clock enable. )
type APB2ENR ¶
type APB2ENR uint32
const ( SYSCFGCOMPEN APB2ENR = 0x01 << 0 //+ SYSCFG and comparator clock enable. ADCEN APB2ENR = 0x01 << 9 //+ ADC1 clock enable. TIM1EN APB2ENR = 0x01 << 11 //+ TIM1 clock enable. SPI1EN APB2ENR = 0x01 << 12 //+ SPI1 clock enable. USART1EN APB2ENR = 0x01 << 14 //+ USART1 clock enable. TIM16EN APB2ENR = 0x01 << 17 //+ TIM16 clock enable. TIM17EN APB2ENR = 0x01 << 18 //+ TIM17 clock enable. DBGMCUEN APB2ENR = 0x01 << 22 //+ DBGMCU clock enable. )
type APB2RSTR ¶
type APB2RSTR uint32
const ( SYSCFGRST APB2RSTR = 0x01 << 0 //+ SYSCFG reset. ADCRST APB2RSTR = 0x01 << 9 //+ ADC reset. TIM1RST APB2RSTR = 0x01 << 11 //+ TIM1 reset. SPI1RST APB2RSTR = 0x01 << 12 //+ SPI1 reset. USART1RST APB2RSTR = 0x01 << 14 //+ USART1 reset. TIM16RST APB2RSTR = 0x01 << 17 //+ TIM16 reset. TIM17RST APB2RSTR = 0x01 << 18 //+ TIM17 reset. DBGMCURST APB2RSTR = 0x01 << 22 //+ DBGMCU reset. )
type BDCR ¶
type BDCR uint32
const ( LSEON BDCR = 0x01 << 0 //+ External Low Speed oscillator enable. LSERDY BDCR = 0x01 << 1 //+ External Low Speed oscillator Ready. LSEBYP BDCR = 0x01 << 2 //+ External Low Speed oscillator Bypass. LSEDRV BDCR = 0x03 << 3 //+ LSEDRV[1:0] bits (LSE Osc. drive capability). RTCSEL BDCR = 0x03 << 8 //+ RTCSEL[1:0] bits (RTC clock source selection). RTCSEL_NOCLOCK BDCR = 0x00 << 8 // No clock. RTCSEL_LSE BDCR = 0x01 << 8 // LSE oscillator clock used as RTC clock. RTCSEL_LSI BDCR = 0x02 << 8 // LSI oscillator clock used as RTC clock. RTCSEL_HSE BDCR = 0x03 << 8 // HSE oscillator clock divided by 128 used as RTC clock. RTCEN BDCR = 0x01 << 15 //+ RTC clock enable. BDRST BDCR = 0x01 << 16 //+ Backup domain software reset. )
type CFGR ¶
type CFGR uint32
const ( SW CFGR = 0x03 << 0 //+ SW[1:0] bits (System clock Switch). SW_HSI CFGR = 0x00 << 0 // HSI selected as system clock. SW_HSE CFGR = 0x01 << 0 // HSE selected as system clock. SW_PLL CFGR = 0x02 << 0 // PLL selected as system clock. SWS CFGR = 0x03 << 2 //+ SWS[1:0] bits (System Clock Switch Status). SWS_HSI CFGR = 0x00 << 2 // HSI oscillator used as system clock. SWS_HSE CFGR = 0x01 << 2 // HSE oscillator used as system clock. SWS_PLL CFGR = 0x02 << 2 // PLL used as system clock. HPRE CFGR = 0x0F << 4 //+ HPRE[3:0] bits (AHB prescaler). HPRE_DIV1 CFGR = 0x00 << 4 // SYSCLK not divided. HPRE_DIV2 CFGR = 0x08 << 4 // SYSCLK divided by 2. HPRE_DIV4 CFGR = 0x09 << 4 // SYSCLK divided by 4. HPRE_DIV8 CFGR = 0x0A << 4 // SYSCLK divided by 8. HPRE_DIV16 CFGR = 0x0B << 4 // SYSCLK divided by 16. HPRE_DIV64 CFGR = 0x0C << 4 // SYSCLK divided by 64. HPRE_DIV128 CFGR = 0x0D << 4 // SYSCLK divided by 128. HPRE_DIV256 CFGR = 0x0E << 4 // SYSCLK divided by 256. HPRE_DIV512 CFGR = 0x0F << 4 // SYSCLK divided by 512. PPRE CFGR = 0x07 << 8 //+ PRE[2:0] bits (APB prescaler). PPRE_DIV1 CFGR = 0x00 << 8 // HCLK not divided. PPRE_DIV2 CFGR = 0x04 << 8 // HCLK divided by 2. PPRE_DIV4 CFGR = 0x05 << 8 // HCLK divided by 4. PPRE_DIV8 CFGR = 0x06 << 8 // HCLK divided by 8. PPRE_DIV16 CFGR = 0x07 << 8 // HCLK divided by 16. ADCPRE CFGR = 0x01 << 14 //+ ADCPRE bit (ADC prescaler). ADCPRE_DIV2 CFGR = 0x00 << 14 // PCLK divided by 2. ADCPRE_DIV4 CFGR = 0x01 << 14 // PCLK divided by 4. PLLSRC CFGR = 0x01 << 16 //+ PLL entry clock source. PLLSRC_HSI_DIV2 CFGR = 0x00 << 16 // HSI clock divided by 2 selected as PLL entry clock source. PLLSRC_HSE_PREDIV CFGR = 0x01 << 16 // HSE/PREDIV clock selected as PLL entry clock source. PLLXTPRE CFGR = 0x01 << 17 //+ HSE divider for PLL entry. PLLXTPRE_HSE_PREDIV_DIV1 CFGR = 0x00 << 17 // HSE/PREDIV clock not divided for PLL entry. PLLXTPRE_HSE_PREDIV_DIV2 CFGR = 0x01 << 17 // HSE/PREDIV clock divided by 2 for PLL entry. PLLMUL CFGR = 0x0F << 18 //+ PLLMUL[3:0] bits (PLL multiplication factor). PLLMUL2 CFGR = 0x00 << 18 // PLL input clock*2. PLLMUL3 CFGR = 0x01 << 18 // PLL input clock*3. PLLMUL4 CFGR = 0x02 << 18 // PLL input clock*4. PLLMUL5 CFGR = 0x03 << 18 // PLL input clock*5. PLLMUL6 CFGR = 0x04 << 18 // PLL input clock*6. PLLMUL7 CFGR = 0x05 << 18 // PLL input clock*7. PLLMUL8 CFGR = 0x06 << 18 // PLL input clock*8. PLLMUL9 CFGR = 0x07 << 18 // PLL input clock*9. PLLMUL10 CFGR = 0x08 << 18 // PLL input clock10. PLLMUL11 CFGR = 0x09 << 18 // PLL input clock*11. PLLMUL12 CFGR = 0x0A << 18 // PLL input clock*12. PLLMUL13 CFGR = 0x0B << 18 // PLL input clock*13. PLLMUL14 CFGR = 0x0C << 18 // PLL input clock*14. PLLMUL15 CFGR = 0x0D << 18 // PLL input clock*15. PLLMUL16 CFGR = 0x0E << 18 // PLL input clock*16. MCO CFGR = 0x0F << 24 //+ MCO[3:0] bits (Microcontroller Clock Output). MCO_NOCLOCK CFGR = 0x00 << 24 // No clock. MCO_HSI14 CFGR = 0x01 << 24 // HSI14 clock selected as MCO source. MCO_LSI CFGR = 0x02 << 24 // LSI clock selected as MCO source. MCO_LSE CFGR = 0x03 << 24 // LSE clock selected as MCO source. MCO_SYSCLK CFGR = 0x04 << 24 // System clock selected as MCO source. MCO_HSI CFGR = 0x05 << 24 // HSI clock selected as MCO source. MCO_HSE CFGR = 0x06 << 24 // HSE clock selected as MCO source. MCO_PLL CFGR = 0x07 << 24 // PLL clock divided by 2 selected as MCO source. MCOPRE CFGR = 0x07 << 28 //+ MCO prescaler. MCOPRE_DIV1 CFGR = 0x00 << 28 // MCO is divided by 1. MCOPRE_DIV2 CFGR = 0x01 << 28 // MCO is divided by 2. MCOPRE_DIV4 CFGR = 0x02 << 28 // MCO is divided by 4. MCOPRE_DIV8 CFGR = 0x03 << 28 // MCO is divided by 8. MCOPRE_DIV16 CFGR = 0x04 << 28 // MCO is divided by 16. MCOPRE_DIV32 CFGR = 0x05 << 28 // MCO is divided by 32. MCOPRE_DIV64 CFGR = 0x06 << 28 // MCO is divided by 64. MCOPRE_DIV128 CFGR = 0x07 << 28 // MCO is divided by 128. PLLNODIV CFGR = 0x01 << 31 //+ PLL is not divided to MCO. )
type CFGR2 ¶
type CFGR2 uint32
const ( PREDIV CFGR2 = 0x0F << 0 //+ PREDIV[3:0] bits. PREDIV_DIV1 CFGR2 = 0x00 << 0 // PREDIV input clock not divided. PREDIV_DIV2 CFGR2 = 0x01 << 0 // PREDIV input clock divided by 2. PREDIV_DIV3 CFGR2 = 0x02 << 0 // PREDIV input clock divided by 3. PREDIV_DIV4 CFGR2 = 0x03 << 0 // PREDIV input clock divided by 4. PREDIV_DIV5 CFGR2 = 0x04 << 0 // PREDIV input clock divided by 5. PREDIV_DIV6 CFGR2 = 0x05 << 0 // PREDIV input clock divided by 6. PREDIV_DIV7 CFGR2 = 0x06 << 0 // PREDIV input clock divided by 7. PREDIV_DIV8 CFGR2 = 0x07 << 0 // PREDIV input clock divided by 8. PREDIV_DIV9 CFGR2 = 0x08 << 0 // PREDIV input clock divided by 9. PREDIV_DIV10 CFGR2 = 0x09 << 0 // PREDIV input clock divided by 10. PREDIV_DIV11 CFGR2 = 0x0A << 0 // PREDIV input clock divided by 11. PREDIV_DIV12 CFGR2 = 0x0B << 0 // PREDIV input clock divided by 12. PREDIV_DIV13 CFGR2 = 0x0C << 0 // PREDIV input clock divided by 13. PREDIV_DIV14 CFGR2 = 0x0D << 0 // PREDIV input clock divided by 14. PREDIV_DIV15 CFGR2 = 0x0E << 0 // PREDIV input clock divided by 15. PREDIV_DIV16 CFGR2 = 0x0F << 0 // PREDIV input clock divided by 16. )
type CFGR3 ¶
type CFGR3 uint32
const ( USART1SW CFGR3 = 0x03 << 0 //+ USART1SW[1:0] bits. USART1SW_PCLK CFGR3 = 0x00 << 0 // PCLK clock used as USART1 clock source. USART1SW_SYSCLK CFGR3 = 0x01 << 0 // System clock selected as USART1 clock source. USART1SW_LSE CFGR3 = 0x02 << 0 // LSE oscillator clock used as USART1 clock source. USART1SW_HSI CFGR3 = 0x03 << 0 // HSI oscillator clock used as USART1 clock source. I2C1SW CFGR3 = 0x01 << 4 //+ I2C1SW bits. I2C1SW_HSI CFGR3 = 0x00 << 4 // HSI oscillator clock used as I2C1 clock source. I2C1SW_SYSCLK CFGR3 = 0x01 << 4 // System clock selected as I2C1 clock source. )
type CIR ¶
type CIR uint32
const ( LSIRDYF CIR = 0x01 << 0 //+ LSI Ready Interrupt flag. LSERDYF CIR = 0x01 << 1 //+ LSE Ready Interrupt flag. HSIRDYF CIR = 0x01 << 2 //+ HSI Ready Interrupt flag. HSERDYF CIR = 0x01 << 3 //+ HSE Ready Interrupt flag. PLLRDYF CIR = 0x01 << 4 //+ PLL Ready Interrupt flag. HSI14RDYF CIR = 0x01 << 5 //+ HSI14 Ready Interrupt flag. CSSF CIR = 0x01 << 7 //+ Clock Security System Interrupt flag. LSIRDYIE CIR = 0x01 << 8 //+ LSI Ready Interrupt Enable. LSERDYIE CIR = 0x01 << 9 //+ LSE Ready Interrupt Enable. HSIRDYIE CIR = 0x01 << 10 //+ HSI Ready Interrupt Enable. HSERDYIE CIR = 0x01 << 11 //+ HSE Ready Interrupt Enable. PLLRDYIE CIR = 0x01 << 12 //+ PLL Ready Interrupt Enable. HSI14RDYIE CIR = 0x01 << 13 //+ HSI14 Ready Interrupt Enable. LSIRDYC CIR = 0x01 << 16 //+ LSI Ready Interrupt Clear. LSERDYC CIR = 0x01 << 17 //+ LSE Ready Interrupt Clear. HSIRDYC CIR = 0x01 << 18 //+ HSI Ready Interrupt Clear. HSERDYC CIR = 0x01 << 19 //+ HSE Ready Interrupt Clear. PLLRDYC CIR = 0x01 << 20 //+ PLL Ready Interrupt Clear. HSI14RDYC CIR = 0x01 << 21 //+ HSI14 Ready Interrupt Clear. CSSC CIR = 0x01 << 23 //+ Clock Security System Interrupt Clear. )
type CR ¶
type CR uint32
const ( HSION CR = 0x01 << 0 //+ Internal High Speed clock enable. HSIRDY CR = 0x01 << 1 //+ Internal High Speed clock ready flag. HSITRIM CR = 0x1F << 3 //+ Internal High Speed clock trimming. HSICAL CR = 0xFF << 8 //+ Internal High Speed clock Calibration. HSEON CR = 0x01 << 16 //+ External High Speed clock enable. HSERDY CR = 0x01 << 17 //+ External High Speed clock ready flag. HSEBYP CR = 0x01 << 18 //+ External High Speed clock Bypass. CSSON CR = 0x01 << 19 //+ Clock Security System enable. PLLON CR = 0x01 << 24 //+ PLL enable. PLLRDY CR = 0x01 << 25 //+ PLL clock ready flag. )
type CR2 ¶
type CR2 uint32
const ( HSI14ON CR2 = 0x01 << 0 //+ Internal High Speed 14MHz clock enable. HSI14RDY CR2 = 0x01 << 1 //+ Internal High Speed 14MHz clock ready flag. HSI14DIS CR2 = 0x01 << 2 //+ Internal High Speed 14MHz clock disable. HSI14TRIM CR2 = 0x1F << 3 //+ Internal High Speed 14MHz clock trimming. HSI14CAL CR2 = 0xFF << 8 //+ Internal High Speed 14MHz clock Calibration. )
type CSR ¶
type CSR uint32
const ( LSION CSR = 0x01 << 0 //+ Internal Low Speed oscillator enable. LSIRDY CSR = 0x01 << 1 //+ Internal Low Speed oscillator Ready. V18PWRRSTF CSR = 0x01 << 23 //+ V1.8 power domain reset flag. RMVF CSR = 0x01 << 24 //+ Remove reset flag. OBLRSTF CSR = 0x01 << 25 //+ OBL reset flag. PINRSTF CSR = 0x01 << 26 //+ PIN reset flag. PORRSTF CSR = 0x01 << 27 //+ POR/PDR reset flag. SFTRSTF CSR = 0x01 << 28 //+ Software Reset flag. IWDGRSTF CSR = 0x01 << 29 //+ Independent Watchdog reset flag. WWDGRSTF CSR = 0x01 << 30 //+ Window watchdog reset flag. LPWRRSTF CSR = 0x01 << 31 //+ Low-Power reset flag. )
type RAHBENR ¶
func (*RAHBENR) AtomicClearBits ¶
func (*RAHBENR) AtomicSetBits ¶
func (*RAHBENR) AtomicStoreBits ¶
type RAHBRSTR ¶
func (*RAHBRSTR) AtomicClearBits ¶
func (*RAHBRSTR) AtomicSetBits ¶
func (*RAHBRSTR) AtomicStoreBits ¶
type RAPB1ENR ¶
func (*RAPB1ENR) AtomicClearBits ¶
func (*RAPB1ENR) AtomicSetBits ¶
func (*RAPB1ENR) AtomicStoreBits ¶
type RAPB1RSTR ¶
func (*RAPB1RSTR) AtomicClearBits ¶
func (*RAPB1RSTR) AtomicSetBits ¶
func (*RAPB1RSTR) AtomicStoreBits ¶
type RAPB2ENR ¶
func (*RAPB2ENR) AtomicClearBits ¶
func (*RAPB2ENR) AtomicSetBits ¶
func (*RAPB2ENR) AtomicStoreBits ¶
type RAPB2RSTR ¶
func (*RAPB2RSTR) AtomicClearBits ¶
func (*RAPB2RSTR) AtomicSetBits ¶
func (*RAPB2RSTR) AtomicStoreBits ¶
type RBDCR ¶
func (*RBDCR) AtomicClearBits ¶
func (*RBDCR) AtomicSetBits ¶
func (*RBDCR) AtomicStoreBits ¶
type RCC_Periph ¶
type RCC_Periph struct { CR RCR CFGR RCFGR CIR RCIR APB2RSTR RAPB2RSTR APB1RSTR RAPB1RSTR AHBENR RAHBENR APB2ENR RAPB2ENR APB1ENR RAPB1ENR BDCR RBDCR CSR RCSR AHBRSTR RAHBRSTR CFGR2 RCFGR2 CFGR3 RCFGR3 CR2 RCR2 }
func (*RCC_Periph) ADCEN ¶
func (p *RCC_Periph) ADCEN() RMAPB2ENR
func (*RCC_Periph) ADCPRE ¶
func (p *RCC_Periph) ADCPRE() RMCFGR
func (*RCC_Periph) ADCRST ¶
func (p *RCC_Periph) ADCRST() RMAPB2RSTR
func (*RCC_Periph) BDRST ¶
func (p *RCC_Periph) BDRST() RMBDCR
func (*RCC_Periph) BaseAddr ¶
func (p *RCC_Periph) BaseAddr() uintptr
func (*RCC_Periph) CRCEN ¶
func (p *RCC_Periph) CRCEN() RMAHBENR
func (*RCC_Periph) CSSC ¶
func (p *RCC_Periph) CSSC() RMCIR
func (*RCC_Periph) CSSF ¶
func (p *RCC_Periph) CSSF() RMCIR
func (*RCC_Periph) CSSON ¶
func (p *RCC_Periph) CSSON() RMCR
func (*RCC_Periph) DBGMCUEN ¶
func (p *RCC_Periph) DBGMCUEN() RMAPB2ENR
func (*RCC_Periph) DBGMCURST ¶
func (p *RCC_Periph) DBGMCURST() RMAPB2RSTR
func (*RCC_Periph) DMAEN ¶
func (p *RCC_Periph) DMAEN() RMAHBENR
func (*RCC_Periph) FLITFEN ¶
func (p *RCC_Periph) FLITFEN() RMAHBENR
func (*RCC_Periph) GPIOAEN ¶
func (p *RCC_Periph) GPIOAEN() RMAHBENR
func (*RCC_Periph) GPIOARST ¶
func (p *RCC_Periph) GPIOARST() RMAHBRSTR
func (*RCC_Periph) GPIOBEN ¶
func (p *RCC_Periph) GPIOBEN() RMAHBENR
func (*RCC_Periph) GPIOBRST ¶
func (p *RCC_Periph) GPIOBRST() RMAHBRSTR
func (*RCC_Periph) GPIOCEN ¶
func (p *RCC_Periph) GPIOCEN() RMAHBENR
func (*RCC_Periph) GPIOCRST ¶
func (p *RCC_Periph) GPIOCRST() RMAHBRSTR
func (*RCC_Periph) GPIODEN ¶
func (p *RCC_Periph) GPIODEN() RMAHBENR
func (*RCC_Periph) GPIODRST ¶
func (p *RCC_Periph) GPIODRST() RMAHBRSTR
func (*RCC_Periph) GPIOFEN ¶
func (p *RCC_Periph) GPIOFEN() RMAHBENR
func (*RCC_Periph) GPIOFRST ¶
func (p *RCC_Periph) GPIOFRST() RMAHBRSTR
func (*RCC_Periph) HPRE ¶
func (p *RCC_Periph) HPRE() RMCFGR
func (*RCC_Periph) HSEBYP ¶
func (p *RCC_Periph) HSEBYP() RMCR
func (*RCC_Periph) HSEON ¶
func (p *RCC_Periph) HSEON() RMCR
func (*RCC_Periph) HSERDY ¶
func (p *RCC_Periph) HSERDY() RMCR
func (*RCC_Periph) HSERDYC ¶
func (p *RCC_Periph) HSERDYC() RMCIR
func (*RCC_Periph) HSERDYF ¶
func (p *RCC_Periph) HSERDYF() RMCIR
func (*RCC_Periph) HSERDYIE ¶
func (p *RCC_Periph) HSERDYIE() RMCIR
func (*RCC_Periph) HSI14CAL ¶
func (p *RCC_Periph) HSI14CAL() RMCR2
func (*RCC_Periph) HSI14DIS ¶
func (p *RCC_Periph) HSI14DIS() RMCR2
func (*RCC_Periph) HSI14ON ¶
func (p *RCC_Periph) HSI14ON() RMCR2
func (*RCC_Periph) HSI14RDY ¶
func (p *RCC_Periph) HSI14RDY() RMCR2
func (*RCC_Periph) HSI14RDYC ¶
func (p *RCC_Periph) HSI14RDYC() RMCIR
func (*RCC_Periph) HSI14RDYF ¶
func (p *RCC_Periph) HSI14RDYF() RMCIR
func (*RCC_Periph) HSI14RDYIE ¶
func (p *RCC_Periph) HSI14RDYIE() RMCIR
func (*RCC_Periph) HSI14TRIM ¶
func (p *RCC_Periph) HSI14TRIM() RMCR2
func (*RCC_Periph) HSICAL ¶
func (p *RCC_Periph) HSICAL() RMCR
func (*RCC_Periph) HSION ¶
func (p *RCC_Periph) HSION() RMCR
func (*RCC_Periph) HSIRDY ¶
func (p *RCC_Periph) HSIRDY() RMCR
func (*RCC_Periph) HSIRDYC ¶
func (p *RCC_Periph) HSIRDYC() RMCIR
func (*RCC_Periph) HSIRDYF ¶
func (p *RCC_Periph) HSIRDYF() RMCIR
func (*RCC_Periph) HSIRDYIE ¶
func (p *RCC_Periph) HSIRDYIE() RMCIR
func (*RCC_Periph) HSITRIM ¶
func (p *RCC_Periph) HSITRIM() RMCR
func (*RCC_Periph) I2C1EN ¶
func (p *RCC_Periph) I2C1EN() RMAPB1ENR
func (*RCC_Periph) I2C1RST ¶
func (p *RCC_Periph) I2C1RST() RMAPB1RSTR
func (*RCC_Periph) I2C1SW ¶
func (p *RCC_Periph) I2C1SW() RMCFGR3
func (*RCC_Periph) IWDGRSTF ¶
func (p *RCC_Periph) IWDGRSTF() RMCSR
func (*RCC_Periph) LPWRRSTF ¶
func (p *RCC_Periph) LPWRRSTF() RMCSR
func (*RCC_Periph) LSEBYP ¶
func (p *RCC_Periph) LSEBYP() RMBDCR
func (*RCC_Periph) LSEDRV ¶
func (p *RCC_Periph) LSEDRV() RMBDCR
func (*RCC_Periph) LSEON ¶
func (p *RCC_Periph) LSEON() RMBDCR
func (*RCC_Periph) LSERDY ¶
func (p *RCC_Periph) LSERDY() RMBDCR
func (*RCC_Periph) LSERDYC ¶
func (p *RCC_Periph) LSERDYC() RMCIR
func (*RCC_Periph) LSERDYF ¶
func (p *RCC_Periph) LSERDYF() RMCIR
func (*RCC_Periph) LSERDYIE ¶
func (p *RCC_Periph) LSERDYIE() RMCIR
func (*RCC_Periph) LSION ¶
func (p *RCC_Periph) LSION() RMCSR
func (*RCC_Periph) LSIRDY ¶
func (p *RCC_Periph) LSIRDY() RMCSR
func (*RCC_Periph) LSIRDYC ¶
func (p *RCC_Periph) LSIRDYC() RMCIR
func (*RCC_Periph) LSIRDYF ¶
func (p *RCC_Periph) LSIRDYF() RMCIR
func (*RCC_Periph) LSIRDYIE ¶
func (p *RCC_Periph) LSIRDYIE() RMCIR
func (*RCC_Periph) MCO ¶
func (p *RCC_Periph) MCO() RMCFGR
func (*RCC_Periph) MCOPRE ¶
func (p *RCC_Periph) MCOPRE() RMCFGR
func (*RCC_Periph) OBLRSTF ¶
func (p *RCC_Periph) OBLRSTF() RMCSR
func (*RCC_Periph) PINRSTF ¶
func (p *RCC_Periph) PINRSTF() RMCSR
func (*RCC_Periph) PLLMUL ¶
func (p *RCC_Periph) PLLMUL() RMCFGR
func (*RCC_Periph) PLLNODIV ¶
func (p *RCC_Periph) PLLNODIV() RMCFGR
func (*RCC_Periph) PLLON ¶
func (p *RCC_Periph) PLLON() RMCR
func (*RCC_Periph) PLLRDY ¶
func (p *RCC_Periph) PLLRDY() RMCR
func (*RCC_Periph) PLLRDYC ¶
func (p *RCC_Periph) PLLRDYC() RMCIR
func (*RCC_Periph) PLLRDYF ¶
func (p *RCC_Periph) PLLRDYF() RMCIR
func (*RCC_Periph) PLLRDYIE ¶
func (p *RCC_Periph) PLLRDYIE() RMCIR
func (*RCC_Periph) PLLSRC ¶
func (p *RCC_Periph) PLLSRC() RMCFGR
func (*RCC_Periph) PLLXTPRE ¶
func (p *RCC_Periph) PLLXTPRE() RMCFGR
func (*RCC_Periph) PORRSTF ¶
func (p *RCC_Periph) PORRSTF() RMCSR
func (*RCC_Periph) PPRE ¶
func (p *RCC_Periph) PPRE() RMCFGR
func (*RCC_Periph) PREDIV ¶
func (p *RCC_Periph) PREDIV() RMCFGR2
func (*RCC_Periph) PWREN ¶
func (p *RCC_Periph) PWREN() RMAPB1ENR
func (*RCC_Periph) PWRRST ¶
func (p *RCC_Periph) PWRRST() RMAPB1RSTR
func (*RCC_Periph) RMVF ¶
func (p *RCC_Periph) RMVF() RMCSR
func (*RCC_Periph) RTCEN ¶
func (p *RCC_Periph) RTCEN() RMBDCR
func (*RCC_Periph) RTCSEL ¶
func (p *RCC_Periph) RTCSEL() RMBDCR
func (*RCC_Periph) SFTRSTF ¶
func (p *RCC_Periph) SFTRSTF() RMCSR
func (*RCC_Periph) SPI1EN ¶
func (p *RCC_Periph) SPI1EN() RMAPB2ENR
func (*RCC_Periph) SPI1RST ¶
func (p *RCC_Periph) SPI1RST() RMAPB2RSTR
func (*RCC_Periph) SRAMEN ¶
func (p *RCC_Periph) SRAMEN() RMAHBENR
func (*RCC_Periph) SW ¶
func (p *RCC_Periph) SW() RMCFGR
func (*RCC_Periph) SWS ¶
func (p *RCC_Periph) SWS() RMCFGR
func (*RCC_Periph) SYSCFGCOMPEN ¶
func (p *RCC_Periph) SYSCFGCOMPEN() RMAPB2ENR
func (*RCC_Periph) SYSCFGRST ¶
func (p *RCC_Periph) SYSCFGRST() RMAPB2RSTR
func (*RCC_Periph) TIM14EN ¶
func (p *RCC_Periph) TIM14EN() RMAPB1ENR
func (*RCC_Periph) TIM14RST ¶
func (p *RCC_Periph) TIM14RST() RMAPB1RSTR
func (*RCC_Periph) TIM16EN ¶
func (p *RCC_Periph) TIM16EN() RMAPB2ENR
func (*RCC_Periph) TIM16RST ¶
func (p *RCC_Periph) TIM16RST() RMAPB2RSTR
func (*RCC_Periph) TIM17EN ¶
func (p *RCC_Periph) TIM17EN() RMAPB2ENR
func (*RCC_Periph) TIM17RST ¶
func (p *RCC_Periph) TIM17RST() RMAPB2RSTR
func (*RCC_Periph) TIM1EN ¶
func (p *RCC_Periph) TIM1EN() RMAPB2ENR
func (*RCC_Periph) TIM1RST ¶
func (p *RCC_Periph) TIM1RST() RMAPB2RSTR
func (*RCC_Periph) TIM3EN ¶
func (p *RCC_Periph) TIM3EN() RMAPB1ENR
func (*RCC_Periph) TIM3RST ¶
func (p *RCC_Periph) TIM3RST() RMAPB1RSTR
func (*RCC_Periph) USART1EN ¶
func (p *RCC_Periph) USART1EN() RMAPB2ENR
func (*RCC_Periph) USART1RST ¶
func (p *RCC_Periph) USART1RST() RMAPB2RSTR
func (*RCC_Periph) USART1SW ¶
func (p *RCC_Periph) USART1SW() RMCFGR3
func (*RCC_Periph) V18PWRRSTF ¶
func (p *RCC_Periph) V18PWRRSTF() RMCSR
func (*RCC_Periph) WWDGEN ¶
func (p *RCC_Periph) WWDGEN() RMAPB1ENR
func (*RCC_Periph) WWDGRST ¶
func (p *RCC_Periph) WWDGRST() RMAPB1RSTR
func (*RCC_Periph) WWDGRSTF ¶
func (p *RCC_Periph) WWDGRSTF() RMCSR
type RCFGR ¶
func (*RCFGR) AtomicClearBits ¶
func (*RCFGR) AtomicSetBits ¶
func (*RCFGR) AtomicStoreBits ¶
type RCFGR2 ¶
func (*RCFGR2) AtomicClearBits ¶
func (*RCFGR2) AtomicSetBits ¶
func (*RCFGR2) AtomicStoreBits ¶
type RCFGR3 ¶
func (*RCFGR3) AtomicClearBits ¶
func (*RCFGR3) AtomicSetBits ¶
func (*RCFGR3) AtomicStoreBits ¶
type RCIR ¶
func (*RCIR) AtomicClearBits ¶
func (*RCIR) AtomicSetBits ¶
func (*RCIR) AtomicStoreBits ¶
type RCR2 ¶
func (*RCR2) AtomicClearBits ¶
func (*RCR2) AtomicSetBits ¶
func (*RCR2) AtomicStoreBits ¶
type RCSR ¶
func (*RCSR) AtomicClearBits ¶
func (*RCSR) AtomicSetBits ¶
func (*RCSR) AtomicStoreBits ¶
type RMAPB1RSTR ¶
func (RMAPB1RSTR) Load ¶
func (rm RMAPB1RSTR) Load() APB1RSTR
func (RMAPB1RSTR) Store ¶
func (rm RMAPB1RSTR) Store(b APB1RSTR)
type RMAPB2RSTR ¶
func (RMAPB2RSTR) Load ¶
func (rm RMAPB2RSTR) Load() APB2RSTR
func (RMAPB2RSTR) Store ¶
func (rm RMAPB2RSTR) Store(b APB2RSTR)
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