arm

package
v0.0.0-...-f78bcf1 Latest Latest
Warning

This package is not in the latest version of its module.

 Go to latest Published: Feb 18, 2025 License: BSD-3-Clause Imports: 5 Imported by: 3

Documentation

Overview

Package arm provides support for ARM architecture specific operations.

The following architectures/cores are supported/tested:

  • ARMv7-A / Cortex-A7 (single-core)

This package is only meant to be used with `GOOS=tamago GOARCH=arm` as supported by the TamaGo framework for bare metal Go, see https://github.com/usbarmory/tamago.

Index

Constants

View Source 
const (
	USR_MODE = 0b10000
	FIQ_MODE = 0b10001
	IRQ_MODE = 0b10010
	SVC_MODE = 0b10011
	MON_MODE = 0b10110
	ABT_MODE = 0b10111
	HYP_MODE = 0b11010
	UND_MODE = 0b11011
	SYS_MODE = 0b11111
)

ARM processor modes (Table B1-1, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

View Source 
const (
	RESET          = 0x00
	UNDEFINED      = 0x04
	SUPERVISOR     = 0x08
	PREFETCH_ABORT = 0x0c
	DATA_ABORT     = 0x10
	IRQ            = 0x18
	FIQ            = 0x1c
)

ARM exception vector offsets (Table 11-1, ARM® Cortex™ -A Series Programmer’s Guide).

View Source 
const (
	ID_PFR0_ARM_MASK     = 0x000f
	ID_PFR0_THUMB_MASK   = 0x00f0
	ID_PFR0_THUMBEE_MASK = 0x0f00
	ID_PFR0_JAZELLE_MASK = 0xf000

	ID_PFR1_PROGRAMMERS_MODEL_MASK = 0x0000f
	ID_PFR1_SECURITY_MASK          = 0x000f0
	ID_PFR1_M_PROFILE_MODEL_MASK   = 0x00f00
	ID_PFR1_VIRTUALIZATION_MASK    = 0x0f000
	ID_PFR1_GENERIC_TIMER_MASK     = 0xf0000
)

ARM processor feature registers

View Source 
const (
	TTE_PAGE_TABLE    uint32 = (1 << 0)
	TTE_SECTION       uint32 = (1 << 1)
	TTE_BUFFERABLE    uint32 = (1 << 2)
	TTE_CACHEABLE     uint32 = (1 << 3)
	TTE_EXECUTE_NEVER uint32 = (1 << 4)
	TTE_SUPERSECTION  uint32 = (1 << 18) | (1 << 1)
	TTE_NS            uint32 = (1 << 19)
)

Memory region attributes (Table B3-10, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

View Source 
const (
	// PL1: no access   PL0: no access
	TTE_AP_000 uint32 = 0b00
	// PL1: read/write  PL0: no access
	TTE_AP_001 uint32 = 0b01
	// PL1: read/write  PL0: read only
	TTE_AP_010 uint32 = 0b10
	// PL1: read/write  PL0: read/write
	TTE_AP_011 uint32 = 0b11
)

MMU access permissions (Table B3-8, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

View Source 
const (
	MemoryRegion = TTE_AP_001<<10 | TTE_CACHEABLE | TTE_BUFFERABLE | TTE_SECTION
	DeviceRegion = TTE_AP_001<<10 | TTE_SECTION
)
View Source 
const (
	// p2402, Table D5-1, ARMv7 Architecture Reference Manual
	CNTCR = 0
	// base frequency
	CNTFID0 = 0x20

	// p2410, D5.7.2 CNTCR, Counter Control Register, ARMv7 Architecture
	// Reference Manual
	//
	// frequency = CNTFID0/CNTFID2
	CNTCR_FCREQ2 = 10
	// frequency = CNTFID0/CNTFID1
	CNTCR_FCREQ1 = 9
	// frequency = CNTFID0
	CNTCR_FCREQ0 = 8
	CNTCR_HDBG   = 1
	CNTCR_EN     = 0

	CNTKCTL_PL0PCTEN = 0
)

ARM timer register constants

View Source 
const (
	ACTLR_SMP = 6
)

ARM cache register constants

View Source 
const (
	FPEXC_EN = 30
)

Variables

View Source 
var SystemExceptionHandler = DefaultExceptionHandler

SystemExceptionHandler allows to override the default exception handler executed at any exception by the table returned by SystemVectorTable(), which is used by default when initializing the CPU instance (e.g. CPU.Init()).

Functions

func Busyloop 

func Busyloop(count int32)

Busyloop spins the processor for busy waiting purposes, taking a counter value for the number of loops.

func DefaultExceptionHandler 

func DefaultExceptionHandler(off int)

DefaultExceptionHandler handles an exception by printing its vector and processor mode before panicking.

func ModeName 

func ModeName(mode int) string

ModeName returns the processor mode name.

func ServiceInterrupts 

func ServiceInterrupts(isr func())

ServiceInterrupts() puts the calling goroutine in wait state, its execution is resumed when an IRQ exception is received, an argument function can be set to service signaled interrupts (see gic package).

func VectorName 

func VectorName(off int) string

VectorName returns the exception vector offset name.

Types

type CPU 

type CPU struct {

	// Timer multiplier
	TimerMultiplier int64
	// Timer offset in nanoseconds
	TimerOffset int64
	// Timer function
	TimerFn func() int64
	// contains filtered or unexported fields
}

CPU instance

func (*CPU) ConfigureMMU 

func (cpu *CPU) ConfigureMMU(start, end, alias, flags uint32)

ConfigureMMU (re)configures the first-level translation tables for the provided memory range with the argument attribute flags. An alias argument greater than zero specifies the physical address corresponding to the start argument in case virtual memory is required, otherwise a flat 1:1 mapping is set.

func (*CPU) DebugStatus 

func (cpu *CPU) DebugStatus() uint32

DebugStatus returns the contents of the ARM DBGAUTHSTATUS register, useful to get the current state of the processor debug permissions (C11.11.1, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

func (*CPU) DisableCache 

func (cpu *CPU) DisableCache()

DisableCache disables the ARM instruction and data caches.

func (*CPU) DisableFastInterrupts 

func (cpu *CPU) DisableFastInterrupts(saved bool)

DisableFastInterrupts masks FIQ interrupts in the current or saved program status.

func (*CPU) DisableInterrupts 

func (cpu *CPU) DisableInterrupts(saved bool)

DisableInterrupts masks IRQ interrupts in the current or saved program status.

func (*CPU) EnableCache 

func (cpu *CPU) EnableCache()

EnableCache activates the ARM instruction and data caches.

func (*CPU) EnableFastInterrupts 

func (cpu *CPU) EnableFastInterrupts(saved bool)

EnableFastInterrupts unmasks FIQ interrupts in the current or saved program status.

func (*CPU) EnableInterrupts 

func (cpu *CPU) EnableInterrupts(saved bool)

EnableInterrupts unmasks IRQ interrupts in the current or saved program status.

func (*CPU) EnableSMP 

func (cpu *CPU) EnableSMP()

EnableSMP sets the SMP bit in Cortex-A7 Auxiliary Control Register, to enable coherent requests to the processor. This must be ensured before caches and MMU are enabled or any cache and TLB maintenance operations are performed (p115, Cortex™-A7 MPCore® Technical Reference Manual r0p5).

func (*CPU) EnableVFP 

func (cpu *CPU) EnableVFP()

EnableVFP activates the ARM Vector-Floating-Point co-processor.

func (*CPU) FlushDataCache 

func (cpu *CPU) FlushDataCache()

FlushDataCache flushes the ARM data cache.

func (*CPU) FlushInstructionCache 

func (cpu *CPU) FlushInstructionCache()

FlushInstructionCache flushes the ARM instruction cache.

func (*CPU) FlushTLBs 

func (cpu *CPU) FlushTLBs()

FlushTLBs flushes the ARM Translation Lookaside Buffers.

func (*CPU) Init 

func (cpu *CPU) Init(vbar uint32)

Init performs initialization of an ARM core instance, the argument must be a pointer to a 64 kB memory area which will be reserved for storing the exception vector table, L1/L2 page tables and the exception stack (see https://github.com/usbarmory/tamago/wiki/Internals#memory-layout).

func (*CPU) InitGenericTimers 

func (cpu *CPU) InitGenericTimers(base uint32, freq int32)

InitGenericTimers initializes ARM Cortex-A7 timers.

func (*CPU) InitGlobalTimers 

func (cpu *CPU) InitGlobalTimers()

InitGlobalTimers initializes ARM Cortex-A9 timers.

func (*CPU) InitMMU 

func (cpu *CPU) InitMMU()

InitMMU initializes the first-level translation tables for all available memory with a flat mapping and privileged attribute flags.

The first 4096 bytes (0x00000000 - 0x00001000) are flagged as invalid to trap null pointers, applications that need to make use of this memory space must use ConfigureMMU to reconfigure as required.

All available memory is marked as non-executable except for the range returned by runtime.TextRegion().

func (*CPU) Mode 

func (cpu *CPU) Mode() int

Mode returns the processor mode.

func (*CPU) NonSecure 

func (cpu *CPU) NonSecure() bool

NonSecure returns whether the processor security mode is non-secure (e.g. TrustZone Normal World.

func (*CPU) NonSecureAccessControl 

func (cpu *CPU) NonSecureAccessControl(nsacr uint32)

NonSecureAccessControl sets the NSACR register value, which defines the Non-Secure access permissions to coprocessors.

func (*CPU) Secure 

func (cpu *CPU) Secure() bool

Secure returns whether the processor security mode is secure (e.g. TrustZone Secure World).

func (*CPU) SetAccessPermissions 

func (cpu *CPU) SetAccessPermissions(start, end, ap, domain uint32)

SetAccessPermissions (re)configures the first-level translation tables for the provided memory range with the argument domain and access permissions.

func (*CPU) SetAttribute 

func (cpu *CPU) SetAttribute(start, end, pos, val uint32)

SetAttribute (re)configures a single attribute flag on the first-level translation tables for the provided memory range.

func (*CPU) SetAttributes 

func (cpu *CPU) SetAttributes(start, end, flags uint32)

SetAttributes (re)configures the first-level translation tables for the provided memory range with the argument attribute flags.

func (*CPU) SetDownCounter 

func (cpu *CPU) SetDownCounter(t int32, enable bool)

SetDownCounter sets a physical countdown timer.

func (*CPU) SetTimer 

func (cpu *CPU) SetTimer(ns int64)

SetTimer sets the timer to the argument nanoseconds value.

func (*CPU) SetVectorTable 

func (cpu *CPU) SetVectorTable(t VectorTable)

SetVectorTable updates the CPU exception handling vector table with the addresses of the functions defined in the passed structure.

type ExceptionHandler 

type ExceptionHandler func()

type VectorTable 

type VectorTable struct {
	Reset         ExceptionHandler
	Undefined     ExceptionHandler
	Supervisor    ExceptionHandler
	PrefetchAbort ExceptionHandler
	DataAbort     ExceptionHandler
	IRQ           ExceptionHandler
	FIQ           ExceptionHandler
}

func SystemVectorTable 

func SystemVectorTable() VectorTable

SystemVectorTable returns a vector table that, for all exceptions, switches to system mode and calls the SystemExceptionHandler on the Go runtime stack within goroutine g0.

Source Files

View all Source files

Directories

Path Synopsis
Package gic implements a driver for the ARM Generic Interrupt Controller.
 Package gic implements a driver for the ARM Generic Interrupt Controller.
Package tzc380 implements a driver for the ARM TrustZone Address Space Controller TZC-380.
 Package tzc380 implements a driver for the ARM TrustZone Address Space Controller TZC-380.

Jump to

Keyboard shortcuts

? : This menu
/ : Search site
f or F : Jump to
y or Y : Canonical URL
go.dev uses cookies from Google to deliver and enhance the quality of its services and to analyze traffic. Learn more.