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Documentation

Overview

CMSIS abstraction functions.

Original copyright:

Copyright (c) 2009 - 2015 ARM LIMITED

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Index

• Constants
• Variables
• func Asm(asm string)
• func AsmFull(asm string, regs map[string]interface{}) uintptr
• func DisableIRQ(irq uint32)
• func DisableInterrupts() uintptr
• func EnableIRQ(irq uint32)
• func EnableInterrupts(mask uintptr)
• func SVCall0(num uintptr) uintptr
• func SVCall1(num uintptr, a1 interface{}) uintptr
• func SVCall2(num uintptr, a1, a2 interface{}) uintptr
• func SVCall3(num uintptr, a1, a2, a3 interface{}) uintptr
• func SVCall4(num uintptr, a1, a2, a3, a4 interface{}) uintptr
• func SemihostingCall(num int, arg uintptr) int
• func SetPriority(irq uint32, priority uint32)
• func SetupSystemTimer(cyclecount uint32) error
• type NVIC_Type
• type SYST_Type

Constants

const (
	SCS_BASE  = 0xE000E000
	SYST_BASE = SCS_BASE + 0x0010
	NVIC_BASE = SCS_BASE + 0x0100
)

const (
	// SYST.SYST_CSR: SysTick Control and Status Register
	SYST_CSR_ENABLE_Pos    = 0x0     // Position of ENABLE field.
	SYST_CSR_ENABLE_Msk    = 0x1     // Bit mask of ENABLE field.
	SYST_CSR_ENABLE        = 0x1     // Bit ENABLE.
	SYST_CSR_TICKINT_Pos   = 0x1     // Position of TICKINT field.
	SYST_CSR_TICKINT_Msk   = 0x2     // Bit mask of TICKINT field.
	SYST_CSR_TICKINT       = 0x2     // Bit TICKINT.
	SYST_CSR_CLKSOURCE_Pos = 0x2     // Position of CLKSOURCE field.
	SYST_CSR_CLKSOURCE_Msk = 0x4     // Bit mask of CLKSOURCE field.
	SYST_CSR_CLKSOURCE     = 0x4     // Bit CLKSOURCE.
	SYST_CSR_COUNTFLAG_Pos = 0x10    // Position of COUNTFLAG field.
	SYST_CSR_COUNTFLAG_Msk = 0x10000 // Bit mask of COUNTFLAG field.
	SYST_CSR_COUNTFLAG     = 0x10000 // Bit COUNTFLAG.

	// SYST.SYST_RVR: SysTick Reload Value Register
	SYST_RVR_RELOAD_Pos = 0x0      // Position of RELOAD field.
	SYST_RVR_RELOAD_Msk = 0xffffff // Bit mask of RELOAD field.

	// SYST.SYST_CVR: SysTick Current Value Register
	SYST_CVR_CURRENT_Pos = 0x0      // Position of CURRENT field.
	SYST_CVR_CURRENT_Msk = 0xffffff // Bit mask of CURRENT field.

	// SYST.SYST_CALIB: SysTick Calibration Value Register
	SYST_CALIB_TENMS_Pos = 0x0        // Position of TENMS field.
	SYST_CALIB_TENMS_Msk = 0xffffff   // Bit mask of TENMS field.
	SYST_CALIB_SKEW_Pos  = 0x1e       // Position of SKEW field.
	SYST_CALIB_SKEW_Msk  = 0x40000000 // Bit mask of SKEW field.
	SYST_CALIB_SKEW      = 0x40000000 // Bit SKEW.
	SYST_CALIB_NOREF_Pos = 0x1f       // Position of NOREF field.
	SYST_CALIB_NOREF_Msk = 0x80000000 // Bit mask of NOREF field.
	SYST_CALIB_NOREF     = 0x80000000 // Bit NOREF.
)

Bitfields for SYST: System Timer

const (
	// Regular semihosting calls
	SemihostingClock      = 0x10
	SemihostingClose      = 0x02
	SemihostingElapsed    = 0x30
	SemihostingErrno      = 0x13
	SemihostingFileLen    = 0x0C
	SemihostingGetCmdline = 0x15
	SemihostingHeapInfo   = 0x16
	SemihostingIsError    = 0x08
	SemihostingIsTTY      = 0x09
	SemihostingOpen       = 0x01
	SemihostingRead       = 0x06
	SemihostingReadByte   = 0x07
	SemihostingRemove     = 0x0E
	SemihostingRename     = 0x0F
	SemihostingSeek       = 0x0A
	SemihostingSystem     = 0x12
	SemihostingTickFreq   = 0x31
	SemihostingTime       = 0x11
	SemihostingTmpName    = 0x0D
	SemihostingWrite      = 0x05
	SemihostingWrite0     = 0x04
	SemihostingWriteByte  = 0x03

	// Angel semihosting calls
	SemihostingEnterSVC        = 0x17
	SemihostingReportException = 0x18
)

Semihosting commands. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html

const (
	// Hardware vector reason codes
	SemihostingBranchThroughZero = 0x20000
	SemihostingUndefinedInstr    = 0x20001
	SemihostingSoftwareInterrupt = 0x20002
	SemihostingPrefetchAbort     = 0x20003
	SemihostingDataAbort         = 0x20004
	SemihostingAddressException  = 0x20005
	SemihostingIRQ               = 0x20006
	SemihostingFIQ               = 0x20007

	// Software reason codes
	SemihostingBreakPoint          = 0x20020
	SemihostingWatchPoint          = 0x20021
	SemihostingStepComplete        = 0x20022
	SemihostingRunTimeErrorUnknown = 0x20023
	SemihostingInternalError       = 0x20024
	SemihostingUserInterruption    = 0x20025
	SemihostingApplicationExit     = 0x20026
	SemihostingStackOverflow       = 0x20027
	SemihostingDivisionByZero      = 0x20028
	SemihostingOSSpecific          = 0x20029
)

Special codes for the Angel Semihosting interface. https://www.keil.com/support/man/docs/armcc/armcc_pge1358787050566.htm

Variables

var NVIC = (*NVIC_Type)(unsafe.Pointer(uintptr(NVIC_BASE)))

var SYST = (*SYST_Type)(unsafe.Pointer(uintptr(SYST_BASE)))

Functions

func Asm

func Asm(asm string)

Run the given assembly code. The code will be marked as having side effects, as it doesn't produce output and thus would normally be eliminated by the optimizer.

func AsmFull

func AsmFull(asm string, regs map[string]interface{}) uintptr

Run the given inline assembly. The code will be marked as having side effects, as it would otherwise be optimized away. The inline assembly string recognizes template values in the form {name}, like so:

arm.AsmFull(
    "str {value}, {result}",
    map[string]interface{}{
        "value":  1
        "result": &dest,
    })

You can use {} in the asm string (which expands to a register) to set the return value.

func DisableIRQ

func DisableIRQ(irq uint32)

Disable the given interrupt number.

func DisableInterrupts

func DisableInterrupts() uintptr

DisableInterrupts disables all interrupts, and returns the old interrupt state.

func EnableIRQ

func EnableIRQ(irq uint32)

Enable the given interrupt number.

func EnableInterrupts

func EnableInterrupts(mask uintptr)

EnableInterrupts enables all interrupts again. The value passed in must be the mask returned by DisableInterrupts.

func SVCall0

func SVCall0(num uintptr) uintptr

Run the following system call (SVCall) with 0 arguments.

func SVCall1

func SVCall1(num uintptr, a1 interface{}) uintptr

Run the following system call (SVCall) with 1 argument.

func SVCall2

func SVCall2(num uintptr, a1, a2 interface{}) uintptr

Run the following system call (SVCall) with 2 arguments.

func SVCall3

func SVCall3(num uintptr, a1, a2, a3 interface{}) uintptr

Run the following system call (SVCall) with 3 arguments.

func SVCall4

func SVCall4(num uintptr, a1, a2, a3, a4 interface{}) uintptr

Run the following system call (SVCall) with 4 arguments.

func SemihostingCall

func SemihostingCall(num int, arg uintptr) int

Call a semihosting function. TODO: implement it here using inline assembly.

func SetPriority

func SetPriority(irq uint32, priority uint32)

Set the priority of the given interrupt number. Note that the priority is given as a 0-255 number, where some of the lower bits are not implemented by the hardware. For example, to set a low interrupt priority, use 0xc0, which is equivalent to using priority level 5 when the hardware has 8 priority levels. Also note that the priority level is inverted in ARM: a lower number means it is a more important interrupt and will interrupt ISRs with a higher interrupt priority.

func SetupSystemTimer

func SetupSystemTimer(cyclecount uint32) error

Set up the system timer to generate periodic tick events. This will cause SysTick_Handler to fire once per tick. The cyclecount parameter is a counter value which can range from 0 to 0xffffff. A value of 0 disables the timer.

Types

type NVIC_Type

type NVIC_Type struct {
	ISER [8]volatile.Register32 // Interrupt Set-enable Registers

	ICER [8]volatile.Register32 // Interrupt Clear-enable Registers

	ISPR [8]volatile.Register32 // Interrupt Set-pending Registers

	ICPR [8]volatile.Register32 // Interrupt Clear-pending Registers

	IABR [8]volatile.Register32 // Interrupt Active Bit Registers

	IPR [60]volatile.Register32 // Interrupt Priority Registers
	// contains filtered or unexported fields
}

Nested Vectored Interrupt Controller (NVIC).

Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CIHIGCIF.html

type SYST_Type

type SYST_Type struct {
	SYST_CSR   volatile.Register32
	SYST_RVR   volatile.Register32
	SYST_CVR   volatile.Register32
	SYST_CALIB volatile.Register32
}

System Timer (SYST)

Source: https://static.docs.arm.com/ddi0403/e/DDI0403E_d_armv7m_arm.pdf B3.3