Documentation ¶
Index ¶
Constants ¶
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const ( Bit0 = 1 << iota // 0b0000_0001 Bit1 // 0b0000_0010 Bit2 // 0b0000_0100 Bit3 // 0b0000_1000 Bit4 // 0b0001_0000 Bit5 // 0b0010_0000 Bit6 // 0b0100_0000 Bit7 // 0b1000_0000 )
Variables ¶
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var CommonIO = map[HardwareAddress]interface{}{ P1: uint8(0xCF), TAC: uint8(0xF8), NR10: uint8(0x80), NR11: uint8(0xBF), NR12: uint8(0xF3), NR14: uint8(0x00), NR21: uint8(0x3F), NR22: uint8(0x00), NR24: uint8(0xBF), NR30: uint8(0x7F), NR31: uint8(0xFF), NR32: uint8(0x9F), NR33: uint8(0xBF), NR41: uint8(0xFF), NR42: uint8(0x00), NR43: uint8(0x00), NR50: uint8(0x77), NR51: uint8(0xF3), NR52: uint8(0xF1), BGP: uint8(0xFC), LCDC: uint8(0x91), IF: uint8(0xE1), STAT: uint8(0x87), }
CommonIO - common starting IO registers.
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var ModelBootROMChecksums = map[[16]byte]Model{ {0xA8, 0xF8, 0x4A, 0x0A, 0xC4, 0x4D, 0xA5, 0xD3, 0xF0, 0xEE, 0x19, 0xF9, 0xCE, 0xA8, 0x0A, 0x8C}: DMG0, {0x32, 0xfb, 0xbd, 0x84, 0x16, 0x8d, 0x34, 0x82, 0x95, 0x6e, 0xb3, 0xc5, 0x05, 0x16, 0x37, 0xf5}: DMGABC, {0x71, 0xa3, 0x78, 0xe7, 0x1f, 0xf3, 0x0b, 0x2d, 0x8a, 0x1f, 0x02, 0xbf, 0x5c, 0x78, 0x96, 0xaa}: MGB, {0xd5, 0x74, 0xd4, 0xf9, 0xc1, 0x2f, 0x30, 0x50, 0x74, 0x79, 0x8f, 0x54, 0xc0, 0x91, 0xa8, 0xb4}: SGB, {0xe0, 0x43, 0x0b, 0xca, 0x99, 0x25, 0xfb, 0x98, 0x82, 0x14, 0x8f, 0xd2, 0xdc, 0x24, 0x18, 0xc1}: SGB2, {0x7c, 0x77, 0x3f, 0x3c, 0x0b, 0x01, 0xcb, 0x73, 0xbc, 0xa8, 0xe8, 0x32, 0x27, 0x28, 0x7b, 0x7f}: CGB0, {0xdb, 0xfc, 0xe9, 0xdb, 0x9d, 0xea, 0xa2, 0x56, 0x7f, 0x6a, 0x84, 0xfd, 0xe5, 0x5f, 0x96, 0x80}: CGBABC, {0xe6, 0xce, 0xfb, 0x5f, 0x7d, 0x35, 0x2f, 0xab, 0x66, 0x81, 0x98, 0x97, 0x63, 0x91, 0x7c, 0x73}: AGB, }
ModelBootROMChecksums - MD5 checksums of the boot ROMs of each model
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var ModelEvents = map[Model][]Event{ DMG0: { {scheduler.APUChannel1, 48}, {scheduler.APUSample, 93}, {scheduler.PPUStartVBlank, 252}, {scheduler.APUFrameSequencer, 984}, {scheduler.APUChannel3, 984}, }, SGB: { {scheduler.APUSample, 64}, {scheduler.PPUHBlank, 196}, {scheduler.APUFrameSequencer, 952}, {scheduler.APUChannel3, 952}, }, }
ModelEvents - model specific starting events (this isn't accurate at all:)
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var ModelIO = map[Model]map[HardwareAddress]interface{}{ Unset: {DIV: uint16(0xABC9)}, DMG0: {DIV: uint16(0x182F), LY: uint8(0x92)}, DMGABC: {DIV: uint16(0xABC9)}, CGBABC: {P1: uint8(0xFF), DIV: uint16(0x2675), BCPS: uint8(0xC8), OCPS: uint8(0xD0)}, CGB0: {DIV: uint16(0x2881)}, SGB: {P1: uint8(0xFF), DIV: uint16(0xD85F), NR52: uint8(0xF0), STAT: uint8(0x85), LY: uint8(0x00)}, SGB2: {DIV: uint16(0xD84F)}, AGB: {DIV: uint16(0x267B)}, }
ModelIO - model specific starting IO registers.
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var ModelNames = map[Model]string{ DMG0: "DMG0", DMGABC: "DMG", CGB0: "CGB0", CGBABC: "CGB", MGB: "MGB", SGB: "SGB", SGB2: "SGB2", AGB: "AGB", Unset: "Unset", }
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var ModelRegisters = map[Model][]uint8{ Unset: {0x01, 0x00, 0xFF, 0x13, 0x00, 0xC1, 0x84, 0x03}, DMG0: {0x01, 0x00, 0xFF, 0x13, 0x00, 0xC1, 0x84, 0x03}, DMGABC: {0x01, 0xB0, 0x00, 0x13, 0x00, 0xD8, 0x01, 0x4D}, CGB0: {0x11, 0x80, 0x00, 0x00, 0x00, 0x08, 0x00, 0x7C}, CGBABC: {0x11, 0x80, 0x00, 0x00, 0x00, 0x08, 0x00, 0x7C}, MGB: {0xFF, 0xB0, 0x00, 0x13, 0x00, 0xD8, 0x01, 0x4D}, SGB: {0x01, 0x00, 0x00, 0x14, 0x00, 0x00, 0xC0, 0x60}, SGB2: {0xFF, 0x00, 0x00, 0x14, 0x00, 0x00, 0xC0, 0x60}, AGB: {0x11, 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x7C}, }
ModelRegisters - model specific starting CPU registers.
Functions ¶
This section is empty.
Types ¶
type HardwareAddress ¶
type HardwareAddress = uint16 // Hardware register located at 0xFF00 - 0xFF7F & 0xFFFF
const ( P1 HardwareAddress = 0xFF00 // Joypad select/input SB HardwareAddress = 0xFF01 // Serial transfer data SC HardwareAddress = 0xFF02 // Controls the serial port DIV HardwareAddress = 0xFF04 // Divider register (upper 8 bits of SYS_CLK) TIMA HardwareAddress = 0xFF05 // Timer register TMA HardwareAddress = 0xFF06 // Loaded into TIMA when TIMA overflows TAC HardwareAddress = 0xFF07 // Controls the timer IF HardwareAddress = 0xFF0F // IF is used to request interrupts NR10 HardwareAddress = 0xFF10 // Channel 1 Sweep NR11 HardwareAddress = 0xFF11 // Channel 1 length timer & duty cycle NR12 HardwareAddress = 0xFF12 // Channel 1 volume & envelope NR13 HardwareAddress = 0xFF13 // Channel 1 period low NR14 HardwareAddress = 0xFF14 // Channel 1 period high & control NR21 HardwareAddress = 0xFF16 // Channel 2 length timer & duty cycle NR22 HardwareAddress = 0xFF17 // Channel 2 volume & envelope NR23 HardwareAddress = 0xFF18 // Channel 2 period low NR24 HardwareAddress = 0xFF19 // Channel 2 period high & control NR30 HardwareAddress = 0xFF1A // Channel 3 DAC enable NR31 HardwareAddress = 0xFF1B // Channel 3 length timer NR32 HardwareAddress = 0xFF1C // Channel 3 output level NR33 HardwareAddress = 0xFF1D // Channel 3 period low NR34 HardwareAddress = 0xFF1E // Channel 3 period high & control NR41 HardwareAddress = 0xFF20 // Channel 4 length timer NR42 HardwareAddress = 0xFF21 // Channel 4 volume & envelope NR43 HardwareAddress = 0xFF22 // Channel 4 frequency & randomness NR44 HardwareAddress = 0xFF23 // Channel 4 control NR50 HardwareAddress = 0xFF24 // Master volume & VIN panning NR51 HardwareAddress = 0xFF25 // Sound panning NR52 HardwareAddress = 0xFF26 // Sound On/Off LCDC HardwareAddress = 0xFF40 // LCDC is used to control the LCD STAT HardwareAddress = 0xFF41 // Reports the LCD status SCY HardwareAddress = 0xFF42 // Vertical scroll position of background SCX HardwareAddress = 0xFF43 // Horizontal scroll position of the background LY HardwareAddress = 0xFF44 // LY is the current scanline LYC HardwareAddress = 0xFF45 // Compared to LY and sets the LYC coincidence flag DMA HardwareAddress = 0xFF46 // DMA Source address & control BGP HardwareAddress = 0xFF47 // Background palette data OBP0 HardwareAddress = 0xFF48 // Object palette 0 data OBP1 HardwareAddress = 0xFF49 // Object palette 1 data WY HardwareAddress = 0xFF4A // Window Y position WX HardwareAddress = 0xFF4B // Window X position + 7 KEY0 HardwareAddress = 0xFF4C // Indicates CGB compatibility mode KEY1 HardwareAddress = 0xFF4D // Used for speed switching in CGB mode VBK HardwareAddress = 0xFF4F // VRAM Bank (1-bit) BDIS HardwareAddress = 0xFF50 // (B)oot ROM (d)(i)(s)able HDMA1 HardwareAddress = 0xFF51 // VRAM DMA source (high) HDMA2 HardwareAddress = 0xFF52 // VRAM DMA source (low) HDMA3 HardwareAddress = 0xFF53 // VRAM DMA destination (high) HDMA4 HardwareAddress = 0xFF54 // VRAM DMA destination (low) HDMA5 HardwareAddress = 0xFF55 // VRAM DMA length/mode/start BCPS HardwareAddress = 0xFF68 // Background colour palette specification BCPD HardwareAddress = 0xFF69 // Background colour palette data OCPS HardwareAddress = 0xFF6A // Object colour palette specification OCPD HardwareAddress = 0xFF6B // Object colour palette data OPRI HardwareAddress = 0xFF6C // Sets sprite priority in CGB mode SVBK HardwareAddress = 0xFF70 // WRAM Bank 01h-07h RP HardwareAddress = 0xFF56 // Controls the IR port FF72 HardwareAddress = 0xFF72 // Undocumented FF73 HardwareAddress = 0xFF73 // Undocumented FF74 HardwareAddress = 0xFF74 // Undocumented FF75 HardwareAddress = 0xFF75 // Undocumented PCM12 HardwareAddress = 0xFF76 // Channel 1/2 PCM data PCM34 HardwareAddress = 0xFF77 // Channel 3/4 PCM Data IE HardwareAddress = 0xFFFF // Controls which interrupts are enabled )
type Model ¶
type Model int // The Model used in emulation.
const ( Unset Model = iota // Unset - Model hasn't been set - behaves as DMGABC DMG0 // DMG0 - early Game Boy, only released in Japan DMGABC // DMGABC - Standard Game Boy CGB0 // CGB0 - early Game Boy Colour, only released in Japan CGBABC // CGBABC - Standard Game Boy Colour MGB // MGB - Pocket Game Boy SGB // SGB - Super Game Boy SGB2 // SGB2 - Super Game Boy 2 AGB // AGB - Game Boy Advance )
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