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Constants ¶
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const ( // Load/Store Operations LDA mnemonic LDX LDY STA STX STY // Register Operations TAX TSX TAY TXA TXS TYA // Stack instructions PHA PHP PLA PLP // Logical instructions AND EOR ORA BIT // Arithmetic instructions ADC SBC CMP CPX CPY // Increment/Decrement instructions INC INX INY DEC DEX DEY // Shift instructions ASL LSR ROL ROR // Jump instructions JMP JSR RTS RTI // Branch instructions BCC BCS BEQ BMI BNE BPL BVC BVS // Flag control instructions CLC CLD CLI CLV SEC SED SEI // Misc BRK NOP // Unofficial LAX SAX DCP ISB SLO RLA SRE RRA )
Variables ¶
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Functions ¶
Types ¶
type Bus ¶
type Bus interface { // ReadCPU read a byte by CPU. // // A location pointed of address may be one of NES component or other RAM/ROM. ReadCPU(addr uint16) uint8 // WriteCPU write a byte from any component by CPU. // // A location pointed of address may be one of NES component or other RAM/ROM. WriteCPU(addr uint16, value uint8) }
Bus is the abstraction of memory access seen from CPU emulator.
This interface provides a strategy of memory access to target.
type CPU ¶
type CPU struct {
// Accumulator, Index X/Y register
A, X, Y uint8
// Stack pointer
S uint8
// Status register
P Status
// Program counter
PC uint16
// clock cycle
Cycles uint64
// contains filtered or unexported fields
}
CPU emulates CPU behaviors
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