Retracted: All the beta tags are retracted and replaced with "pre" to prevent users
from accidentally upgrading into the broken beta 1.
Documentation
¶
Index ¶
- Constants
- func InstructionName(i asm.Instruction) string
- func RegisterName(r asm.Register) string
- type Assembler
- type AssemblerImpl
- func (a *AssemblerImpl) Assemble() ([]byte, error)
- func (a *AssemblerImpl) CompileConditionalRegisterSet(cond asm.ConditionalRegisterState, dstReg asm.Register)
- func (a *AssemblerImpl) CompileConstToRegister(instruction asm.Instruction, value asm.ConstantValue, ...) (inst asm.Node)
- func (a *AssemblerImpl) CompileJump(jmpInstruction asm.Instruction) asm.Node
- func (a *AssemblerImpl) CompileJumpToRegister(jmpInstruction asm.Instruction, reg asm.Register)
- func (a *AssemblerImpl) CompileLeftShiftedRegisterToRegister(instruction asm.Instruction, shiftedSourceReg asm.Register, ...)
- func (a *AssemblerImpl) CompileMemoryToRegister(instruction asm.Instruction, sourceBaseReg asm.Register, ...)
- func (a *AssemblerImpl) CompileMemoryToVectorRegister(instruction asm.Instruction, srcBaseReg asm.Register, ...)
- func (a *AssemblerImpl) CompileMemoryWithRegisterOffsetToRegister(instruction asm.Instruction, srcBaseReg, srcOffsetReg, dstReg asm.Register)
- func (a *AssemblerImpl) CompileMemoryWithRegisterOffsetToVectorRegister(instruction asm.Instruction, srcBaseReg, srcOffsetRegister asm.Register, ...)
- func (a *AssemblerImpl) CompileReadInstructionAddress(destinationRegister asm.Register, ...)
- func (a *AssemblerImpl) CompileRegisterAndConstToNone(instruction asm.Instruction, src asm.Register, srcConst asm.ConstantValue)
- func (a *AssemblerImpl) CompileRegisterToMemory(instruction asm.Instruction, ...)
- func (a *AssemblerImpl) CompileRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg, dstOffsetReg asm.Register)
- func (a *AssemblerImpl) CompileRegisterToRegister(instruction asm.Instruction, from, to asm.Register)
- func (a *AssemblerImpl) CompileRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, ...)
- func (a *AssemblerImpl) CompileStandAlone(instruction asm.Instruction) asm.Node
- func (a *AssemblerImpl) CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register)
- func (a *AssemblerImpl) CompileStaticConstToVectorRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register, ...)
- func (a *AssemblerImpl) CompileThreeRegistersToRegister(instruction asm.Instruction, src1, src2, src3, dst asm.Register)
- func (a *AssemblerImpl) CompileTwoRegistersToNone(instruction asm.Instruction, src1, src2 asm.Register)
- func (a *AssemblerImpl) CompileTwoRegistersToRegister(instruction asm.Instruction, src1, src2, dst asm.Register)
- func (a *AssemblerImpl) CompileTwoVectorRegistersToVectorRegister(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register, ...)
- func (a *AssemblerImpl) CompileTwoVectorRegistersToVectorRegisterWithConst(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register, ...)
- func (a *AssemblerImpl) CompileVectorRegisterToMemory(instruction asm.Instruction, srcReg, dstBaseReg asm.Register, ...)
- func (a *AssemblerImpl) CompileVectorRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, ...)
- func (a *AssemblerImpl) CompileVectorRegisterToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, ...)
- func (a *AssemblerImpl) CompileVectorRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, ...)
- func (a *AssemblerImpl) CompileVectorRegisterToVectorRegisterWithConst(instruction asm.Instruction, srcReg, dstReg asm.Register, ...)
- type VectorArrangement
- type VectorIndex
Constants ¶
View Source
const ( // CondEQ is the eq (equal) condition code CondEQ = asm.ConditionalRegisterStateUnset + 1 + iota // CondNE is the ne (not equal) condition code CondNE // CondHS is the hs (unsigned higher or same) condition code CondHS // CondLO is the lo (unsigned lower) condition code CondLO // CondMI is the mi (negative) condition code CondMI // CondPL is the pl (positive or zero) condition code CondPL // CondVS is the vs (signed overflow) condition code CondVS // CondVC is the vc (no signed overflow) condition code CondVC // CondHI is the hi (unsigned higher) condition code CondHI // CondLS is the ls (unsigned lower or same) condition code CondLS // CondGE is the ge (signed greater than or equal) condition code CondGE // CondLT is the lt (signed less than) condition code CondLT // CondGT is the gt (signed greater than) condition code CondGT // CondLE is the le (signed less than or equal) condition code CondLE // CondAL is the al (always executed) condition code CondAL // CondNV has the same meaning as CondAL CondNV )
Arm64-specific register states.
Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm See https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/condition-codes-1-condition-flags-and-codes
View Source
const ( // RegR0 is the R0 register RegR0 asm.Register = asm.NilRegister + 1 + iota // RegR1 is the R1 register RegR1 // RegR2 is the R2 register RegR2 // RegR3 is the R3 register RegR3 // RegR4 is the R4 register RegR4 // RegR5 is the R5 register RegR5 // RegR6 is the R6 register RegR6 // RegR7 is the R7 register RegR7 // RegR8 is the R8 register RegR8 // RegR9 is the R9 register RegR9 // RegR10 is the R10 register RegR10 // RegR11 is the R11 register RegR11 // RegR12 is the R12 register RegR12 // RegR13 is the R13 register RegR13 // RegR14 is the R14 register RegR14 // RegR15 is the R15 register RegR15 // RegR16 is the R16 register RegR16 // RegR17 is the R17 register RegR17 // RegR18 is the R18 register RegR18 // RegR19 is the R19 register RegR19 // RegR20 is the R20 register RegR20 // RegR21 is the R21 register RegR21 // RegR22 is the R22 register RegR22 // RegR23 is the R23 register RegR23 // RegR24 is the R24 register RegR24 // RegR25 is the R25 register RegR25 // RegR26 is the R26 register RegR26 // RegR27 is the R27 register RegR27 // RegR28 is the R28 register RegR28 // RegR29 is the R29 register RegR29 // RegR30 is the R30 register RegR30 // RegRZR is the RZR register (read-only, always returning zero) RegRZR // RegV0 is the V0 register RegV0 // RegV1 is the V1 register RegV1 // RegV2 is the V2 register RegV2 // RegV3 is the V3 register RegV3 // RegV4 is the V4 register RegV4 // RegV5 is the V5 register RegV5 // RegV6 is the V6 register RegV6 // RegV7 is the V7 register RegV7 // RegV8 is the V8 register RegV8 // RegV9 is the V9 register RegV9 // RegV10 is the V10 register RegV10 // RegV11 is the V11 register RegV11 // RegV12 is the V12 register RegV12 // RegV13 is the V13 register RegV13 // RegV14 is the V14 register RegV14 // RegV15 is the V15 register RegV15 // RegV16 is the V16 register RegV16 // RegV17 is the V17 register RegV17 // RegV18 is the V18 register RegV18 // RegV19 is the V19 register RegV19 // RegV20 is the V20 register RegV20 // RegV21 is the V21 register RegV21 // RegV22 is the V22 register RegV22 // RegV23 is the V23 register RegV23 // RegV24 is the V24 register RegV24 // RegV25 is the V25 register RegV25 // RegV26 is the V26 register RegV26 // RegV27 is the V27 register RegV27 // RegV28 is the V28 register RegV28 // RegV29 is the V29 register RegV29 // RegV30 is the V30 register RegV30 // RegV31 is the V31 register RegV31 // RegFPSR is the FPSR register RegFPSR // RegCondEQ encodes CondEQ into a field that would otherwise store a register RegCondEQ // RegCondNE encodes CondNE into a field that would otherwise store a register RegCondNE // RegCondHS encodes CondHS into a field that would otherwise store a register RegCondHS // RegCondLO encodes CondLO into a field that would otherwise store a register RegCondLO // RegCondMI encodes CondMI into a field that would otherwise store a register RegCondMI // RegCondPL encodes CondPL into a field that would otherwise store a register RegCondPL // RegCondVS encodes CondVS into a field that would otherwise store a register RegCondVS // RegCondVC encodes CondVC into a field that would otherwise store a register RegCondVC // RegCondHI encodes CondHI into a field that would otherwise store a register RegCondHI // RegCondLS encodes CondLS into a field that would otherwise store a register RegCondLS // RegCondGE encodes CondGE into a field that would otherwise store a register RegCondGE // RegCondLT encodes CondLT into a field that would otherwise store a register RegCondLT // RegCondGT encodes CondGT into a field that would otherwise store a register RegCondGT // RegCondLE encodes CondLE into a field that would otherwise store a register RegCondLE // RegCondAL encodes CondAL into a field that would otherwise store a register RegCondAL // RegCondNV encodes CondNV into a field that would otherwise store a register RegCondNV )
Arm64-specific registers.
Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm See https://developer.arm.com/documentation/dui0801/a/Overview-of-AArch64-state/Predeclared-core-register-names-in-AArch64-state
View Source
const ( // NOP is the NOP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NOP NOP asm.Instruction = iota // RET is the RET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RET RET // ADD is the ADD instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- ADD // ADDS is the ADDS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADDS--shifted-register- ADDS // ADDW is the ADD instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- ADDW // ADR is the ADR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADR ADR // AND is the AND instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--shifted-register- AND // ANDIMM32 is the AND(immediate) instruction in 32-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en ANDIMM32 // ANDIMM64 is the AND(immediate) instruction in 64-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en ANDIMM64 // ANDW is the AND instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--register- ANDW // ASR is the ASR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- ASR // ASRW is the ASR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- ASRW // B is the B instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B B // BCONDEQ is the B.cond instruction with CondEQ. BCONDEQ // BCONDGE is the B.cond instruction with CondGE. BCONDGE // BCONDGT is the B.cond instruction with CondGT. BCONDGT // BCONDHI is the B.cond instruction with CondHI. BCONDHI // BCONDHS is the B.cond instruction with CondHS. BCONDHS // BCONDLE is the B.cond instruction with CondLE. BCONDLE // BCONDLO is the B.cond instruction with CondLO. BCONDLO // BCONDLS is the B.cond instruction with CondLS. BCONDLS // BCONDLT is the B.cond instruction with CondLT. BCONDLT // BCONDMI is the B.cond instruction with CondMI. BCONDMI // BCONDPL is the B.cond instruction with CondPL. BCONDPL // BCONDNE is the B.cond instruction with CondNE. BCONDNE // BCONDVS is the B.cond instruction with CondVS. BCONDVS // CLZ is the CLZ instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ CLZ // CLZW is the CLZ instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ CLZW // CMP is the CMP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- CMP // CMPW is the CMP instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- CMPW // CSET is the CSET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CSET CSET // EOR is the EOR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- EOR // EORW is the EOR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- EORW // FABSD is the FABS instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- FABSD // FABSS is the FABS instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- FABSS // FADDD is the FADD instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- FADDD // FADDS is the FADD instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- FADDS // FCMPD is the FCMP instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP FCMPD // FCMPS is the FCMP instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP FCMPS // FCVTDS is the FCVT instruction, for single to double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT FCVTDS // FCVTSD is the FCVT instruction, for double to single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT FCVTSD // FCVTZSD is the FCVTZS instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- FCVTZSD // FCVTZSDW is the FCVTZS instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- FCVTZSDW // FCVTZSS is the FCVTZS instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- FCVTZSS // FCVTZSSW is the FCVTZS instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- FCVTZSSW // FCVTZUD is the FCVTZU instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- FCVTZUD // FCVTZUDW is the FCVTZU instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- FCVTZUDW // FCVTZUS is the FCVTZU instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- FCVTZUS // FCVTZUSW is the FCVTZU instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- FCVTZUSW // FDIVD is the FDIV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- FDIVD // FDIVS is the FDIV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- FDIVS // FMAXD is the FMAX instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- FMAXD // FMAXS is the FMAX instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- FMAXS // FMIND is the FMIN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- FMIND // FMINS is the FMIN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- FMINS // FMOVD is the FMOV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- FMOVD // FMOVS is the FMOV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- FMOVS // FMULD is the FMUL instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- FMULD // FMULS is the FMUL instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- FMULS // FNEGD is the FNEG instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- FNEGD // FNEGS is the FNEG instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- FNEGS // FRINTMD is the FRINTM instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- FRINTMD // FRINTMS is the FRINTM instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- FRINTMS // FRINTND is the FRINTN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- FRINTND // FRINTNS is the FRINTN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- FRINTNS // FRINTPD is the FRINTP instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- FRINTPD // FRINTPS is the FRINTP instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- FRINTPS // FRINTZD is the FRINTZ instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- FRINTZD // FRINTZS is the FRINTZ instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- FRINTZS // FSQRTD is the FSQRT instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- FSQRTD // FSQRTS is the FSQRT instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- FSQRTS // FSUBD is the FSUB instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- FSUBD // FSUBS is the FSUB instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- FSUBS // LSL is the LSL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- LSL // LSLW is the LSL instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- LSLW // LSR is the LSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- LSR // LSRW is the LSR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- LSRW // FLDRD is the LDR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en FLDRD // FLDRS is the LDR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en FLDRS // LDRD is the LDR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en LDRD // LDRW is the LDR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en LDRW // LDRSBD is the LDRSB instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- LDRSBD // LDRSBW is the LDRSB instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- LDRSBW // LDRB is the LDRB instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--register- LDRB // LDRSHD is the LDRSHW instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- LDRSHD // LDRSHW is the LDRSHW instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- LDRSHW // LDRH is the LDRH instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--register- LDRH // LDRSW is the LDRSW instruction https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSW--register- LDRSW // FSTRD is the STR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en FSTRD // FSTRS is the STR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en FSTRS // STRD is the STR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en STRD // STRW is the STR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en STRW // STRH is the STRH instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRH--register---Store-Register-Halfword--register--?lang=en STRH // STRB is the STRB instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRB--register---Store-Register-Byte--register--?lang=en STRB // MOVD moves a double word from register to register, or const to register. MOVD // MOVW moves a word from register to register, or const to register. MOVW // MRS is the MRS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MRS MRS // MSR is the MSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSR--register- MSR // MSUB is the MSUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB MSUB // MSUBW is the MSUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB MSUBW // MUL is the MUL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL MUL // MULW is the MUL instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL MULW // NEG is the NEG instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG NEG // NEGW is the NEG instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG NEGW // ORR is the ORR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- ORR // ORRW is the ORR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- ORRW // RBIT is the RBIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT RBIT // RBITW is the RBIT instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT RBITW // ROR is the ROR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- ROR // RORW is the RORW instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- RORW // SCVTFD is the SCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- SCVTFD // SCVTFS is the SCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- SCVTFS // SCVTFWD is the SCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- SCVTFWD // SCVTFWS is the SCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- SCVTFWS // SDIV is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV SDIV // SDIVW is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV SDIVW // SUB is the SUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- SUB // SUBS is the SUBS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUBS--shifted-register- SUBS // SUBW is the SUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- SUBW // SXTB is the SXTB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB SXTB // SXTBW is the SXTB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB SXTBW // SXTH is the SXTH instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH SXTH // SXTHW is the SXTH instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH SXTHW // SXTW is the SXTW instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTW SXTW // UCVTFD is the UCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- UCVTFD // UCVTFS is the UCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- UCVTFS // UCVTFWD is the UCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- UCVTFWD // UCVTFWS is the UCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- UCVTFWS // UDIV is the UDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV UDIV // UDIVW is the UDIV instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV UDIVW // VBIT is the BIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/BIT--vector- VBIT // VCNT is the CNT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/CNT--vector- VCNT // VMOV has different semantics depending on the types of operands: // - LDR(SIMD&FP) if the src is memory and dst is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/LDR--immediate--SIMD-FP---Load-SIMD-FP-Register--immediate-offset-- // - LDR(literal, SIMD&FP) if the src is static const and dst is a vector: https://developer.arm.com/documentation/dui0801/h/A64-Floating-point-Instructions/LDR--literal--SIMD-and-FP- // - STR(SIMD&FP) if the dst is memory and src is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset-- VMOV // UMOV is the UMOV instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMOV--Unsigned-Move-vector-element-to-general-purpose-register-?lang=en UMOV // INSGEN is the INS(general) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--general---Insert-vector-element-from-general-purpose-register-?lang=en INSGEN // INSELEM is the INS(element) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en INSELEM // UADDLV is the UADDLV(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/UADDLV--vector- UADDLV // VADD is the ADD(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/ADD--vector- VADD // VFADDS is the FADD(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- VFADDS // VFADDD is the FADD(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- VFADDD // VSUB is the SUB(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/SUB--vector- VSUB // VFSUBS is the FSUB(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- VFSUBS // VFSUBD is the FSUB(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- VFSUBD // SSHL is the SSHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en SSHL // SSHLL is the SSHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- SSHLL // USHL is the USHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en USHL // USHLL is the USHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- USHLL // LD1R is the LD1R instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LD1R--Load-one-single-element-structure-and-Replicate-to-all-lanes--of-one-register-- LD1R // SMOV32 is the 32-bit variant of SMOV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/SMOV--vector- SMOV32 // DUPGEN is the DUP(general) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--general---Duplicate-general-purpose-register-to-vector- DUPGEN // DUPELEM is the DUP(element) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--element---Duplicate-vector-element-to-vector-or-scalar- DUPELEM // UMAXP is the UMAXP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/UMAXP--vector- UMAXP // UMINV is the UMINV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/UMINV--vector- UMINV // CMEQ is the CMEQ(vector, register) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/CMEQ--vector--register- CMEQ // CMEQZERO is the CMEP(zero) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMEQ--zero---Compare-bitwise-Equal-to-zero--vector--?lang=en CMEQZERO // ADDP is the ADDP(scalar) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADDP--scalar---Add-Pair-of-elements--scalar--?lang=en ADDP // VADDP is the ADDP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/ADDP--vector- // Note: prefixed by V to distinguish from the non-vector variant of ADDP(scalar). VADDP // TBL1 is the TBL instruction whose source is one vector. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- TBL1 // TBL2 is the TBL instruction whose source is two vectors. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- TBL2 // NOT is the NOT(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/NOT--Bitwise-NOT--vector--?lang=en NOT // VAND is the AND(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector-- // Note: prefixed by V to distinguish from the non-vector variant of AND. VAND // VORR is the ORR(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ORR--vector--register---Bitwise-inclusive-OR--vector--register-- // Note: prefixed by V to distinguish from the non-vector variant of ORR. VORR // BSL https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BSL--Bitwise-Select- BSL // BIC is the BIC(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BIC--vector--register---Bitwise-bit-Clear--vector--register-- BIC // VFNEG is the FNEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/FNEG--vector---Floating-point-Negate--vector-- // Note: prefixed by V to distinguish from the non-vector variant of FNEG. VFNEG // ADDV is the ADDV instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ADDV--Add-across-Vector- ADDV // ZIP1 is the ZIP1 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ZIP1--Zip-vectors--primary--?lang=en ZIP1 // SSHR is the SSHR(immediate,vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHR--Signed-Shift-Right--immediate--?lang=en SSHR // EXT is the EXT instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/EXT--Extract-vector-from-pair-of-vectors-?lang=en EXT // CMGT is the CMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGT--register---Compare-signed-Greater-than--vector--?lang=en CMGT // CMHI is the CMHI(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHI--register---Compare-unsigned-Higher--vector--?lang=en CMHI // CMGE is the CMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGE--register---Compare-signed-Greater-than-or-Equal--vector--?lang=en CMGE // CMHS is the CMHS(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHS--register---Compare-unsigned-Higher-or-Same--vector--?lang=en CMHS // FCMEQ is the FCMEQ(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMEQ--register---Floating-point-Compare-Equal--vector--?lang=en FCMEQ // FCMGT is the FCMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGT--register---Floating-point-Compare-Greater-than--vector--?lang=en FCMGT // FCMGE is the FCMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGE--register---Floating-point-Compare-Greater-than-or-Equal--vector--?lang=en FCMGE // VFMUL is the FMUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMUL--vector---Floating-point-Multiply--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFMUL // VFDIV is the FDIV(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FDIV--vector---Floating-point-Divide--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFDIV // VFSQRT is the FSQRT(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSQRT--vector---Floating-point-Square-Root--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFSQRT // VFMIN is the FMIN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMIN--vector---Floating-point-minimum--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFMIN // VFMAX is the FMAX(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMAX--vector---Floating-point-Maximum--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFMAX // VFABS is the FABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FABS--vector---Floating-point-Absolute-value--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFABS // VFRINTP is the FRINTP(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTP--vector---Floating-point-Round-to-Integral--toward-Plus-infinity--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFRINTP // VFRINTM is the FRINTM(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTM--vector---Floating-point-Round-to-Integral--toward-Minus-infinity--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFRINTM // VFRINTZ is the FRINTZ(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTZ--vector---Floating-point-Round-to-Integral--toward-Zero--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFRINTZ // VFRINTN is the FRINTN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTN--vector---Floating-point-Round-to-Integral--to-nearest-with-ties-to-even--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFRINTN // VMUL is the MUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/MUL--vector---Multiply--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VMUL // VNEG is the NEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/NEG--vector---Negate--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VNEG // VABS is the ABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ABS--Absolute-value--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VABS // VSQADD is the SQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQADD--Signed-saturating-Add-?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VSQADD // VUQADD is the UQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQADD--Unsigned-saturating-Add-?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VUQADD // VSQSUB is the SQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQSUB--Signed-saturating-Subtract-?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VSQSUB // VUQSUB is the UQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQSUB--Unsigned-saturating-Subtract-?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VUQSUB // SMIN is the SMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMIN--Signed-Minimum--vector--?lang=en SMIN // SMAX is the SMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMAX--Signed-Maximum--vector--?lang=en SMAX // UMIN is the UMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMIN--Unsigned-Minimum--vector--?lang=en UMIN // UMAX is the UMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMAX--Unsigned-Maximum--vector--?lang=en UMAX // URHADD is the URHADD instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/URHADD--Unsigned-Rounding-Halving-Add-?lang=en URHADD // REV64 is the REV64 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/REV64--Reverse-elements-in-64-bit-doublewords--vector--?lang=en REV64 // XTN is the XTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/XTN--XTN2--Extract-Narrow-?lang=en XTN // VUMLAL is the UMLAL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMLAL--UMLAL2--vector---Unsigned-Multiply-Add-Long--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VUMLAL // SHLL is the SHLL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SHLL--SHLL2--Shift-Left-Long--by-element-size--?lang=en SHLL // SADDLP is the SADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SADDLP--Signed-Add-Long-Pairwise-?lang=en SADDLP // UADDLP is the UADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UADDLP--Unsigned-Add-Long-Pairwise-?lang=en UADDLP // SSHLL2 is the SSHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- SSHLL2 // USHLL2 is the USHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- USHLL2 // SQRDMULH is the SQRDMULH(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQRDMULH--vector---Signed-saturating-Rounding-Doubling-Multiply-returning-High-half-?lang=en SQRDMULH // SMULL is the SMULL(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en SMULL // SMULL2 is the SMULL2(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en SMULL2 // UMULL is the UMULL instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en UMULL // UMULL2 is the UMULL2 instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en UMULL2 // VFCVTZS is the FCVTZS(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZS--vector--integer---Floating-point-Convert-to-Signed-integer--rounding-toward-Zero--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFCVTZS // VFCVTZU is the FCVTZU(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZU--vector--integer---Floating-point-Convert-to-Unsigned-integer--rounding-toward-Zero--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VFCVTZU // SQXTN is the SQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en SQXTN // UQXTN is the UQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQXTN--UQXTN2--Unsigned-saturating-extract-Narrow-?lang=en UQXTN // SQXTN2 is the SQXTN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en SQXTN2 // SQXTUN is the SQXTUN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en SQXTUN // SQXTUN2 is the SQXTUN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en SQXTUN2 // VSCVTF is the SCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SCVTF--vector--integer---Signed-integer-Convert-to-Floating-point--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VSCVTF // VUCVTF is the UCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UCVTF--vector--integer---Unsigned-integer-Convert-to-Floating-point--vector--?lang=en // Note: prefixed by V to distinguish from the non-vector variant. VUCVTF // FCVTL is the FCVTL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTL--FCVTL2--Floating-point-Convert-to-higher-precision-Long--vector--?lang=en FCVTL // FCVTN is the FCVTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTN--FCVTN2--Floating-point-Convert-to-lower-precision-Narrow--vector--?lang=en FCVTN )
Arm64-specific instructions.
Note: This only defines arm64 instructions used by wazero's compiler. Note: Naming conventions partially match the Go assembler: https://go.dev/doc/asm
View Source
const VectorIndexNone = ^VectorIndex(0)
VectorIndexNone indicates no vector index specified.
Variables ¶
This section is empty.
Functions ¶
func InstructionName ¶
func InstructionName(i asm.Instruction) string
InstructionName returns the name of the given instruction
func RegisterName ¶
RegisterName returns the name of a given register
Types ¶
type Assembler ¶
type Assembler interface {
asm.AssemblerBase
// CompileMemoryWithRegisterOffsetToRegister adds an instruction where source operand is the memory address
// specified as `srcBaseReg + srcOffsetReg` and dst is the register `dstReg`.
CompileMemoryWithRegisterOffsetToRegister(instruction asm.Instruction, srcBaseReg, srcOffsetReg, dstReg asm.Register)
// CompileRegisterToMemoryWithRegisterOffset adds an instruction where source operand is the register `srcReg`,
// and the destination is the memory address specified as `dstBaseReg + dstOffsetReg`
CompileRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg, dstOffsetReg asm.Register)
// CompileTwoRegistersToRegister adds an instruction where source operands consists of two registers `src1` and `src2`,
// and the destination is the register `dst`.
CompileTwoRegistersToRegister(instruction asm.Instruction, src1, src2, dst asm.Register)
// CompileThreeRegistersToRegister adds an instruction where source operands consist of three registers
// `src1`, `src2` and `src3`, and destination operands consist of `dst` register.
CompileThreeRegistersToRegister(instruction asm.Instruction, src1, src2, src3, dst asm.Register)
// CompileTwoRegistersToNone adds an instruction where source operands consist of two registers `src1` and `src2`,
// and destination operand is unspecified.
CompileTwoRegistersToNone(instruction asm.Instruction, src1, src2 asm.Register)
// CompileRegisterAndConstToNone adds an instruction where source operands consist of one register `src` and
// constant `srcConst`, and destination operand is unspecified.
CompileRegisterAndConstToNone(instruction asm.Instruction, src asm.Register, srcConst asm.ConstantValue)
// CompileLeftShiftedRegisterToRegister adds an instruction where source operand is the "left shifted register"
// represented as `srcReg << shiftNum` and the destination is the register `dstReg`.
CompileLeftShiftedRegisterToRegister(
instruction asm.Instruction,
shiftedSourceReg asm.Register,
shiftNum asm.ConstantValue,
srcReg, dstReg asm.Register,
)
// CompileConditionalRegisterSet adds an instruction to set 1 on dstReg if the condition satisfies,
// otherwise set 0.
CompileConditionalRegisterSet(cond asm.ConditionalRegisterState, dstReg asm.Register)
// CompileMemoryToVectorRegister adds an instruction where source operands is the memory address specified by
// `srcBaseReg+srcOffset` and the destination is `dstReg` vector register.
CompileMemoryToVectorRegister(instruction asm.Instruction, srcBaseReg asm.Register, srcOffset asm.ConstantValue,
dstReg asm.Register, arrangement VectorArrangement)
// CompileMemoryWithRegisterOffsetToVectorRegister is the same as CompileMemoryToVectorRegister except that the
// offset is specified by the `srcOffsetRegister` register.
CompileMemoryWithRegisterOffsetToVectorRegister(instruction asm.Instruction, srcBaseReg,
srcOffsetRegister asm.Register, dstReg asm.Register, arrangement VectorArrangement)
// CompileVectorRegisterToMemory adds an instruction where source operand is `srcReg` vector register and the
// destination is the memory address specified by `dstBaseReg+dstOffset`.
CompileVectorRegisterToMemory(instruction asm.Instruction, srcReg, dstBaseReg asm.Register,
dstOffset asm.ConstantValue, arrangement VectorArrangement)
// CompileVectorRegisterToMemoryWithRegisterOffset is the same as CompileVectorRegisterToMemory except that the
// offset is specified by the `dstOffsetRegister` register.
CompileVectorRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg,
dstOffsetRegister asm.Register, arrangement VectorArrangement)
// CompileRegisterToVectorRegister adds an instruction where source operand is `srcReg` general purpose register and
// the destination is the `dstReg` vector register. The destination vector's arrangement and index of element can be
// given by `arrangement` and `index`, but not all the instructions will use them.
CompileRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
arrangement VectorArrangement, index VectorIndex)
// CompileVectorRegisterToRegister adds an instruction where destination operand is `dstReg` general purpose register
// and the source is the `srcReg` vector register. The source vector's arrangement and index of element can be
// given by `arrangement` and `index`, but not all the instructions will use them.
CompileVectorRegisterToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
arrangement VectorArrangement, index VectorIndex)
// CompileVectorRegisterToVectorRegister adds an instruction where both source and destination operands are vector
// registers. The vector's arrangement can be specified `arrangement`, and the source and destination element's
// index are given by `srcIndex` and `dstIndex` respectively, but not all the instructions will use them.
CompileVectorRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
arrangement VectorArrangement, srcIndex, dstIndex VectorIndex)
// CompileVectorRegisterToVectorRegisterWithConst is the same as CompileVectorRegisterToVectorRegister but the
// additional constant can be provided.
// For example, the const can be used to specify the shift amount for USHLL instruction.
CompileVectorRegisterToVectorRegisterWithConst(instruction asm.Instruction, srcReg, dstReg asm.Register,
arrangement VectorArrangement, c asm.ConstantValue)
// CompileStaticConstToRegister adds an instruction where the source operand is StaticConstant located in
// the memory and the destination is the dstReg.
CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register)
// CompileStaticConstToVectorRegister adds an instruction where the source operand is StaticConstant located in
// the memory and the destination is the dstReg.
CompileStaticConstToVectorRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register,
arrangement VectorArrangement)
// CompileTwoVectorRegistersToVectorRegister adds an instruction where source are two vectors and destination is one
// vector. The vector's arrangement can be specified `arrangement`.
CompileTwoVectorRegistersToVectorRegister(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register,
arrangement VectorArrangement)
// CompileTwoVectorRegistersToVectorRegisterWithConst is the same as CompileTwoVectorRegistersToVectorRegister except
// that this also accept additional constant.
// For example EXIT instruction needs the extraction target immediate as const.
CompileTwoVectorRegistersToVectorRegisterWithConst(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register,
arrangement VectorArrangement, c asm.ConstantValue)
}
Assembler is the interface for arm64 specific assembler.
type AssemblerImpl ¶
type AssemblerImpl struct {
asm.BaseAssemblerImpl
Root, Current *nodeImpl
Buf *bytes.Buffer
// MaxDisplacementForConstantPool is fixed to defaultMaxDisplacementForConstPool
// but have it as a field here for testability.
MaxDisplacementForConstantPool int
// contains filtered or unexported fields
}
AssemblerImpl implements Assembler.
func NewAssembler ¶
func NewAssembler(temporaryRegister asm.Register) *AssemblerImpl
func (*AssemblerImpl) Assemble ¶
func (a *AssemblerImpl) Assemble() ([]byte, error)
Assemble implements asm.AssemblerBase
func (*AssemblerImpl) CompileConditionalRegisterSet ¶
func (a *AssemblerImpl) CompileConditionalRegisterSet(cond asm.ConditionalRegisterState, dstReg asm.Register)
CompileConditionalRegisterSet implements Assembler.CompileConditionalRegisterSet
func (*AssemblerImpl) CompileConstToRegister ¶
func (a *AssemblerImpl) CompileConstToRegister( instruction asm.Instruction, value asm.ConstantValue, destinationReg asm.Register, ) (inst asm.Node)
CompileConstToRegister implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileJump ¶
func (a *AssemblerImpl) CompileJump(jmpInstruction asm.Instruction) asm.Node
CompileJump implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileJumpToRegister ¶
func (a *AssemblerImpl) CompileJumpToRegister(jmpInstruction asm.Instruction, reg asm.Register)
CompileJumpToRegister implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileLeftShiftedRegisterToRegister ¶
func (a *AssemblerImpl) CompileLeftShiftedRegisterToRegister( instruction asm.Instruction, shiftedSourceReg asm.Register, shiftNum asm.ConstantValue, srcReg, dstReg asm.Register, )
CompileLeftShiftedRegisterToRegister implements Assembler.CompileLeftShiftedRegisterToRegister
func (*AssemblerImpl) CompileMemoryToRegister ¶
func (a *AssemblerImpl) CompileMemoryToRegister( instruction asm.Instruction, sourceBaseReg asm.Register, sourceOffsetConst asm.ConstantValue, destinationReg asm.Register, )
CompileMemoryToRegister implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileMemoryToVectorRegister ¶
func (a *AssemblerImpl) CompileMemoryToVectorRegister( instruction asm.Instruction, srcBaseReg asm.Register, dstOffset asm.ConstantValue, dstReg asm.Register, arrangement VectorArrangement)
CompileMemoryToVectorRegister implements Assembler.CompileMemoryToVectorRegister
func (*AssemblerImpl) CompileMemoryWithRegisterOffsetToRegister ¶
func (a *AssemblerImpl) CompileMemoryWithRegisterOffsetToRegister( instruction asm.Instruction, srcBaseReg, srcOffsetReg, dstReg asm.Register, )
CompileMemoryWithRegisterOffsetToRegister implements Assembler.CompileMemoryWithRegisterOffsetToRegister
func (*AssemblerImpl) CompileMemoryWithRegisterOffsetToVectorRegister ¶
func (a *AssemblerImpl) CompileMemoryWithRegisterOffsetToVectorRegister(instruction asm.Instruction, srcBaseReg, srcOffsetRegister asm.Register, dstReg asm.Register, arrangement VectorArrangement)
CompileMemoryWithRegisterOffsetToVectorRegister implements Assembler.CompileMemoryWithRegisterOffsetToVectorRegister
func (*AssemblerImpl) CompileReadInstructionAddress ¶
func (a *AssemblerImpl) CompileReadInstructionAddress( destinationRegister asm.Register, beforeAcquisitionTargetInstruction asm.Instruction, )
CompileReadInstructionAddress implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileRegisterAndConstToNone ¶
func (a *AssemblerImpl) CompileRegisterAndConstToNone( instruction asm.Instruction, src asm.Register, srcConst asm.ConstantValue, )
CompileRegisterAndConstToNone implements Assembler.CompileRegisterAndConstToNone
func (*AssemblerImpl) CompileRegisterToMemory ¶
func (a *AssemblerImpl) CompileRegisterToMemory( instruction asm.Instruction, sourceRegister, destinationBaseRegister asm.Register, destinationOffsetConst asm.ConstantValue, )
CompileRegisterToMemory implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileRegisterToMemoryWithRegisterOffset ¶
func (a *AssemblerImpl) CompileRegisterToMemoryWithRegisterOffset( instruction asm.Instruction, srcReg, dstBaseReg, dstOffsetReg asm.Register, )
CompileRegisterToMemoryWithRegisterOffset implements Assembler.CompileRegisterToMemoryWithRegisterOffset
func (*AssemblerImpl) CompileRegisterToRegister ¶
func (a *AssemblerImpl) CompileRegisterToRegister(instruction asm.Instruction, from, to asm.Register)
CompileRegisterToRegister implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileRegisterToVectorRegister ¶
func (a *AssemblerImpl) CompileRegisterToVectorRegister( instruction asm.Instruction, srcReg, dstReg asm.Register, arrangement VectorArrangement, index VectorIndex)
CompileRegisterToVectorRegister implements Assembler.CompileRegisterToVectorRegister
func (*AssemblerImpl) CompileStandAlone ¶
func (a *AssemblerImpl) CompileStandAlone(instruction asm.Instruction) asm.Node
CompileStandAlone implements the same method as documented on asm.AssemblerBase.
func (*AssemblerImpl) CompileStaticConstToRegister ¶
func (a *AssemblerImpl) CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register)
CompileStaticConstToRegister implements Assembler.CompileStaticConstToVectorRegister
func (*AssemblerImpl) CompileStaticConstToVectorRegister ¶
func (a *AssemblerImpl) CompileStaticConstToVectorRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register, arrangement VectorArrangement)
CompileStaticConstToVectorRegister implements Assembler.CompileStaticConstToVectorRegister
func (*AssemblerImpl) CompileThreeRegistersToRegister ¶
func (a *AssemblerImpl) CompileThreeRegistersToRegister( instruction asm.Instruction, src1, src2, src3, dst asm.Register, )
CompileThreeRegistersToRegister implements Assembler.CompileThreeRegistersToRegister
func (*AssemblerImpl) CompileTwoRegistersToNone ¶
func (a *AssemblerImpl) CompileTwoRegistersToNone(instruction asm.Instruction, src1, src2 asm.Register)
CompileTwoRegistersToNone implements Assembler.CompileTwoRegistersToNone
func (*AssemblerImpl) CompileTwoRegistersToRegister ¶
func (a *AssemblerImpl) CompileTwoRegistersToRegister(instruction asm.Instruction, src1, src2, dst asm.Register)
CompileTwoRegistersToRegister implements Assembler.CompileTwoRegistersToRegister
func (*AssemblerImpl) CompileTwoVectorRegistersToVectorRegister ¶
func (a *AssemblerImpl) CompileTwoVectorRegistersToVectorRegister(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register, arrangement VectorArrangement)
CompileTwoVectorRegistersToVectorRegister implements Assembler.CompileTwoVectorRegistersToVectorRegister.
func (*AssemblerImpl) CompileTwoVectorRegistersToVectorRegisterWithConst ¶
func (a *AssemblerImpl) CompileTwoVectorRegistersToVectorRegisterWithConst(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register, arrangement VectorArrangement, c asm.ConstantValue)
CompileTwoVectorRegistersToVectorRegisterWithConst implements Assembler.CompileTwoVectorRegistersToVectorRegisterWithConst.
func (*AssemblerImpl) CompileVectorRegisterToMemory ¶
func (a *AssemblerImpl) CompileVectorRegisterToMemory( instruction asm.Instruction, srcReg, dstBaseReg asm.Register, dstOffset asm.ConstantValue, arrangement VectorArrangement)
CompileVectorRegisterToMemory implements Assembler.CompileVectorRegisterToMemory
func (*AssemblerImpl) CompileVectorRegisterToMemoryWithRegisterOffset ¶
func (a *AssemblerImpl) CompileVectorRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg, dstOffsetRegister asm.Register, arrangement VectorArrangement)
CompileVectorRegisterToMemoryWithRegisterOffset implements Assembler.CompileVectorRegisterToMemoryWithRegisterOffset
func (*AssemblerImpl) CompileVectorRegisterToRegister ¶
func (a *AssemblerImpl) CompileVectorRegisterToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, arrangement VectorArrangement, index VectorIndex)
CompileVectorRegisterToRegister implements Assembler.CompileVectorRegisterToRegister
func (*AssemblerImpl) CompileVectorRegisterToVectorRegister ¶
func (a *AssemblerImpl) CompileVectorRegisterToVectorRegister( instruction asm.Instruction, srcReg, dstReg asm.Register, arrangement VectorArrangement, srcIndex, dstIndex VectorIndex)
CompileVectorRegisterToVectorRegister implements Assembler.CompileVectorRegisterToVectorRegister
func (*AssemblerImpl) CompileVectorRegisterToVectorRegisterWithConst ¶
func (a *AssemblerImpl) CompileVectorRegisterToVectorRegisterWithConst(instruction asm.Instruction, srcReg, dstReg asm.Register, arrangement VectorArrangement, c asm.ConstantValue)
CompileVectorRegisterToVectorRegisterWithConst implements Assembler.CompileVectorRegisterToVectorRegisterWithConst
type VectorArrangement ¶
type VectorArrangement byte
VectorArrangement is the arrangement of data within a vector register.
const ( // VectorArrangementNone is an arrangement indicating no data is stored. VectorArrangementNone VectorArrangement = iota // VectorArrangement8B is an arrangement of 8 bytes (64-bit vector) VectorArrangement8B // VectorArrangement16B is an arrangement of 16 bytes (128-bit vector) VectorArrangement16B // VectorArrangement4H is an arrangement of 4 half precisions (64-bit vector) VectorArrangement4H // VectorArrangement8H is an arrangement of 8 half precisions (128-bit vector) VectorArrangement8H // VectorArrangement2S is an arrangement of 2 single precisions (64-bit vector) VectorArrangement2S // VectorArrangement4S is an arrangement of 4 single precisions (128-bit vector) VectorArrangement4S // VectorArrangement1D is an arrangement of 1 double precision (64-bit vector) VectorArrangement1D // VectorArrangement2D is an arrangement of 2 double precisions (128-bit vector) VectorArrangement2D // VectorArrangementB is a size specifier of byte VectorArrangementB // VectorArrangementH is a size specifier of word (16-bit) VectorArrangementH // VectorArrangementS is a size specifier of double word (32-bit) VectorArrangementS // VectorArrangementD is a size specifier of quad word (64-bit) VectorArrangementD // VectorArrangementQ is a size specifier of the entire vector (128-bit) VectorArrangementQ )
func (VectorArrangement) String ¶
func (v VectorArrangement) String() (ret string)
type VectorIndex ¶
type VectorIndex byte
VectorIndex is the index of an element of a vector register
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