README
¶
cpu
internal/cpu(in Go standard lib) with these detections:
AVX512
Cache Size
Invariant TSC
It also provides:
False sharing range, see
X86FalseSharingRange
for X86 platform.TSC frequency
Name
Family & Model
Acknowledgement
Documentation
¶
Overview ¶
Package cpu implements processor feature detection used by the Go standard library.
Index ¶
Constants ¶
const ( IntelFam6SkylakeL = "06_4EH" IntelFam6Skylake = "06_5EH" IntelFam6XeonScalable = "06_55H" IntelFam6KabylakeL = "06_8EH" IntelFam6Kabylake = "06_9EH" )
Copied from: CPUID Signature values of DisplayFamily and DisplayModel, in Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 4: Model-Specific Registers & https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/intel-family.h
const ( Other = iota Intel AMD VIA Transmeta NSC KVM // Kernel-based Virtual Machine MSVM // Microsoft Hyper-V or Windows Virtual PC VMware XenHVM Bhyve Hygon )
const CacheLineSize = 64
const GOARCH = "amd64"
const X86FalseSharingRange = 128
"Loads data or instructions from memory to the second-level cache. To use the streamer, organize the data or instructions in blocks of 128 bytes, aligned on 128 bytes." From <Intel® 64 and IA-32 architectures optimization reference manual>, in section 3.7.3 "Hardware Prefetching for Second-Level Cache"
In practice, I have found use 128bytes can gain better performance than 64bytes (one cache line).
Variables ¶
var ARM64 arm64
var PPC64 ppc64
var S390X s390x
var X86 x86
Functions ¶
This section is empty.