Versions in this module Expand all Collapse all v3 v3.0.3 Jul 5, 2024 v3.0.2 Mar 27, 2024 v3.0.1 Mar 13, 2024 v3.0.0 Jan 30, 2024 Changes in this version + type AllInstCPIStack struct + AllInstCPI float64 + BranchStack float64 + LDSStack float64 + SIMDStack float64 + ScalarStack float64 + TotalStackBase float64 + VMemStack float64 + type AllocStatus byte + const AllocStatusFree + const AllocStatusReserved + const AllocStatusToReserve + const AllocStatusUsed + type BranchUnit struct + func NewBranchUnit(cu *ComputeUnit, scratchpadPreparer ScratchpadPreparer, alu emu.ALU) *BranchUnit + func (u *BranchUnit) AcceptWave(wave *wavefront.Wavefront, now sim.VTimeInSec) + func (u *BranchUnit) CanAcceptWave() bool + func (u *BranchUnit) Flush() + func (u *BranchUnit) IsIdle() bool + func (u *BranchUnit) Run(now sim.VTimeInSec) bool + type Builder struct + func MakeBuilder() Builder + func (b *Builder) Build(name string) *ComputeUnit + func (b Builder) WithEngine(engine sim.Engine) Builder + func (b Builder) WithFreq(f sim.Freq) Builder + func (b Builder) WithLog2CachelineSize(n uint64) Builder + func (b Builder) WithSGPRCount(count int) Builder + func (b Builder) WithSIMDCount(n int) Builder + func (b Builder) WithVGPRCount(counts []int) Builder + func (b Builder) WithVisTracer(t tracing.Tracer) Builder + type CPIStackTracer struct + func NewCPIStackInstHook(cu *ComputeUnit, timeTeller sim.TimeTeller) *CPIStackTracer + func (h *CPIStackTracer) EndTask(task tracing.Task) + func (h *CPIStackTracer) GetCPIStack() map[string]float64 + func (h *CPIStackTracer) GetSIMDCPIStack() map[string]float64 + func (h *CPIStackTracer) StartTask(task tracing.Task) + func (h *CPIStackTracer) StepTask(task tracing.Task) + type ComputeUnit struct + BranchUnit SubComponent + Decoder emu.Decoder + InFlightInstFetch []*InstFetchReqInfo + InFlightScalarMemAccess []*ScalarMemAccessInfo + InFlightVectorMemAccess []VectorMemAccessInfo + InFlightVectorMemAccessLimit int + InstMem sim.Port + LDSDecoder SubComponent + LDSUnit SubComponent + SIMDUnit []SubComponent + SRegFile RegisterFile + ScalarDecoder SubComponent + ScalarMem sim.Port + ScalarUnit SubComponent + Scheduler Scheduler + ToACE sim.Port + ToCP sim.Port + ToInstMem sim.Port + ToScalarMem sim.Port + ToVectorMem sim.Port + VRegFile []RegisterFile + VectorDecoder SubComponent + VectorMemDecoder SubComponent + VectorMemModules mem.LowModuleFinder + VectorMemUnit SubComponent + WfDispatcher WfDispatcher + WfPools []*WavefrontPool + func NewComputeUnit(name string, engine sim.Engine) *ComputeUnit + func (cu *ComputeUnit) ControlPort() sim.Port + func (cu *ComputeUnit) DispatchingPort() sim.Port + func (cu *ComputeUnit) LDSBytes() int + func (cu *ComputeUnit) SRegCount() int + func (cu *ComputeUnit) Tick(now sim.VTimeInSec) bool + func (cu *ComputeUnit) UpdatePCAndSetReady(wf *wavefront.Wavefront) + func (cu *ComputeUnit) VRegCounts() []int + func (cu *ComputeUnit) WfPoolSizes() []int + type DecodeUnit struct + ExecUnits []SubComponent + func NewDecodeUnit(cu *ComputeUnit) *DecodeUnit + func (du *DecodeUnit) AcceptWave(wave *wavefront.Wavefront, now sim.VTimeInSec) + func (du *DecodeUnit) AddExecutionUnit(cuComponent SubComponent) + func (du *DecodeUnit) CanAcceptWave() bool + func (du *DecodeUnit) Flush() + func (du *DecodeUnit) IsIdle() bool + func (du *DecodeUnit) Run(now sim.VTimeInSec) bool + type FetchArbiter struct + InstBufByteSize int + func (a *FetchArbiter) Arbitrate(wfPools []*WavefrontPool) []*wavefront.Wavefront + type ISADebugger struct + func NewISADebugger(logger *log.Logger, cu *ComputeUnit) *ISADebugger + func (h *ISADebugger) EndTask(task tracing.Task) + func (h *ISADebugger) StartTask(task tracing.Task) + func (h *ISADebugger) StepTask(task tracing.Task) + type InstCountManagement struct + OtherInstCount uint64 + SIMDInstCount uint64 + TotalInstCount uint64 + type InstFetchReqInfo struct + Address uint64 + Req *mem.ReadReq + Wavefront *wavefront.Wavefront + type InstTimeManagement struct + TotalBranchTime float64 + TotalLDSTime float64 + TotalOtherTime float64 + TotalSIMDTime float64 + TotalSpecialTime float64 + TotalTime float64 + TotalVMemTime float64 + type InstTracer struct + AllInstCPIStackValues AllInstCPIStack + CountManager InstCountManagement + SIMDCPIStackValues SIMDCPIStack + ScalarInstTracer *tracing.BusyTimeTracer + TimeManager InstTimeManagement + func NewInstTracer(timeTeller sim.TimeTeller) *InstTracer + func (t *InstTracer) CalcSIMDCPIStack() + func (t *InstTracer) CalcTotalCPIStack() + func (t *InstTracer) EndTask(task tracing.Task) + func (t *InstTracer) StartTask(task tracing.Task) + func (t *InstTracer) StepTask(task tracing.Task) + type IssueArbiter struct + func NewIssueArbiter() *IssueArbiter + func (a *IssueArbiter) Arbitrate(wfPools []*WavefrontPool) []*wavefront.Wavefront + type LDSUnit struct + func NewLDSUnit(cu *ComputeUnit, scratchpadPreparer ScratchpadPreparer, alu emu.ALU) *LDSUnit + func (u *LDSUnit) AcceptWave(wave *wavefront.Wavefront, now sim.VTimeInSec) + func (u *LDSUnit) CanAcceptWave() bool + func (u *LDSUnit) Flush() + func (u *LDSUnit) IsIdle() bool + func (u *LDSUnit) Run(now sim.VTimeInSec) bool + type RegisterAccess struct + Data []byte + LaneID int + OK bool + Reg *insts.Reg + RegCount int + Time sim.VTimeInSec + WaveOffset int + type RegisterFile interface + Read func(access RegisterAccess) + Write func(access RegisterAccess) + type ResourceMask struct + func NewResourceMask(size int) *ResourceMask + func (m *ResourceMask) ConvertStatus(from, to AllocStatus) + func (m *ResourceMask) NextRegion(length int, statusReq AllocStatus) (int, bool) + func (m *ResourceMask) SetStatus(offset, length int, status AllocStatus) + func (m *ResourceMask) StatusCount(status AllocStatus) int + type SIMDCPIStack struct + BranchStack float64 + LDSStack float64 + SIMDCPI float64 + ScalarStack float64 + StackBase float64 + VMemStack float64 + type SIMDUnit struct + NumSinglePrecisionUnit int + func NewSIMDUnit(cu *ComputeUnit, name string, scratchpadPreparer ScratchpadPreparer, ...) *SIMDUnit + func (u *SIMDUnit) AcceptWave(wave *wavefront.Wavefront, now sim.VTimeInSec) + func (u *SIMDUnit) CanAcceptWave() bool + func (u *SIMDUnit) Flush() + func (u *SIMDUnit) IsIdle() bool + func (u *SIMDUnit) Name() string + func (u *SIMDUnit) Run(now sim.VTimeInSec) bool + type ScalarMemAccessInfo struct + DstSGPR *insts.Reg + Inst *wavefront.Inst + Req *mem.ReadReq + Wavefront *wavefront.Wavefront + type ScalarUnit struct + func NewScalarUnit(cu *ComputeUnit, scratchpadPreparer ScratchpadPreparer, alu emu.ALU) *ScalarUnit + func (u *ScalarUnit) AcceptWave(wave *wavefront.Wavefront, now sim.VTimeInSec) + func (u *ScalarUnit) CanAcceptWave() bool + func (u *ScalarUnit) Flush() + func (u *ScalarUnit) IsIdle() bool + func (u *ScalarUnit) Run(now sim.VTimeInSec) bool + type Scheduler interface + Flush func() + Pause func() + Resume func() + Run func(now sim.VTimeInSec) bool + type SchedulerImpl struct + func NewScheduler(cu *ComputeUnit, fetchArbiter WfArbiter, issueArbiter WfArbiter) *SchedulerImpl + func (s *SchedulerImpl) DecodeNextInst(now sim.VTimeInSec) bool + func (s *SchedulerImpl) DoFetch(now sim.VTimeInSec) bool + func (s *SchedulerImpl) DoIssue(now sim.VTimeInSec) bool + func (s *SchedulerImpl) EvaluateInternalInst(now sim.VTimeInSec) bool + func (s *SchedulerImpl) Flush() + func (s *SchedulerImpl) Pause() + func (s *SchedulerImpl) Resume() + func (s *SchedulerImpl) Run(now sim.VTimeInSec) bool + type ScratchpadPreparer interface + Commit func(instEmuState emu.InstEmuState, wf *wavefront.Wavefront) + Prepare func(instEmuState emu.InstEmuState, wf *wavefront.Wavefront) + type ScratchpadPreparerImpl struct + func NewScratchpadPreparerImpl(cu *ComputeUnit) *ScratchpadPreparerImpl + func (p *ScratchpadPreparerImpl) Commit(instEmuState emu.InstEmuState, wf *wavefront.Wavefront) + func (p *ScratchpadPreparerImpl) Prepare(instEmuState emu.InstEmuState, wf *wavefront.Wavefront) + type SimpleRegisterFile struct + ByteSizePerLane int + func NewSimpleRegisterFile(byteSize uint64, byteSizePerLane int) *SimpleRegisterFile + func (r *SimpleRegisterFile) Read(access RegisterAccess) + func (r *SimpleRegisterFile) Write(access RegisterAccess) + type SubComponent interface + AcceptWave func(wave *wavefront.Wavefront, now sim.VTimeInSec) + CanAcceptWave func() bool + Flush func() + IsIdle func() bool + Run func(now sim.VTimeInSec) bool + type VectorMemAccessInfo struct + ID string + Inst *wavefront.Inst + Read *mem.ReadReq + Wavefront *wavefront.Wavefront + Write *mem.WriteReq + func (i VectorMemAccessInfo) TaskID() string + type VectorMemoryUnit struct + func NewVectorMemoryUnit(cu *ComputeUnit, scratchpadPreparer ScratchpadPreparer, coalescer coalescer) *VectorMemoryUnit + func (u *VectorMemoryUnit) AcceptWave(wave *wavefront.Wavefront, now sim.VTimeInSec) + func (u *VectorMemoryUnit) CanAcceptWave() bool + func (u *VectorMemoryUnit) Flush() + func (u *VectorMemoryUnit) IsIdle() bool + func (u *VectorMemoryUnit) Run(now sim.VTimeInSec) bool + type WavefrontPool struct + Capacity int + VRegFile sim.Component + func NewWavefrontPool(capacity int) *WavefrontPool + func (wfp *WavefrontPool) AddWf(wf *wavefront.Wavefront) + func (wfp *WavefrontPool) Availability() int + func (wfp *WavefrontPool) RemoveWf(wf *wavefront.Wavefront) + type WfArbiter interface + Arbitrate func(wfpools []*WavefrontPool) []*wavefront.Wavefront + type WfDispatchEvent struct + IsLastInWG bool + ManagedWf *wavefront.Wavefront + MapWGReq *protocol.MapWGReq + func NewWfDispatchEvent(t sim.VTimeInSec, handler sim.Handler, Wf *wavefront.Wavefront) *WfDispatchEvent + type WfDispatcher interface + DispatchWf func(now sim.VTimeInSec, wf *wavefront.Wavefront, ...) + type WfDispatcherImpl struct + Latency int + func NewWfDispatcher(cu *ComputeUnit) *WfDispatcherImpl + func (d *WfDispatcherImpl) DispatchWf(now sim.VTimeInSec, wf *wavefront.Wavefront, ...)
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