Documentation
¶
Overview ¶
Package memory implements the Atari VCS memory model. The addresses and memory sub-packages help with this.
It is important to understand that memory is viewed differently by different parts of the VCS system. To help with this, the emulation uses what we call memory buses. These buses have nothing to do with the real hardware; they are purely conceptual and are implemented through Go interfaces.
The following ASCII diagram tries to show how the different components of the VCS are connected to the memory. What may not be clear from this diagram is that the peripheral bus only ever writes to memory. The other buses are bidirectional.
PERIPHERALS
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\/
periph bus
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\/
CPU ---- cpu bus ---- MEMORY ---- chip bus ---- TIA
\
| \
| \---- RIOT
debugger bus
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DEBUGGER
The memory itself is divided into areas, defined in the memorymap package. Removing the periph bus and debugger bus from the picture, the above diagram with memory areas added is as follows:
===* TIA ---- chip bus ---- TIA
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|===* RIOT ---- chip bus ---- RIOT
CPU ---- cpu bus -----
|===* PIA RAM
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==== Cartridge
The asterisk indicates that addresses used by the CPU are mapped to the primary mirror address. The memorymap package contains more detail on this.
Cartridge memory is accessed by whatever mirror address the CPU wants. This is because some cartridge formats might be sensitive to which mirror is being used (eg. Supercharger). Cartridges also implement a Listen() function. This is a special function outside of the bussing system. See cartridge package for details.
Note that the RIOT registers and PIA RAM are all part of the same hardware package, the PIA 6532. However, for our purposes the two memory areas are considered to be entirely separate.
Index ¶
- type VCSMemory
- func (mem *VCSMemory) GetArea(area memorymap.Area) bus.DebugBus
- func (mem VCSMemory) Peek(address uint16) (uint8, error)
- func (mem VCSMemory) Poke(address uint16, data uint8) error
- func (mem *VCSMemory) Read(address uint16) (uint8, error)
- func (mem *VCSMemory) ReadZeroPage(address uint8) (uint8, error)
- func (mem *VCSMemory) Write(address uint16, data uint8) error
Constants ¶
This section is empty.
Variables ¶
This section is empty.
Functions ¶
This section is empty.
Types ¶
type VCSMemory ¶
type VCSMemory struct {
bus.DebugBus
bus.CPUBus
// memmap is a hash for every address in the VCS address space, returning
// one of the four memory areas
Memmap []bus.DebugBus
// the four memory areas
RIOT *vcs.ChipMemory
TIA *vcs.ChipMemory
RAM *vcs.RAM
Cart *cartridge.Cartridge
// the following are only used by the debugging interface. it would be
// lovely to remove these for non-debugging emulation but there's not much
// impact on performance so they can stay for now:
//
// . a note of the last (unmapped) memory address to be accessed
// . as above but the mapped address
// . the value that was written/read from the last address accessed
// . whether the last addres accessed was written or read
// . the ID of the last memory access (currently a timestamp)
LastAccessAddress uint16
LastAccessAddressMapped uint16
LastAccessValue uint8
LastAccessWrite bool
LastAccessID int
// unused pins when reading TIA/RIOT registers take the value of the last
// value on the bus. if RandomPins is true then the values of the unusued
// pins are randomised. this is the equivalent of the Stella option "drive
// unused pins randomly on a read/peek"
RandomPins prefs.Bool
// contains filtered or unexported fields
}
VCSMemory is the monolithic representation of the memory in 2600.
func NewVCSMemory ¶
NewVCSMemory is the preferred method of initialisation for VCSMemory
func (*VCSMemory) Read ¶
Read is an implementation of CPUBus. Address will be normalised and processed by the correct memory area.
func (*VCSMemory) ReadZeroPage ¶
ReadZeroPage is an implementation of CPUBus. Address will be normalised and processed by the correct memory areas.
Source Files
Directories
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| Path | Synopsis |
|---|---|
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Package addresses countains all information about VCS addresses and registers, including canonical symbols for read and write addresses and registers.
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Package addresses countains all information about VCS addresses and registers, including canonical symbols for read and write addresses and registers. |
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Package bus defines the memory bus concept.
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Package bus defines the memory bus concept. |
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Package cartridge fully implements loading of mapping of cartridge memory.
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Package cartridge fully implements loading of mapping of cartridge memory. |
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banks
Package banks contains types that are used by the cartridge package to communicate information about catridge banks to the debugger.
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Package banks contains types that are used by the cartridge package to communicate information about catridge banks to the debugger. |
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harmony
Package harmony implements the Harmony cartridge.
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Package harmony implements the Harmony cartridge. |
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supercharger
Package supercharger implements the tape based cartridge format.
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Package supercharger implements the tape based cartridge format. |
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Package memorymap facilitates the translation of addresses to primary address equivalents.
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Package memorymap facilitates the translation of addresses to primary address equivalents. |
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Package vcs represents the areas of memory that are internal to the VCS hardware.
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Package vcs represents the areas of memory that are internal to the VCS hardware. |