bus

Documentation

Overview

Package bus defines the memory bus concept. For an explanation see the memory package documentation.

Package bus is used to define access patterns for different areas of the emulation to the VCS memory. For example, the VCS chips (the TIA and the RIOT) access memory differently to the CPU. By restricting access to memory from the chip to the ChipBus interface, we can prevent

The DebugBus is for the exclusive use of debuggers and exposes a Peek() and Poke() function.

Index

• Constants
• type CPUBus
• type CPUBusZeroPage
• type ChipBus
• type ChipData
• type DebugBus
• type UpdateBus

Constants

const (
	AddressError = "inaccessible address (%#04x)"
)

Sentinal error returned by memory package functions. Note that the error expects a numberic address, which will be formatted as four digit hex.

Types

type CPUBus

type CPUBus interface {
	Read(address uint16) (uint8, error)
	Write(address uint16, data uint8) error
}

CPUBus defines the operations for the memory system when accessed from the CPU All memory areas implement this interface because they are all accessible from the CPU (compare to ChipBus). The VCSMemory type also implements this interface and maps the read/write address to the correct memory area -- meaning that CPU access need not care which part of memory it is writing to

Addresses should be mapped to their primary mirror when accesses the RIOT, TIA or RAM; and should be unmapped when accessing cartridge memory (some cartridge mappers are sensitive to which cartridge mirror is being used).

type CPUBusZeroPage

type CPUBusZeroPage interface {
	// implementations of ReadZeroPage may just pass the address onto the
	// Read() function and return, depending on what the implementation is
	// supposed to do. for the real vcs emulation however, a zero page read
	// has consequences
	ReadZeroPage(address uint8) (uint8, error)
}

type ChipBus

type ChipBus interface {
	// ChipRead checks to see if the chip's memory area has been written to. if
	// it has the function returns true and an instance of ChipData
	ChipRead() (bool, ChipData)

	// ChipWrite writes the data to the chip memory
	ChipWrite(reg addresses.ChipRegister, data uint8)

	// LastReadRegister returns the register name of the last memory location
	// *read* by the CPU
	LastReadRegister() string
}

ChipBus defines the operations for the memory system when accessed from the VCS chips (TIA, RIOT). Only ChipMemory implements this interface.

type ChipData

type ChipData struct {
	// the canonical name of the chip register written to
	Name string

	// the data value written to the chip register
	Value uint8
}

ChipData packages together the name of the chip register that has been written to and the value that was written. Useful for passing values without losing context - for example, the UpdateBus.Update() function.

type DebugBus

type DebugBus interface {
	Peek(address uint16) (uint8, error)
	Poke(address uint16, value uint8) error
}

DebugBus defines the meta-operations for all memory areas. Think of these functions as "debugging" functions, that is operations outside of the normal operation of the machine.

type UpdateBus

type UpdateBus interface {
	Update(ChipData) bool
}

UpdateBus is a bus internal to the emulation. It exposes the Update() function of one sub-system to another sub-system. Currently used to connect the RIOT input sub-system to the TIA VBLANK (by calling Update() on the input sub-system from the TIA).