Documentation ¶
Index ¶
Constants ¶
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const ( AMD64_Rax = 0 AMD64_Rdx = 1 AMD64_Rcx = 2 AMD64_Rbx = 3 AMD64_Rsi = 4 AMD64_Rdi = 5 AMD64_Rbp = 6 AMD64_Rsp = 7 AMD64_R8 = 8 AMD64_R9 = 9 AMD64_R10 = 10 AMD64_R11 = 11 AMD64_R12 = 12 AMD64_R13 = 13 AMD64_R14 = 14 AMD64_R15 = 15 AMD64_Rip = 16 AMD64_XMM0 = 17 // XMM1 through XMM15 follow AMD64_ST0 = 33 // ST(1) through ST(7) follow AMD64_Rflags = 49 AMD64_Es = 50 AMD64_Cs = 51 AMD64_Ss = 52 AMD64_Ds = 53 AMD64_Fs = 54 AMD64_Gs = 55 AMD64_Fs_base = 58 AMD64_Gs_base = 59 AMD64_MXCSR = 64 AMD64_CW = 65 AMD64_SW = 66 AMD64_XMM16 = 67 // XMM17 through XMM31 follow AMD64_K0 = 118 // k1 through k7 follow )
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const ( ARM64_X0 = 0 // X1 through X30 follow ARM64_BP = 29 // also X29 ARM64_LR = 30 // also X30 ARM64_SP = 31 ARM64_PC = 32 ARM64_V0 = 64 // V1 through V31 follow )
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const ( I386_Eax = 0 I386_Ecx = 1 I386_Edx = 2 I386_Ebx = 3 I386_Esp = 4 I386_Ebp = 5 I386_Esi = 6 I386_Edi = 7 I386_Eip = 8 I386_Eflags = 9 I386_ST0 = 11 // ST(1) through ST(7) follow I386_XMM0 = 21 // XMM1 through XMM7 follow I386_Es = 40 I386_Cs = 41 I386_Ss = 42 I386_Ds = 43 I386_Fs = 44 I386_Gs = 45 )
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const ( // General Purpose Registers: from R0 to R31 PPC64LE_FIRST_GPR = 0 PPC64LE_R0 = PPC64LE_FIRST_GPR PPC64LE_LAST_GPR = 31 // Floating point registers: from F0 to F31 PPC64LE_FIRST_FPR = 32 PPC64LE_F0 = PPC64LE_FIRST_FPR PPC64LE_LAST_FPR = 63 // Vector (Altivec/VMX) registers: from V0 to V31 PPC64LE_FIRST_VMX = 77 PPC64LE_V0 = PPC64LE_FIRST_VMX PPC64LE_LAST_VMX = 108 // Vector Scalar (VSX) registers: from VS32 to VS63 // On ppc64le these are mapped to F0 to F31 PPC64LE_FIRST_VSX = 32 PPC64LE_VS0 = PPC64LE_FIRST_VSX PPC64LE_LAST_VSX = 63 // Condition Registers: from CR0 to CR7 PPC64LE_CR0 = 0 // Special registers PPC64LE_SP = 1 // Stack frame pointer: Gpr[1] PPC64LE_PC = 12 // The documentation refers to this as the CIA (Current Instruction Address) PPC64LE_LR = 65 // Link register )
Variables ¶
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var AMD64NameToDwarf = func() map[string]int { r := make(map[string]int) for regNum, regName := range amd64DwarfToName { r[strings.ToLower(regName)] = int(regNum) } r["eflags"] = 49 r["st0"] = 33 r["st1"] = 34 r["st2"] = 35 r["st3"] = 36 r["st4"] = 37 r["st5"] = 38 r["st6"] = 39 r["st7"] = 40 return r }()
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var ARM64NameToDwarf = func() map[string]int { r := make(map[string]int) for i := 0; i <= 32; i++ { r[fmt.Sprintf("x%d", i)] = ARM64_X0 + i } r["fp"] = 29 r["lr"] = 30 r["sp"] = 31 r["pc"] = 32 for i := 0; i <= 31; i++ { r[fmt.Sprintf("v%d", i)] = ARM64_V0 + i } return r }()
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var I386NameToDwarf = func() map[string]int { r := make(map[string]int) for regNum, regName := range i386DwarfToName { r[strings.ToLower(regName)] = regNum } r["eflags"] = 9 r["st0"] = 11 r["st1"] = 12 r["st2"] = 13 r["st3"] = 14 r["st4"] = 15 r["st5"] = 16 r["st6"] = 17 r["st7"] = 18 return r }()
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var PPC64LENameToDwarf = func() map[string]int { r := make(map[string]int) r["nip"] = PPC64LE_PC r["sp"] = PPC64LE_SP r["bp"] = PPC64LE_SP r["link"] = PPC64LE_LR for i := 0; i <= 31; i++ { r[fmt.Sprintf("r%d", i)] = PPC64LE_R0 + i } for i := 0; i <= 31; i++ { r[fmt.Sprintf("f%d", i)] = PPC64LE_F0 + i } for i := 0; i <= 31; i++ { r[fmt.Sprintf("v%d", i)] = PPC64LE_V0 + i } for i := 0; i <= 63; i++ { r[fmt.Sprintf("vs%d", i)] = PPC64LE_VS0 + i } for i := 0; i <= 7; i++ { r[fmt.Sprintf("cr%d", i)] = PPC64LE_CR0 + i } return r }()
Functions ¶
func AMD64MaxRegNum ¶
func AMD64MaxRegNum() uint64
func AMD64ToName ¶
func ARM64MaxRegNum ¶
func ARM64MaxRegNum() uint64
func ARM64ToName ¶
func I386MaxRegNum ¶
func I386MaxRegNum() int
func I386ToName ¶
func PPC64LEMaxRegNum ¶ added in v1.21.1
func PPC64LEMaxRegNum() uint64
PPC64LEMaxRegNum is 172 registers in total, across 4 categories: General Purpose Registers or GPR (32 GPR + 9 special registers) Floating Point Registers or FPR (32 FPR + 1 special register) Altivec/VMX Registers or VMX (32 VMX + 2 special registers) VSX Registers or VSX (64 VSX) Documentation: https://lldb.llvm.org/cpp_reference/RegisterContextPOSIX__ppc64le_8cpp_source.html
func PPC64LEToName ¶ added in v1.21.1
Types ¶
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