Documentation ¶
Overview ¶
CMSIS abstraction functions.
Original copyright:
Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Index ¶
- Constants
- Variables
- func Asm(asm string)
- func AsmFull(asm string, regs map[string]interface{})
- func EnableIRQ(irq uint32)
- func ReadRegister(name string) uintptr
- func SVCall0(num uintptr) uintptr
- func SVCall1(num uintptr, a1 interface{}) uintptr
- func SVCall2(num uintptr, a1, a2 interface{}) uintptr
- func SVCall3(num uintptr, a1, a2, a3 interface{}) uintptr
- func SVCall4(num uintptr, a1, a2, a3, a4 interface{}) uintptr
- func SemihostingCall(num int, arg uintptr) int
- func SetPriority(irq uint32, priority uint32)
- type NVIC_Type
- type RegValue
Constants ¶
const ( SCS_BASE = 0xE000E000 NVIC_BASE = SCS_BASE + 0x0100 )
const ( // Regular semihosting calls SemihostingClock = 0x10 SemihostingClose = 0x02 SemihostingElapsed = 0x30 SemihostingErrno = 0x13 SemihostingFileLen = 0x0C SemihostingGetCmdline = 0x15 SemihostingHeapInfo = 0x16 SemihostingIsError = 0x08 SemihostingIsTTY = 0x09 SemihostingOpen = 0x01 SemihostingRead = 0x06 SemihostingReadByte = 0x07 SemihostingRemove = 0x0E SemihostingRename = 0x0F SemihostingSeek = 0x0A SemihostingSystem = 0x12 SemihostingTickFreq = 0x31 SemihostingTime = 0x11 SemihostingTmpName = 0x0D SemihostingWrite = 0x05 SemihostingWrite0 = 0x04 SemihostingWriteByte = 0x03 // Angel semihosting calls SemihostingEnterSVC = 0x17 SemihostingReportException = 0x18 )
Semihosting commands. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html
const ( // Hardware vector reason codes SemihostingBranchThroughZero = 20000 SemihostingUndefinedInstr = 20001 SemihostingSoftwareInterrupt = 20002 SemihostingPrefetchAbort = 20003 SemihostingDataAbort = 20004 SemihostingAddressException = 20005 SemihostingIRQ = 20006 SemihostingFIQ = 20007 // Software reason codes SemihostingBreakPoint = 20020 SemihostingWatchPoint = 20021 SemihostingStepComplete = 20022 SemihostingRunTimeErrorUnknown = 20023 SemihostingInternalError = 20024 SemihostingUserInterruption = 20025 SemihostingApplicationExit = 20026 SemihostingStackOverflow = 20027 SemihostingDivisionByZero = 20028 SemihostingOSSpecific = 20029 )
Special codes for the Angel Semihosting interface.
Variables ¶
Functions ¶
func Asm ¶
func Asm(asm string)
Run the given assembly code. The code will be marked as having side effects, as it doesn't produce output and thus would normally be eliminated by the optimizer.
func AsmFull ¶
Run the given inline assembly. The code will be marked as having side effects, as it would otherwise be optimized away. The inline assembly string recognizes template values in the form {name}, like so:
arm.AsmFull( "str {value}, {result}", map[string]interface{}{ "value": 1 "result": &dest, })
func ReadRegister ¶
ReadRegister returns the contents of the specified register. The register must be a processor register, reachable with the "mov" instruction.
func SemihostingCall ¶
Call a semihosting function. TODO: implement it here using inline assembly.
func SetPriority ¶
Set the priority of the given interrupt number. Note that the priority is given as a 0-255 number, where some of the lower bits are not implemented by the hardware. For example, to set a low interrupt priority, use 0xc0, which is equivalent to using priority level 5 when the hardware has 8 priority levels. Also note that the priority level is inverted in ARM: a lower number means it is a more important interrupt and will interrupt ISRs with a higher interrupt priority.
Types ¶
type NVIC_Type ¶
type NVIC_Type struct { ISER [8]RegValue // Interrupt Set-enable Registers ICER [8]RegValue // Interrupt Clear-enable Registers ISPR [8]RegValue // Interrupt Set-pending Registers ICPR [8]RegValue // Interrupt Clear-pending Registers IABR [8]RegValue // Interrupt Active Bit Registers IPR [60]RegValue // Interrupt Priority Registers // contains filtered or unexported fields }
Nested Vectored Interrupt Controller (NVIC).
Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CIHIGCIF.html