lpspi

package
v0.0.7 Latest Latest
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 Go to latest Published: Mar 28, 2024 License: BSD-3-Clause Imports: 10 Imported by: 0

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Index

Constants

View Source 
const (
	FEATURE   uint32 = 0xFFFF << 0 //+ Module Identification Number
	FEATURE_4 uint32 = 0x04 << 0   //  Standard feature set supporting a 32-bit shift register.
	MINOR     uint32 = 0xFF << 16  //+ Minor Version Number
	MAJOR     uint32 = 0xFF << 24  //+ Major Version Number
)

VERID

View Source 
const (
	FEATUREn = 0
	MINORn   = 16
	MAJORn   = 24
)
View Source 
const (
	TXFIFO uint32 = 0xFF << 0  //+ Transmit FIFO Size
	RXFIFO uint32 = 0xFF << 8  //+ Receive FIFO Size
	PCSNUM uint32 = 0xFF << 16 //+ PCS Number
)

PARAM

View Source 
const (
	TXFIFOn = 0
	RXFIFOn = 8
	PCSNUMn = 16
)
View Source 
const (
	MENn   = 0
	RSTn   = 1
	DOZENn = 2
	DBGENn = 3
	RTFn   = 8
	RRFn   = 9
)
View Source 
const (
	TDFn = 0
	RDFn = 1
	WCFn = 8
	FCFn = 9
	TCFn = 10
	TEFn = 11
	REFn = 12
	DMFn = 13
	MBFn = 24
)
View Source 
const (
	TDIEn = 0
	RDIEn = 1
	WCIEn = 8
	FCIEn = 9
	TCIEn = 10
	TEIEn = 11
	REIEn = 12
	DMIEn = 13
)
View Source 
const (
	TDDEn = 0
	RDDEn = 1
)
View Source 
const (
	HRENn    = 0
	HRPOLn   = 1
	HRSELn   = 2
	CIRFIFOn = 8
	RDMOn    = 9
)
View Source 
const (
	MASTERn  = 0
	SAMPLEn  = 1
	AUTOPCSn = 2
	NOSTALLn = 3
	PCSPOLn  = 8
	MATCFGn  = 16
	PINCFGn  = 24
	OUTCFGn  = 26
	PCSCFGn  = 27
)
View Source 
const (
	SCKDIVn = 0
	DBTn    = 8
	PCSSCKn = 16
	SCKPCSn = 24
)
View Source 
const (
	TXWATERn = 0
	RXWATERn = 16
)
View Source 
const (
	TXCOUNTn = 0
	RXCOUNTn = 16
)
View Source 
const (
	FRAMESZn  = 0
	WIDTHn    = 16
	TXMSKn    = 18
	RXMSKn    = 19
	CONTCn    = 20
	CONTn     = 21
	BYSWn     = 22
	LSBFn     = 23
	PCSn      = 24
	PRESCALEn = 27
	CPHAn     = 30
	CPOLn     = 31
)
View Source 
const (
	SOFn     = 0
	RXEMPTYn = 1
)

Variables

This section is empty.

Functions

This section is empty.

Types

type CCR 

type CCR uint32
const (
	SCKDIV CCR = 0xFF << 0  //+ SCK Divider
	DBT    CCR = 0xFF << 8  //+ Delay Between Transfers
	PCSSCK CCR = 0xFF << 16 //+ PCS-to-SCK Delay
	SCKPCS CCR = 0xFF << 24 //+ SCK-to-PCS Delay
)

type CFGR0 

type CFGR0 uint32
const (
	HREN    CFGR0 = 0x01 << 0 //+ Host Request Enable
	HRPOL   CFGR0 = 0x01 << 1 //+ Host Request Polarity
	HRSEL   CFGR0 = 0x01 << 2 //+ Host Request Select
	CIRFIFO CFGR0 = 0x01 << 8 //+ Circular FIFO Enable
	RDMO    CFGR0 = 0x01 << 9 //+ Receive Data Match Only
)

type CFGR1 

type CFGR1 uint32
const (
	MASTER  CFGR1 = 0x01 << 0  //+ Master Mode
	SAMPLE  CFGR1 = 0x01 << 1  //+ Sample Point
	AUTOPCS CFGR1 = 0x01 << 2  //+ Automatic PCS
	NOSTALL CFGR1 = 0x01 << 3  //+ No Stall
	PCSPOL  CFGR1 = 0x0F << 8  //+ Peripheral Chip Select Polarity
	PCS0H   CFGR1 = 0x01 << 8  //  PCS0 pin is active high
	PCS1H   CFGR1 = 0x02 << 8  //  PCS1 pin is active high
	PCS2H   CFGR1 = 0x04 << 8  //  PCS2 pin is active high
	PCS3H   CFGR1 = 0x08 << 8  //  PCS3 pin is active high
	MATCFG  CFGR1 = 0x07 << 16 //+ Match Configuration
	MATDIS  CFGR1 = 0x00 << 16 //  Match is disabled
	MAT0    CFGR1 = 0x02 << 16 //  Match if data[0]==MATCH0 || data[0]==MATCH1
	MATX    CFGR1 = 0x03 << 16 //  Match if data[x]==MATCH0 || data[x]==MATCH1
	MAT02   CFGR1 = 0x04 << 16 //  Match if data[0:2] == {MATCH0, MATCH1}
	MATX2   CFGR1 = 0x05 << 16 //  Match if data[x:x+2] == {MATCH0, MATCH1}
	MAT0M   CFGR1 = 0x06 << 16 //  Match if data[0]&MATCH1 == MATCH0&MATCH1
	MATXM   CFGR1 = 0x07 << 16 //  Match if data[x]&MATCH1 == MATCH0&MATCH1
	PINCFG  CFGR1 = 0x03 << 24 //+ Pin Configuration
	FD      CFGR1 = 0x00 << 24 //  SIN=Rx, SOUT=Tx in full-duplex mode
	HDSIN   CFGR1 = 0x01 << 24 //  1-bit half-duplex on SIN
	HDSOUT  CFGR1 = 0x02 << 24 //  1-bit half-duplex on SOUT
	FDSWAP  CFGR1 = 0x03 << 24 //  SIN=Tx, SOUT=Rx in full-duplex mode
	OUTCFG  CFGR1 = 0x01 << 26 //+ Output Config
	PCSDATA CFGR1 = 0x01 << 27 //+ Use PCS[3:2] as DATA[3:2] for 4-bit half-duplex mode
)

type CR 

type CR uint32
const (
	MEN   CR = 0x01 << 0 //+ Module Enable
	RST   CR = 0x01 << 1 //+ Software Reset
	DOZEN CR = 0x01 << 2 //+ Doze mode enable
	DBGEN CR = 0x01 << 3 //+ Debug Enable
	RTF   CR = 0x01 << 8 //+ Reset Transmit FIFO
	RRF   CR = 0x01 << 9 //+ Reset Receive FIFO
)

type DER 

type DER uint32
const (
	TDDE DER = 0x01 << 0 //+ Transmit Data DMA Enable
	RDDE DER = 0x01 << 1 //+ Receive Data DMA Enable
)

type FCR 

type FCR uint32
const (
	TXWATER FCR = 0x0F << 0  //+ Transmit FIFO Watermark
	RXWATER FCR = 0x0F << 16 //+ Receive FIFO Watermark
)

type FSR 

type FSR uint32
const (
	TXCOUNT FSR = 0x1F << 0  //+ Transmit FIFO Count
	RXCOUNT FSR = 0x1F << 16 //+ Receive FIFO Count
)

type IER 

type IER uint32
const (
	TDIE IER = 0x01 << 0  //+ Transmit Data Interrupt Enable
	RDIE IER = 0x01 << 1  //+ Receive Data Interrupt Enable
	WCIE IER = 0x01 << 8  //+ Word Complete Interrupt Enable
	FCIE IER = 0x01 << 9  //+ Frame Complete Interrupt Enable
	TCIE IER = 0x01 << 10 //+ Transfer Complete Interrupt Enable
	TEIE IER = 0x01 << 11 //+ Transmit Error Interrupt Enable
	REIE IER = 0x01 << 12 //+ Receive Error Interrupt Enable
	DMIE IER = 0x01 << 13 //+ Data Match Interrupt Enable
)

type Master 

type Master struct {
	// contains filtered or unexported fields
}

Master is a driver to the LPSPI peripheral used in master mode.

func NewMaster 

func NewMaster(p *Periph, rxdma, txdma dma.Channel) *Master

NewMaster returns a new master-mode driver for p. If valid DMA channels are given, the DMA will be used for bigger data transfers.

func (*Master) BaseFreqHz 

func (d *Master) BaseFreqHz() int

func (*Master) Disable 

func (d *Master) Disable()

Disable disables LPSPI peripheral.

func (*Master) Enable 

func (d *Master) Enable()

Enable enables LPSPI peripheral.

func (*Master) Periph 

func (d *Master) Periph() *Periph

Periph returns the underlying LPSPI peripheral.

func (*Master) Read 

func (d *Master) Read(p []byte) (int, error)

Read implements io.Reader interface. It works like Read32 but for 16-bit words instead of bytes.

BUG: Typical usage scenarios of this function require 8-bit frame size with the TXMSK and CONT bits set but there is a hardware bug that makes this configuration unusable (see WriteCmd for more information).

func (*Master) Read16 

func (d *Master) Read16(p []uint16)

Read16 works like Read32 but for 16-bit words instead of bytes.

BUG: Typical usage scenarios of this function require 16-bit frame size with the TXMSK and CONT bits set but there is a hardware bug that makes this configuration unusable (see WriteCmd for more information).

func (*Master) Read32 

func (d *Master) Read32(p []uint32)

Read32 is designed for the unidirectional mode of operation, e.g. the TXMSK bit and the proper frame size were set by the last command. It may also be used for bidirectional transfers provided there are at least len(p) words available in the recevie FIFO (not recommended, use WriteRead32 instead).

BUG: There are known hardware bugs related to Rx-only mode (see WriteCmd for more information). In contrast to Read and Read16 this function can be used with TXMSK set provided the frame size is set to 8*len(p) and the CONT bit is cleared.

func (*Master) ReadWord 

func (d *Master) ReadWord() uint32

ReadWord reads a 32-bit data word from the receive FIFO, waiting for data if not available.

func (*Master) RxDMAISR 

func (d *Master) RxDMAISR()

RxDMAISR is required in DMA mode if Read* or WriteRead* methods are used.

func (*Master) Setup 

func (d *Master) Setup(baseFreqHz int)

Setup enables the SPI clock, resets the peripheral and sets the base SCK clock frequency to baseFreqHz rounded down to 133/n MHz, where n is an integer number from 2 to 257. The LPSPI controller is configured as master (CFGR1=MASTER). Other configuration registers have their default values. For custom configuration use the Periph method to access all configuration registers. Different slave devices on the bust may require different SPI mode (CPOL, CPHA) and clock speed therefore, these types of settings are configured per transaction (see WriteCmd). The resulting SPI clock frequency should not exceed 30 MHz. (33 MHz seems to work as well and there are reports that even 2x overclocking is achievable).

func (*Master) TxDMAISR 

func (d *Master) TxDMAISR()

TxDMAISR is required in DMA mode if Write* (excluding WriteRead*) methods are used.

func (*Master) UsePin 

func (d *Master) UsePin(pin iomux.Pin, sig Signal) bool

UsePin is a helper function that can be used to configure IO pins as required by LPUART peripheral. Only certain pins can be used (see datasheet). UsePin returns true on succes or false if it isn't possible to use a pin as a sig. See also Periph.Pins.

func (*Master) Write 

func (d *Master) Write(p []byte) (int, error)

Write implements io.Writer interface. It works like Write32 but for 8-bit words.

func (*Master) Write16 

func (d *Master) Write16(p []uint16)

Write16 works like Write32 but for 16-bit words.

func (*Master) Write32 

func (d *Master) Write32(p []uint32)

Write32 is designed for unidirectional mode of operation, e.g. the TCR.RXMSK bit was set by the last command. It may also be used for bidirectional transfers, provided len(p) is less than the free space in the receive FIFO (not recommended, use WriteRead32 instead). always returns len(p), nil.

func (*Master) WriteCmd 

func (d *Master) WriteCmd(cmd TCR, frameSize int)

WriteCmd writes a command to the transmit FIFO. The command allows you to select a slave device by asserting PCSx pin. It also alows you to select clock prescaler, polarity, phase and other things in different way for every transaction. You can encode the frame size in cmd directly using the FRAMESZ field or specify it using the frameSize parameter (FRAMESZ = frameSize-1). The frame size is specified as a numer of bits. The minimum supported frame size is 8 bits and maximum is 4096 bits. If frameSize <= 32 it also specifies the word size. If frameSize > 32 then the word size is 32 except the last one which is equal to frameSize % 32 and must be >= 2 (e.g. frameSize = 33 is not supported).

LPSPI BUGS

The LPSPI peripheral has two bugs not mentioned in the errata that reveal in the master mode when the TCR.CONT bit is set:

1. In bidirectional mode, when you write n words to TDR, you can read only n-1 words from RDR. The last word can be read after CONT is cleared or the peripheral is disabled in the CR register. It seems the received word is stored somewhere before it enters the receive FIFO so the writes to TDR and reads from RDR are out of sync for one word.

2. In Rx-only mode, LPSPI starts reading data just after the command with the CONT and TXMSK bits is written to TCR. If you do not read from RDR then 17 words are read from BUS (16 into FIFO and 1 elsewhere) and the REF error flag is set. If you next will read 1 word from the FIFO the LPSPI will read next 2 words from the BUS (one of them is lost).

func (*Master) WriteRead 

func (d *Master) WriteRead(out, in []byte) (n int)

WriteRead writes n = min(len(out), len(in)) bytes to the transmit FIFO, zero-extending any byte to the full 32-bit FIFO word. At the same time it reads the same number of bytes from the receive FIFO, using only the low significant bytes from the available 32-bit FIFO words.

func (*Master) WriteRead16 

func (d *Master) WriteRead16(out, in []uint16) (n int)

WriteRead16 works like WriteRead but with 16-bit words instead of bytes.

func (*Master) WriteRead32 

func (d *Master) WriteRead32(out, in []uint32) (n int)

WriteRead32 works like WriteRead but with 32-bit words instead of bytes.

func (*Master) WriteString 

func (d *Master) WriteString(s string) (int, error)

WriteString implemets io.StringWriter interface. See Write for more information.

func (*Master) WriteStringRead 

func (d *Master) WriteStringRead(out string, in []byte) int

WriteStringRead works like WriteRead but the output bytes are taken from the string.

func (*Master) WriteWord 

func (d *Master) WriteWord(word uint32)

WriteWord writes a 32-bit data word to the transmit FIFO, waiting for a free FIFO slot if not available.

type Periph 

type Periph struct {
	VERID mmio.R32[uint32]
	PARAM mmio.R32[uint32]

	CR    mmio.R32[CR]
	SR    mmio.R32[SR]
	IER   mmio.R32[IER]
	DER   mmio.R32[DER]
	CFGR0 mmio.R32[CFGR0]
	CFGR1 mmio.R32[CFGR1]

	DMR0 mmio.R32[uint32]
	DMR1 mmio.R32[uint32]

	CCR mmio.R32[CCR]

	FCR mmio.R32[FCR]
	FSR mmio.R32[FSR]
	TCR mmio.R32[TCR]
	TDR mmio.R32[uint32]

	RSR mmio.R32[RSR]
	RDR mmio.R32[uint32]
	// contains filtered or unexported fields
}

func LPSPI 

func LPSPI(n int) *Periph

func (*Periph) DisableClock 

func (p *Periph) DisableClock()

DisableClock disables the clock for the LPSPI peripheral.

func (*Periph) EnableClock 

func (p *Periph) EnableClock(lp bool)

EnableClock enables the clock for the LPSPI peripheral. lp determines whether the clock remains on in low power WAIT mode.

func (*Periph) Pins 

func (p *Periph) Pins(sig Signal) []iomux.Pin

Pins return IO pins that can be used for singal sig.

func (*Periph) Reset 

func (p *Periph) Reset()

type RSR 

type RSR uint32
const (
	SOF     RSR = 0x01 << 0 //+ Start Of Frame
	RXEMPTY RSR = 0x01 << 1 //+ RX FIFO Empty
)

type SR 

type SR uint32
const (
	TDF SR = 0x01 << 0  //+ Transmit Data Flag
	RDF SR = 0x01 << 1  //+ Receive Data Flag
	WCF SR = 0x01 << 8  //+ Word Complete Flag
	FCF SR = 0x01 << 9  //+ Frame Complete Flag
	TCF SR = 0x01 << 10 //+ Transfer Complete Flag
	TEF SR = 0x01 << 11 //+ Transmit Error Flag
	REF SR = 0x01 << 12 //+ Receive Error Flag
	DMF SR = 0x01 << 13 //+ Data Match Flag
	MBF SR = 0x01 << 24 //+ Module Busy Flag
)

type Signal 

type Signal int8
const (
	PCS0 Signal = iota // chip select 0
	PCS1               // chip select 1 / host request
	PCS2               // chip select 2 / data 2
	PCS3               // chip select 3 / data 3
	SCK                // clock
	SDI                // MISO / MOSI / data 1
	SDO                // MOSI / MISO / data 0
)

type TCR 

type TCR uint32
const (
	FRAMESZ   TCR = 0xFFF << 0 //+ Frame Size
	WIDTH     TCR = 0x03 << 16 //+ Transfer Width
	WIDTH0    TCR = 0x00 << 16 //  1 bit transfer
	WIDTH1    TCR = 0x01 << 16 //  2 bit transfer
	WIDTH2    TCR = 0x02 << 16 //  4 bit transfer
	TXMSK     TCR = 0x01 << 18 //+ Transmit Data Mask
	RXMSK     TCR = 0x01 << 19 //+ Receive Data Mask
	CONTC     TCR = 0x01 << 20 //+ Continuing Command
	CONT      TCR = 0x01 << 21 //+ Continuous Transfer
	BYSW      TCR = 0x01 << 22 //+ Byte Swap
	LSBF      TCR = 0x01 << 23 //+ LSB First
	TPCS      TCR = 0x03 << 24 //+ Peripheral Chip Select
	TPCS0     TCR = 0x00 << 24 //  Transfer using LPSPI_PCS[0]
	TPCS1     TCR = 0x01 << 24 //  Transfer using LPSPI_PCS[1]
	TPCS2     TCR = 0x02 << 24 //  Transfer using LPSPI_PCS[2]
	TPCS3     TCR = 0x03 << 24 //  Transfer using LPSPI_PCS[3]
	PRESCALE  TCR = 0x07 << 27 //+ Prescaler Value
	PREDIV1   TCR = 0x00 << 27 //  Divide by 1
	PREDIV2   TCR = 0x01 << 27 //  Divide by 2
	PREDIV4   TCR = 0x02 << 27 //  Divide by 4
	PREDIV8   TCR = 0x03 << 27 //  Divide by 8
	PREDIV16  TCR = 0x04 << 27 //  Divide by 16
	PREDIV32  TCR = 0x05 << 27 //  Divide by 32
	PREDIV64  TCR = 0x06 << 27 //  Divide by 64
	PREDIV128 TCR = 0x07 << 27 //  Divide by 128
	CPHA      TCR = 0x01 << 30 //+ Clock Phase
	CPHA0     TCR = 0x00 << 30 //  Capture data on the leading and change on the following edge of SCK
	CPHA1     TCR = 0x01 << 30 //  Change data on the leading and capture on the following edge of SCK
	CPOL      TCR = 0x01 << 31 //+ Clock Polarity
	CPOL0     TCR = 0x00 << 31 //  The inactive state value of SCK is low
	CPOL1     TCR = 0x01 << 31 //  The inactive state value of SCK is high
)

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