procbuilder

package
v0.0.0-...-3be6dbe Latest Latest
Warning

This package is not in the latest version of its module.

 Go to latest Published: Oct 11, 2023 License: Apache-2.0 Imports: 24 Imported by: 0

Documentation

Index

Constants

View Source 
const (
	OP_CALLO = uint8(0) + iota
	OP_CALLA
	OP_RET
)
View Source 
const (
	FPADD = uint8(0) + iota
	FPMULT
	FPDIV
)
View Source 
const (
	LQADD = uint8(0) + iota
	LQMULT
	LQDIV
)
View Source 
const (
	OP_PUSH = uint8(0) + iota
	OP_PULL
)
View Source 
const (
	FPPUT = uint8(0) + iota
	FPGET
)
View Source 
const (
	LQPUT = uint8(0) + iota
	LQCORR
	LQGET
)
View Source 
const (
	OnlyDestRegs = uint64(1)
	OnlySrcRegs  = uint64(2)
)
View Source 
const (
	C_OPCODE = uint8(0) + iota
	C_REGSIZE
	C_INPUT
	C_OUTPUT
	C_ROMSIZE
	C_RAMSIZE
	C_SHAREDOBJECT
	C_CONNECTED
)
View Source 
const (
	O_REGISTER = uint8(0) + iota
	O_INPUT
	O_OUTPUT
	O_CHANNEL
)
View Source 
const (
	I_NIL = 0
)
View Source 
const (
	S_NIL = ""
)

Variables

View Source 
var AllDynamicalInstructions []DynamicInstruction
View Source 
var Allopcodes []Opcode
View Source 
var Allshared []Sharedel

Functions

func EventuallyCreateInstruction 

func EventuallyCreateInstruction(name string) (bool, error)

func ExecutionCase 

func ExecutionCase(conf *Config, arch *Arch, tabs int, open bool) string

func Get_channel_name 

func Get_channel_name(i int) string

func Get_input_name 

func Get_input_name(i int) string

func Get_output_name 

func Get_output_name(i int) string

func Get_register_name 

func Get_register_name(i int) string

func Int16FromBits 

func Int16FromBits(f uint16) int16

func Int16bits 

func Int16bits(f int16) uint16

func Int32FromBits 

func Int32FromBits(f uint32) int32

func Int32bits 

func Int32bits(f int32) uint32

func Int64FromBits 

func Int64FromBits(f uint64) int64

func Int64bits 

func Int64bits(f int64) uint64

func Int8FromBits 

func Int8FromBits(f uint8) int8

func Int8bits 

func Int8bits(f int8) uint8

func IsHwOptimizationSet 

func IsHwOptimizationSet(current HwOptimizations, optimization HwOptimizations) bool

func Machine_Program_Crossover 

func Machine_Program_Crossover(p mel.Me3li, q mel.Me3li, ep *mel.EvolutionParameters) mel.Me3li

func Machine_Program_Generate 

func Machine_Program_Generate(ep *mel.EvolutionParameters) mel.Me3li

func Machine_Program_Mutate 

func Machine_Program_Mutate(p mel.Me3li, ep *mel.EvolutionParameters) mel.Me3li

func Needed_bits 

func Needed_bits(num int) int

func NextInstruction 

func NextInstruction(conf *Config, arch *Arch, tabs int, jumpTo string) string

func Process_input 

func Process_input(iregname string, input_num int) (string, error)

func Process_number 

func Process_number(input string) (string, error)

func Process_output 

func Process_output(iregname string, input_num int) (string, error)

func Process_shared 

func Process_shared(soshort string, soname string, num int) (string, error)

func RandStringBytes 

func RandStringBytes(n int) string

func Sequence_to_0 

func Sequence_to_0(start string) ([]string, uint8)

Types

type Adc 

type Adc struct{}

The Adc opcode is both a basic instruction and a template for other instructions.

func (Adc) AbstractAssembler 

func (Op Adc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Adc) Assembler 

func (op Adc) Assembler(arch *Arch, words []string) (string, error)

func (Adc) Disassembler 

func (op Adc) Disassembler(arch *Arch, instr string) (string, error)

func (Adc) ExtraFiles 

func (Op Adc) ExtraFiles(arch *Arch) ([]string, []string)

func (Adc) Forbidden_modes 

func (op Adc) Forbidden_modes() (bool, []string)

func (Adc) Generate 

func (op Adc) Generate(arch *Arch) string

The random genaration does nothing

func (Adc) HLAssemblerInstructionMetadata 

func (Op Adc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Adc) HLAssemblerMatch 

func (Op Adc) HLAssemblerMatch(arch *Arch) []string

func (Adc) HLAssemblerNormalize 

func (Op Adc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Adc) OpInstructionVerilogHeader 

func (op Adc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Adc) Op_get_desc 

func (op Adc) Op_get_desc() string

func (Adc) Op_get_instruction_len 

func (op Adc) Op_get_instruction_len(arch *Arch) int

func (Adc) Op_get_name 

func (op Adc) Op_get_name() string

func (Adc) Op_instruction_internal_state 

func (op Adc) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Adc) Op_instruction_verilog_default_state 

func (Op Adc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Adc) Op_instruction_verilog_extra_block 

func (Op Adc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Adc) Op_instruction_verilog_extra_modules 

func (Op Adc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Adc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Adc) Op_instruction_verilog_internal_state 

func (Op Adc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Adc) Op_instruction_verilog_reset 

func (Op Adc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Adc) Op_instruction_verilog_state_machine 

func (op Adc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Adc) Op_show_assembler 

func (op Adc) Op_show_assembler(arch *Arch) string

func (Adc) Required_modes 

func (op Adc) Required_modes() (bool, []string)

func (Adc) Required_shared 

func (op Adc) Required_shared() (bool, []string)

func (Adc) Simulate 

func (op Adc) Simulate(vm *VM, instr string) error

The simulation does nothing

type Add 

type Add struct{}

The Add opcode is both a basic instruction and a template for other instructions.

func (Add) AbstractAssembler 

func (Op Add) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Add) Assembler 

func (op Add) Assembler(arch *Arch, words []string) (string, error)

func (Add) Disassembler 

func (op Add) Disassembler(arch *Arch, instr string) (string, error)

func (Add) ExtraFiles 

func (Op Add) ExtraFiles(arch *Arch) ([]string, []string)

func (Add) Forbidden_modes 

func (op Add) Forbidden_modes() (bool, []string)

func (Add) Generate 

func (op Add) Generate(arch *Arch) string

The random generation does nothing

func (Add) HLAssemblerInstructionMetadata 

func (Op Add) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Add) HLAssemblerMatch 

func (Op Add) HLAssemblerMatch(arch *Arch) []string

func (Add) HLAssemblerNormalize 

func (Op Add) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Add) OpInstructionVerilogHeader 

func (op Add) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Add) Op_get_desc 

func (op Add) Op_get_desc() string

func (Add) Op_get_instruction_len 

func (op Add) Op_get_instruction_len(arch *Arch) int

func (Add) Op_get_name 

func (op Add) Op_get_name() string

func (Add) Op_instruction_internal_state 

func (op Add) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Add) Op_instruction_verilog_default_state 

func (Op Add) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Add) Op_instruction_verilog_extra_block 

func (Op Add) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Add) Op_instruction_verilog_extra_modules 

func (Op Add) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Add) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Add) Op_instruction_verilog_internal_state 

func (Op Add) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Add) Op_instruction_verilog_reset 

func (Op Add) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Add) Op_instruction_verilog_state_machine 

func (op Add) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Add) Op_show_assembler 

func (op Add) Op_show_assembler(arch *Arch) string

func (Add) Required_modes 

func (op Add) Required_modes() (bool, []string)

func (Add) Required_shared 

func (op Add) Required_shared() (bool, []string)

func (Add) Simulate 

func (op Add) Simulate(vm *VM, instr string) error

Add simulates the execution of the Add instruction

type Addf 

type Addf struct{}

The Addf opcode is both a basic instruction and a template for other instructions.

func (Addf) AbstractAssembler 

func (Op Addf) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Addf) Assembler 

func (op Addf) Assembler(arch *Arch, words []string) (string, error)

func (Addf) Disassembler 

func (op Addf) Disassembler(arch *Arch, instr string) (string, error)

func (Addf) ExtraFiles 

func (Op Addf) ExtraFiles(arch *Arch) ([]string, []string)

func (Addf) Forbidden_modes 

func (op Addf) Forbidden_modes() (bool, []string)

func (Addf) Generate 

func (op Addf) Generate(arch *Arch) string

The random genaration does nothing

func (Addf) HLAssemblerInstructionMetadata 

func (Op Addf) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Addf) HLAssemblerMatch 

func (Op Addf) HLAssemblerMatch(arch *Arch) []string

func (Addf) HLAssemblerNormalize 

func (Op Addf) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Addf) OpInstructionVerilogHeader 

func (op Addf) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Addf) Op_get_desc 

func (op Addf) Op_get_desc() string

func (Addf) Op_get_instruction_len 

func (op Addf) Op_get_instruction_len(arch *Arch) int

func (Addf) Op_get_name 

func (op Addf) Op_get_name() string

func (Addf) Op_instruction_internal_state 

func (op Addf) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Addf) Op_instruction_verilog_default_state 

func (Op Addf) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Addf) Op_instruction_verilog_extra_block 

func (Op Addf) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Addf) Op_instruction_verilog_extra_modules 

func (Op Addf) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Addf) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Addf) Op_instruction_verilog_internal_state 

func (Op Addf) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Addf) Op_instruction_verilog_reset 

func (Op Addf) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Addf) Op_instruction_verilog_state_machine 

func (op Addf) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Addf) Op_show_assembler 

func (op Addf) Op_show_assembler(arch *Arch) string

func (Addf) Required_modes 

func (op Addf) Required_modes() (bool, []string)

func (Addf) Required_shared 

func (op Addf) Required_shared() (bool, []string)

func (Addf) Simulate 

func (op Addf) Simulate(vm *VM, instr string) error

type Addf16 

type Addf16 struct{}

The Addf16 opcode is both a basic instruction and a template for other instructions.

func (Addf16) AbstractAssembler 

func (Op Addf16) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Addf16) Assembler 

func (op Addf16) Assembler(arch *Arch, words []string) (string, error)

func (Addf16) Disassembler 

func (op Addf16) Disassembler(arch *Arch, instr string) (string, error)

func (Addf16) ExtraFiles 

func (Op Addf16) ExtraFiles(arch *Arch) ([]string, []string)

func (Addf16) Forbidden_modes 

func (op Addf16) Forbidden_modes() (bool, []string)

func (Addf16) Generate 

func (op Addf16) Generate(arch *Arch) string

The random genaration does nothing

func (Addf16) HLAssemblerInstructionMetadata 

func (Op Addf16) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Addf16) HLAssemblerMatch 

func (Op Addf16) HLAssemblerMatch(arch *Arch) []string

func (Addf16) HLAssemblerNormalize 

func (Op Addf16) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Addf16) OpInstructionVerilogHeader 

func (op Addf16) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Addf16) Op_get_desc 

func (op Addf16) Op_get_desc() string

func (Addf16) Op_get_instruction_len 

func (op Addf16) Op_get_instruction_len(arch *Arch) int

func (Addf16) Op_get_name 

func (op Addf16) Op_get_name() string

func (Addf16) Op_instruction_internal_state 

func (op Addf16) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Addf16) Op_instruction_verilog_default_state 

func (Op Addf16) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Addf16) Op_instruction_verilog_extra_block 

func (Op Addf16) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Addf16) Op_instruction_verilog_extra_modules 

func (Op Addf16) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Addf16) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Addf16) Op_instruction_verilog_internal_state 

func (Op Addf16) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Addf16) Op_instruction_verilog_reset 

func (Op Addf16) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Addf16) Op_instruction_verilog_state_machine 

func (op Addf16) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Addf16) Op_show_assembler 

func (op Addf16) Op_show_assembler(arch *Arch) string

func (Addf16) Required_modes 

func (op Addf16) Required_modes() (bool, []string)

func (Addf16) Required_shared 

func (op Addf16) Required_shared() (bool, []string)

func (Addf16) Simulate 

func (op Addf16) Simulate(vm *VM, instr string) error

type Addi 

type Addi struct{}

func (Addi) AbstractAssembler 

func (Op Addi) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Addi) Assembler 

func (op Addi) Assembler(arch *Arch, words []string) (string, error)

func (Addi) Disassembler 

func (op Addi) Disassembler(arch *Arch, instr string) (string, error)

func (Addi) ExtraFiles 

func (Op Addi) ExtraFiles(arch *Arch) ([]string, []string)

func (Addi) Forbidden_modes 

func (op Addi) Forbidden_modes() (bool, []string)

func (Addi) Generate 

func (op Addi) Generate(arch *Arch) string

func (Addi) HLAssemblerInstructionMetadata 

func (Op Addi) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Addi) HLAssemblerMatch 

func (Op Addi) HLAssemblerMatch(arch *Arch) []string

func (Addi) HLAssemblerNormalize 

func (Op Addi) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Addi) OpInstructionVerilogHeader 

func (op Addi) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Addi) Op_get_desc 

func (op Addi) Op_get_desc() string

func (Addi) Op_get_instruction_len 

func (op Addi) Op_get_instruction_len(arch *Arch) int

func (Addi) Op_get_name 

func (op Addi) Op_get_name() string

func (Addi) Op_instruction_verilog_default_state 

func (Op Addi) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Addi) Op_instruction_verilog_extra_block 

func (Op Addi) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Addi) Op_instruction_verilog_extra_modules 

func (Op Addi) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Addi) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Addi) Op_instruction_verilog_internal_state 

func (Op Addi) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Addi) Op_instruction_verilog_reset 

func (Op Addi) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Addi) Op_instruction_verilog_state_machine 

func (op Addi) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Addi) Op_show_assembler 

func (op Addi) Op_show_assembler(arch *Arch) string

func (Addi) Required_modes 

func (op Addi) Required_modes() (bool, []string)

func (Addi) Required_shared 

func (op Addi) Required_shared() (bool, []string)

func (Addi) Simulate 

func (op Addi) Simulate(vm *VM, instr string) error

type Addp 

type Addp struct {
	// contains filtered or unexported fields
}

func (Addp) AbstractAssembler 

func (Op Addp) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Addp) Assembler 

func (op Addp) Assembler(arch *Arch, words []string) (string, error)

func (Addp) Disassembler 

func (op Addp) Disassembler(arch *Arch, instr string) (string, error)

func (Addp) ExtraFiles 

func (Op Addp) ExtraFiles(arch *Arch) ([]string, []string)

func (Addp) Forbidden_modes 

func (op Addp) Forbidden_modes() (bool, []string)

func (Addp) Generate 

func (op Addp) Generate(arch *Arch) string

The random generation does nothing

func (Addp) HLAssemblerInstructionMetadata 

func (Op Addp) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Addp) HLAssemblerMatch 

func (Op Addp) HLAssemblerMatch(arch *Arch) []string

func (Addp) HLAssemblerNormalize 

func (Op Addp) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Addp) OpInstructionVerilogHeader 

func (op Addp) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Addp) Op_get_desc 

func (op Addp) Op_get_desc() string

func (Addp) Op_get_instruction_len 

func (op Addp) Op_get_instruction_len(arch *Arch) int

func (Addp) Op_get_name 

func (op Addp) Op_get_name() string

func (Addp) Op_instruction_internal_state 

func (op Addp) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Addp) Op_instruction_verilog_default_state 

func (Op Addp) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Addp) Op_instruction_verilog_extra_block 

func (Op Addp) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Addp) Op_instruction_verilog_extra_modules 

func (Op Addp) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Addp) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Addp) Op_instruction_verilog_internal_state 

func (Op Addp) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Addp) Op_instruction_verilog_reset 

func (Op Addp) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Addp) Op_instruction_verilog_state_machine 

func (op Addp) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Addp) Op_show_assembler 

func (op Addp) Op_show_assembler(arch *Arch) string

func (Addp) Required_modes 

func (op Addp) Required_modes() (bool, []string)

func (Addp) Required_shared 

func (op Addp) Required_shared() (bool, []string)

func (Addp) Simulate 

func (op Addp) Simulate(vm *VM, instr string) error

type And 

type And struct{}

The And opcode is both a basic instruction and a template for other instructions.

func (And) AbstractAssembler 

func (Op And) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (And) Assembler 

func (op And) Assembler(arch *Arch, words []string) (string, error)

func (And) Disassembler 

func (op And) Disassembler(arch *Arch, instr string) (string, error)

func (And) ExtraFiles 

func (Op And) ExtraFiles(arch *Arch) ([]string, []string)

func (And) Forbidden_modes 

func (op And) Forbidden_modes() (bool, []string)

func (And) Generate 

func (op And) Generate(arch *Arch) string

The random genaration does nothing

func (And) HLAssemblerInstructionMetadata 

func (Op And) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (And) HLAssemblerMatch 

func (Op And) HLAssemblerMatch(arch *Arch) []string

func (And) HLAssemblerNormalize 

func (Op And) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (And) OpInstructionVerilogHeader 

func (op And) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (And) Op_get_desc 

func (op And) Op_get_desc() string

func (And) Op_get_instruction_len 

func (op And) Op_get_instruction_len(arch *Arch) int

func (And) Op_get_name 

func (op And) Op_get_name() string

func (And) Op_instruction_internal_state 

func (op And) Op_instruction_internal_state(arch *Arch, flavor string) string

func (And) Op_instruction_verilog_default_state 

func (Op And) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (And) Op_instruction_verilog_extra_block 

func (Op And) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (And) Op_instruction_verilog_extra_modules 

func (Op And) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op And) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (And) Op_instruction_verilog_internal_state 

func (Op And) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (And) Op_instruction_verilog_reset 

func (Op And) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (And) Op_instruction_verilog_state_machine 

func (op And) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (And) Op_show_assembler 

func (op And) Op_show_assembler(arch *Arch) string

func (And) Required_modes 

func (op And) Required_modes() (bool, []string)

func (And) Required_shared 

func (op And) Required_shared() (bool, []string)

func (And) Simulate 

func (op And) Simulate(vm *VM, instr string) error

The simulation does nothing

type Arch 

type Arch struct {
	Modes []string
	Conproc
	Rom
	Ram
	Shared_constraints string
	Tag                string
	WordSize           uint8 // 0 means automatic computed, otherwise it is the size in bits of the word
}

The architecture

func (*Arch) Assembler 

func (arch *Arch) Assembler(inp []byte) (Program, error)

func (*Arch) Assembler_process_line 

func (arch *Arch) Assembler_process_line(line []byte) (string, error)

func (*Arch) HasAny 

func (arch *Arch) HasAny(ops []string) bool

func (*Arch) HasOp 

func (arch *Arch) HasOp(curOp string) bool

func (*Arch) Max_word 

func (arch *Arch) Max_word() int

func (*Arch) OnlyOne 

func (arch *Arch) OnlyOne(curOp string, ops []string) bool

func (*Arch) Program_generate 

func (arch *Arch) Program_generate() Program

func (*Arch) Shared_bits 

func (arch *Arch) Shared_bits(soname string) int

func (*Arch) Shared_depth 

func (arch *Arch) Shared_depth(soname string, so_id int) int

func (*Arch) Shared_num 

func (arch *Arch) Shared_num(soname string) int

func (*Arch) Show_assembler 

func (arch *Arch) Show_assembler() string

func (*Arch) String 

func (arch *Arch) String() string

func (*Arch) Write_verilog 

func (arch *Arch) Write_verilog(arch_module_name string, modules_names map[string]string, flavor string) string

func (*Arch) Write_verilog_main 

func (arch *Arch) Write_verilog_main(processor_module_name string, rom_module_name string, processor_name string, rom_name string, flavor string) string

func (*Arch) Write_verilog_testbench 

func (arch *Arch) Write_verilog_testbench(arch_module_name string, processor_name string, rom_name string, flavor string) string

type Barrier 

type Barrier struct{}

func (Barrier) GetArchHeader 

func (op Barrier) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Barrier) GetArchParams 

func (op Barrier) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Barrier) GetCPParams 

func (op Barrier) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Barrier) Shortname 

func (op Barrier) Shortname() string

func (Barrier) Shr_get_name 

func (op Barrier) Shr_get_name() string

type ByName 

type ByName []Opcode

func (ByName) Len 

func (op ByName) Len() int

func (ByName) Less 

func (op ByName) Less(i, j int) bool

func (ByName) Swap 

func (op ByName) Swap(i, j int)

type Call 

type Call struct {
	// contains filtered or unexported fields
}

func (Call) AbstractAssembler 

func (op Call) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Call) Assembler 

func (op Call) Assembler(arch *Arch, words []string) (string, error)

func (Call) Disassembler 

func (op Call) Disassembler(arch *Arch, instr string) (string, error)

func (Call) ExtraFiles 

func (op Call) ExtraFiles(arch *Arch) ([]string, []string)

func (Call) Forbidden_modes 

func (op Call) Forbidden_modes() (bool, []string)

func (Call) Generate 

func (op Call) Generate(arch *Arch) string

func (Call) HLAssemblerInstructionMetadata 

func (op Call) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Call) HLAssemblerMatch 

func (op Call) HLAssemblerMatch(arch *Arch) []string

func (Call) HLAssemblerNormalize 

func (op Call) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Call) OpInstructionVerilogHeader 

func (op Call) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Call) Op_get_desc 

func (op Call) Op_get_desc() string

func (Call) Op_get_instruction_len 

func (op Call) Op_get_instruction_len(arch *Arch) int

func (Call) Op_get_name 

func (op Call) Op_get_name() string

func (Call) Op_instruction_verilog_default_state 

func (op Call) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Call) Op_instruction_verilog_extra_block 

func (op Call) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Call) Op_instruction_verilog_extra_modules 

func (op Call) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Call) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Call) Op_instruction_verilog_internal_state 

func (op Call) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Call) Op_instruction_verilog_reset 

func (op Call) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Call) Op_instruction_verilog_state_machine 

func (op Call) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Call) Op_show_assembler 

func (op Call) Op_show_assembler(arch *Arch) string

func (Call) Required_modes 

func (op Call) Required_modes() (bool, []string)

func (Call) Required_shared 

func (op Call) Required_shared() (bool, []string)

func (Call) Simulate 

func (op Call) Simulate(vm *VM, instr string) error

type Channel 

type Channel struct{}

func (Channel) GetArchHeader 

func (op Channel) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Channel) GetArchParams 

func (op Channel) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Channel) GetCPParams 

func (op Channel) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Channel) Shortname 

func (op Channel) Shortname() string

func (Channel) Shr_get_name 

func (op Channel) Shr_get_name() string

type Chc 

type Chc struct{}

The Chc opcode is both a basic instruction and a template for other instructions.

func (Chc) AbstractAssembler 

func (Op Chc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Chc) Assembler 

func (op Chc) Assembler(arch *Arch, words []string) (string, error)

func (Chc) Disassembler 

func (op Chc) Disassembler(arch *Arch, instr string) (string, error)

func (Chc) ExtraFiles 

func (Op Chc) ExtraFiles(arch *Arch) ([]string, []string)

func (Chc) Forbidden_modes 

func (op Chc) Forbidden_modes() (bool, []string)

func (Chc) Generate 

func (op Chc) Generate(arch *Arch) string

The random genaration does nothing

func (Chc) HLAssemblerInstructionMetadata 

func (Op Chc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Chc) HLAssemblerMatch 

func (Op Chc) HLAssemblerMatch(arch *Arch) []string

func (Chc) HLAssemblerNormalize 

func (Op Chc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Chc) OpInstructionVerilogHeader 

func (op Chc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Chc) Op_get_desc 

func (op Chc) Op_get_desc() string

func (Chc) Op_get_instruction_len 

func (op Chc) Op_get_instruction_len(arch *Arch) int

func (Chc) Op_get_name 

func (op Chc) Op_get_name() string

func (Chc) Op_instruction_verilog_default_state 

func (Op Chc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Chc) Op_instruction_verilog_extra_block 

func (Op Chc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Chc) Op_instruction_verilog_extra_modules 

func (Op Chc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Chc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Chc) Op_instruction_verilog_internal_state 

func (Op Chc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Chc) Op_instruction_verilog_reset 

func (Op Chc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Chc) Op_instruction_verilog_state_machine 

func (op Chc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Chc) Op_show_assembler 

func (op Chc) Op_show_assembler(arch *Arch) string

func (Chc) Required_modes 

func (op Chc) Required_modes() (bool, []string)

func (Chc) Required_shared 

func (op Chc) Required_shared() (bool, []string)

func (Chc) Simulate 

func (op Chc) Simulate(vm *VM, instr string) error

The simulation does nothing

type Chw 

type Chw struct{}

The Chw opcode is both a basic instruction and a template for other instructions.

func (Chw) AbstractAssembler 

func (Op Chw) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Chw) Assembler 

func (op Chw) Assembler(arch *Arch, words []string) (string, error)

func (Chw) Disassembler 

func (op Chw) Disassembler(arch *Arch, instr string) (string, error)

func (Chw) ExtraFiles 

func (Op Chw) ExtraFiles(arch *Arch) ([]string, []string)

func (Chw) Forbidden_modes 

func (op Chw) Forbidden_modes() (bool, []string)

func (Chw) Generate 

func (op Chw) Generate(arch *Arch) string

The random genaration does nothing

func (Chw) HLAssemblerInstructionMetadata 

func (Op Chw) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Chw) HLAssemblerMatch 

func (Op Chw) HLAssemblerMatch(arch *Arch) []string

func (Chw) HLAssemblerNormalize 

func (Op Chw) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Chw) OpInstructionVerilogHeader 

func (op Chw) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Chw) Op_get_desc 

func (op Chw) Op_get_desc() string

func (Chw) Op_get_instruction_len 

func (op Chw) Op_get_instruction_len(arch *Arch) int

func (Chw) Op_get_name 

func (op Chw) Op_get_name() string

func (Chw) Op_instruction_verilog_default_state 

func (Op Chw) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Chw) Op_instruction_verilog_extra_block 

func (Op Chw) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Chw) Op_instruction_verilog_extra_modules 

func (Op Chw) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Chw) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Chw) Op_instruction_verilog_internal_state 

func (Op Chw) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Chw) Op_instruction_verilog_reset 

func (Op Chw) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Chw) Op_instruction_verilog_state_machine 

func (op Chw) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Chw) Op_show_assembler 

func (op Chw) Op_show_assembler(arch *Arch) string

func (Chw) Required_modes 

func (op Chw) Required_modes() (bool, []string)

func (Chw) Required_shared 

func (op Chw) Required_shared() (bool, []string)

func (Chw) Simulate 

func (op Chw) Simulate(vm *VM, instr string) error

The simulation does nothing

type Cil 

type Cil struct{}

The And opcode is both a basic instruction and a template for other instructions.

func (Cil) AbstractAssembler 

func (Op Cil) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Cil) Assembler 

func (op Cil) Assembler(arch *Arch, words []string) (string, error)

func (Cil) Disassembler 

func (op Cil) Disassembler(arch *Arch, instr string) (string, error)

func (Cil) ExtraFiles 

func (Op Cil) ExtraFiles(arch *Arch) ([]string, []string)

func (Cil) Forbidden_modes 

func (op Cil) Forbidden_modes() (bool, []string)

func (Cil) Generate 

func (op Cil) Generate(arch *Arch) string

The random genaration does nothing

func (Cil) HLAssemblerInstructionMetadata 

func (Op Cil) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Cil) HLAssemblerMatch 

func (Op Cil) HLAssemblerMatch(arch *Arch) []string

func (Cil) HLAssemblerNormalize 

func (Op Cil) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Cil) OpInstructionVerilogHeader 

func (op Cil) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Cil) Op_get_desc 

func (op Cil) Op_get_desc() string

func (Cil) Op_get_instruction_len 

func (op Cil) Op_get_instruction_len(arch *Arch) int

func (Cil) Op_get_name 

func (op Cil) Op_get_name() string

func (Cil) Op_instruction_internal_state 

func (op Cil) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Cil) Op_instruction_verilog_default_state 

func (Op Cil) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Cil) Op_instruction_verilog_extra_block 

func (Op Cil) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Cil) Op_instruction_verilog_extra_modules 

func (Op Cil) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Cil) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Cil) Op_instruction_verilog_internal_state 

func (Op Cil) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Cil) Op_instruction_verilog_reset 

func (Op Cil) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Cil) Op_instruction_verilog_state_machine 

func (op Cil) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Cil) Op_show_assembler 

func (op Cil) Op_show_assembler(arch *Arch) string

func (Cil) Required_modes 

func (op Cil) Required_modes() (bool, []string)

func (Cil) Required_shared 

func (op Cil) Required_shared() (bool, []string)

func (Cil) Simulate 

func (op Cil) Simulate(vm *VM, instr string) error

The simulation does nothing

type Cilc 

type Cilc struct{}

func (Cilc) AbstractAssembler 

func (Op Cilc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Cilc) Assembler 

func (op Cilc) Assembler(arch *Arch, words []string) (string, error)

func (Cilc) Disassembler 

func (op Cilc) Disassembler(arch *Arch, instr string) (string, error)

func (Cilc) ExtraFiles 

func (Op Cilc) ExtraFiles(arch *Arch) ([]string, []string)

func (Cilc) Forbidden_modes 

func (op Cilc) Forbidden_modes() (bool, []string)

func (Cilc) Generate 

func (op Cilc) Generate(arch *Arch) string

func (Cilc) HLAssemblerInstructionMetadata 

func (Op Cilc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Cilc) HLAssemblerMatch 

func (Op Cilc) HLAssemblerMatch(arch *Arch) []string

func (Cilc) HLAssemblerNormalize 

func (Op Cilc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Cilc) OpInstructionVerilogHeader 

func (op Cilc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Cilc) Op_get_desc 

func (op Cilc) Op_get_desc() string

func (Cilc) Op_get_instruction_len 

func (op Cilc) Op_get_instruction_len(arch *Arch) int

func (Cilc) Op_get_name 

func (op Cilc) Op_get_name() string

func (Cilc) Op_instruction_verilog_default_state 

func (Op Cilc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Cilc) Op_instruction_verilog_extra_block 

func (Op Cilc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Cilc) Op_instruction_verilog_extra_modules 

func (Op Cilc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Cilc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Cilc) Op_instruction_verilog_internal_state 

func (Op Cilc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Cilc) Op_instruction_verilog_reset 

func (Op Cilc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Cilc) Op_instruction_verilog_state_machine 

func (op Cilc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Cilc) Op_show_assembler 

func (op Cilc) Op_show_assembler(arch *Arch) string

func (Cilc) Required_modes 

func (op Cilc) Required_modes() (bool, []string)

func (Cilc) Required_shared 

func (op Cilc) Required_shared() (bool, []string)

func (Cilc) Simulate 

func (op Cilc) Simulate(vm *VM, instr string) error

type Cir 

type Cir struct{}

The And opcode is both a basic instruction and a template for other instructions.

func (Cir) AbstractAssembler 

func (Op Cir) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Cir) Assembler 

func (op Cir) Assembler(arch *Arch, words []string) (string, error)

func (Cir) Disassembler 

func (op Cir) Disassembler(arch *Arch, instr string) (string, error)

func (Cir) ExtraFiles 

func (Op Cir) ExtraFiles(arch *Arch) ([]string, []string)

func (Cir) Forbidden_modes 

func (op Cir) Forbidden_modes() (bool, []string)

func (Cir) Generate 

func (op Cir) Generate(arch *Arch) string

The random genaration does nothing

func (Cir) HLAssemblerInstructionMetadata 

func (Op Cir) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Cir) HLAssemblerMatch 

func (Op Cir) HLAssemblerMatch(arch *Arch) []string

func (Cir) HLAssemblerNormalize 

func (Op Cir) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Cir) OpInstructionVerilogHeader 

func (op Cir) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Cir) Op_get_desc 

func (op Cir) Op_get_desc() string

func (Cir) Op_get_instruction_len 

func (op Cir) Op_get_instruction_len(arch *Arch) int

func (Cir) Op_get_name 

func (op Cir) Op_get_name() string

func (Cir) Op_instruction_internal_state 

func (op Cir) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Cir) Op_instruction_verilog_default_state 

func (Op Cir) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Cir) Op_instruction_verilog_extra_block 

func (Op Cir) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Cir) Op_instruction_verilog_extra_modules 

func (Op Cir) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Cir) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Cir) Op_instruction_verilog_internal_state 

func (Op Cir) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Cir) Op_instruction_verilog_reset 

func (Op Cir) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Cir) Op_instruction_verilog_state_machine 

func (op Cir) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Cir) Op_show_assembler 

func (op Cir) Op_show_assembler(arch *Arch) string

func (Cir) Required_modes 

func (op Cir) Required_modes() (bool, []string)

func (Cir) Required_shared 

func (op Cir) Required_shared() (bool, []string)

func (Cir) Simulate 

func (op Cir) Simulate(vm *VM, instr string) error

The simulation does nothing

type Cirn 

type Cirn struct{}

func (Cirn) AbstractAssembler 

func (Op Cirn) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Cirn) Assembler 

func (op Cirn) Assembler(arch *Arch, words []string) (string, error)

func (Cirn) Disassembler 

func (op Cirn) Disassembler(arch *Arch, instr string) (string, error)

func (Cirn) ExtraFiles 

func (Op Cirn) ExtraFiles(arch *Arch) ([]string, []string)

func (Cirn) Forbidden_modes 

func (op Cirn) Forbidden_modes() (bool, []string)

func (Cirn) Generate 

func (op Cirn) Generate(arch *Arch) string

The random genaration does nothing

func (Cirn) HLAssemblerInstructionMetadata 

func (Op Cirn) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Cirn) HLAssemblerMatch 

func (Op Cirn) HLAssemblerMatch(arch *Arch) []string

func (Cirn) HLAssemblerNormalize 

func (Op Cirn) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Cirn) OpInstructionVerilogHeader 

func (op Cirn) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Cirn) Op_get_desc 

func (op Cirn) Op_get_desc() string

func (Cirn) Op_get_instruction_len 

func (op Cirn) Op_get_instruction_len(arch *Arch) int

func (Cirn) Op_get_name 

func (op Cirn) Op_get_name() string

func (Cirn) Op_instruction_internal_state 

func (op Cirn) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Cirn) Op_instruction_verilog_default_state 

func (Op Cirn) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Cirn) Op_instruction_verilog_extra_block 

func (Op Cirn) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Cirn) Op_instruction_verilog_extra_modules 

func (Op Cirn) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Cirn) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Cirn) Op_instruction_verilog_internal_state 

func (Op Cirn) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Cirn) Op_instruction_verilog_reset 

func (Op Cirn) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Cirn) Op_instruction_verilog_state_machine 

func (op Cirn) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Cirn) Op_show_assembler 

func (op Cirn) Op_show_assembler(arch *Arch) string

func (Cirn) Required_modes 

func (op Cirn) Required_modes() (bool, []string)

func (Cirn) Required_shared 

func (op Cirn) Required_shared() (bool, []string)

func (Cirn) Simulate 

func (op Cirn) Simulate(vm *VM, instr string) error

The simulation does nothing

type Clc 

type Clc struct{}

func (Clc) AbstractAssembler 

func (Op Clc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Clc) Assembler 

func (op Clc) Assembler(arch *Arch, words []string) (string, error)

func (Clc) Disassembler 

func (op Clc) Disassembler(arch *Arch, instr string) (string, error)

func (Clc) ExtraFiles 

func (Op Clc) ExtraFiles(arch *Arch) ([]string, []string)

func (Clc) Forbidden_modes 

func (op Clc) Forbidden_modes() (bool, []string)

func (Clc) Generate 

func (op Clc) Generate(arch *Arch) string

func (Clc) HLAssemblerInstructionMetadata 

func (Op Clc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Clc) HLAssemblerMatch 

func (Op Clc) HLAssemblerMatch(arch *Arch) []string

func (Clc) HLAssemblerNormalize 

func (Op Clc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Clc) OpInstructionVerilogHeader 

func (op Clc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Clc) Op_get_desc 

func (op Clc) Op_get_desc() string

func (Clc) Op_get_instruction_len 

func (op Clc) Op_get_instruction_len(arch *Arch) int

func (Clc) Op_get_name 

func (op Clc) Op_get_name() string

func (Clc) Op_instruction_verilog_default_state 

func (Op Clc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Clc) Op_instruction_verilog_extra_block 

func (Op Clc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Clc) Op_instruction_verilog_extra_modules 

func (Op Clc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Clc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Clc) Op_instruction_verilog_internal_state 

func (Op Clc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Clc) Op_instruction_verilog_reset 

func (Op Clc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Clc) Op_instruction_verilog_state_machine 

func (op Clc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Clc) Op_show_assembler 

func (op Clc) Op_show_assembler(arch *Arch) string

func (Clc) Required_modes 

func (op Clc) Required_modes() (bool, []string)

func (Clc) Required_shared 

func (op Clc) Required_shared() (bool, []string)

func (Clc) Simulate 

func (op Clc) Simulate(vm *VM, instr string) error

type Clr 

type Clr struct{}

func (Clr) AbstractAssembler 

func (Op Clr) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Clr) Assembler 

func (op Clr) Assembler(arch *Arch, words []string) (string, error)

func (Clr) Disassembler 

func (op Clr) Disassembler(arch *Arch, instr string) (string, error)

func (Clr) ExtraFiles 

func (Op Clr) ExtraFiles(arch *Arch) ([]string, []string)

func (Clr) Forbidden_modes 

func (op Clr) Forbidden_modes() (bool, []string)

func (Clr) Generate 

func (op Clr) Generate(arch *Arch) string

func (Clr) HLAssemblerInstructionMetadata 

func (Op Clr) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Clr) HLAssemblerMatch 

func (Op Clr) HLAssemblerMatch(arch *Arch) []string

func (Clr) HLAssemblerNormalize 

func (Op Clr) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Clr) OpInstructionVerilogHeader 

func (op Clr) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Clr) Op_get_desc 

func (op Clr) Op_get_desc() string

func (Clr) Op_get_instruction_len 

func (op Clr) Op_get_instruction_len(arch *Arch) int

func (Clr) Op_get_name 

func (op Clr) Op_get_name() string

func (Clr) Op_instruction_verilog_default_state 

func (Op Clr) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Clr) Op_instruction_verilog_extra_block 

func (Op Clr) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Clr) Op_instruction_verilog_extra_modules 

func (Op Clr) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Clr) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Clr) Op_instruction_verilog_internal_state 

func (Op Clr) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Clr) Op_instruction_verilog_reset 

func (Op Clr) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Clr) Op_instruction_verilog_state_machine 

func (op Clr) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Clr) Op_show_assembler 

func (op Clr) Op_show_assembler(arch *Arch) string

func (Clr) Required_modes 

func (op Clr) Required_modes() (bool, []string)

func (Clr) Required_shared 

func (op Clr) Required_shared() (bool, []string)

func (Clr) Simulate 

func (op Clr) Simulate(vm *VM, instr string) error

type Cmpr 

type Cmpr struct {
	// contains filtered or unexported fields
}

func (Cmpr) AbstractAssembler 

func (op Cmpr) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Cmpr) Assembler 

func (op Cmpr) Assembler(arch *Arch, words []string) (string, error)

func (Cmpr) Disassembler 

func (op Cmpr) Disassembler(arch *Arch, instr string) (string, error)

func (Cmpr) ExtraFiles 

func (op Cmpr) ExtraFiles(arch *Arch) ([]string, []string)

func (Cmpr) Forbidden_modes 

func (op Cmpr) Forbidden_modes() (bool, []string)

func (Cmpr) Generate 

func (op Cmpr) Generate(arch *Arch) string

The random generation does nothing

func (Cmpr) HLAssemblerInstructionMetadata 

func (op Cmpr) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Cmpr) HLAssemblerMatch 

func (op Cmpr) HLAssemblerMatch(arch *Arch) []string

func (Cmpr) HLAssemblerNormalize 

func (op Cmpr) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Cmpr) OpInstructionVerilogHeader 

func (op Cmpr) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Cmpr) Op_get_desc 

func (op Cmpr) Op_get_desc() string

func (Cmpr) Op_get_instruction_len 

func (op Cmpr) Op_get_instruction_len(arch *Arch) int

func (Cmpr) Op_get_name 

func (op Cmpr) Op_get_name() string

func (Cmpr) Op_instruction_internal_state 

func (op Cmpr) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Cmpr) Op_instruction_verilog_default_state 

func (op Cmpr) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Cmpr) Op_instruction_verilog_extra_block 

func (op Cmpr) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Cmpr) Op_instruction_verilog_extra_modules 

func (op Cmpr) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Cmpr) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Cmpr) Op_instruction_verilog_internal_state 

func (op Cmpr) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Cmpr) Op_instruction_verilog_reset 

func (op Cmpr) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Cmpr) Op_instruction_verilog_state_machine 

func (op Cmpr) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Cmpr) Op_show_assembler 

func (op Cmpr) Op_show_assembler(arch *Arch) string

func (Cmpr) Required_modes 

func (op Cmpr) Required_modes() (bool, []string)

func (Cmpr) Required_shared 

func (op Cmpr) Required_shared() (bool, []string)

func (Cmpr) Simulate 

func (op Cmpr) Simulate(vm *VM, instr string) error

type Config 

type Config struct {
	*bmreqs.ReqRoot
	*bcof.BCOFEntry
	HwOptimizations
	Debug             bool
	Commented_verilog bool
	Runinfo           *RuntimeInfo
}

type Conproc 

type Conproc struct {
	CpID  uint32
	Rsize uint8
	R     uint8 // Number of n-bit registers
	N     uint8 // Number of n-bit inputs
	M     uint8 // Number of n-bit outputs
	Op    []Opcode
}

The CPU

func (*Conproc) Decode_opcode 

func (proc *Conproc) Decode_opcode(intr string) (int, error)

func (*Conproc) Inputs_bits 

func (proc *Conproc) Inputs_bits() int

func (*Conproc) Opcodes_bits 

func (proc *Conproc) Opcodes_bits() int

func (*Conproc) Outputs_bits 

func (proc *Conproc) Outputs_bits() int

func (*Conproc) String 

func (proc *Conproc) String() string

func (*Conproc) Write_opcodes_verilog 

func (proc *Conproc) Write_opcodes_verilog() string

func (*Conproc) Write_verilog 

func (proc *Conproc) Write_verilog(conf *Config, arch *Arch, processor_module_name string, flavor string) string

type Cpy 

type Cpy struct{}

func (Cpy) AbstractAssembler 

func (Op Cpy) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Cpy) Assembler 

func (op Cpy) Assembler(arch *Arch, words []string) (string, error)

func (Cpy) Disassembler 

func (op Cpy) Disassembler(arch *Arch, instr string) (string, error)

func (Cpy) ExtraFiles 

func (Op Cpy) ExtraFiles(arch *Arch) ([]string, []string)

func (Cpy) Forbidden_modes 

func (op Cpy) Forbidden_modes() (bool, []string)

func (Cpy) Generate 

func (op Cpy) Generate(arch *Arch) string

The random genaration does nothing

func (Cpy) HLAssemblerInstructionMetadata 

func (Op Cpy) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Cpy) HLAssemblerMatch 

func (Op Cpy) HLAssemblerMatch(arch *Arch) []string

func (Cpy) HLAssemblerNormalize 

func (Op Cpy) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Cpy) OpInstructionVerilogHeader 

func (op Cpy) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Cpy) Op_get_desc 

func (op Cpy) Op_get_desc() string

func (Cpy) Op_get_instruction_len 

func (op Cpy) Op_get_instruction_len(arch *Arch) int

func (Cpy) Op_get_name 

func (op Cpy) Op_get_name() string

func (Cpy) Op_instruction_internal_state 

func (op Cpy) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Cpy) Op_instruction_verilog_default_state 

func (Op Cpy) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Cpy) Op_instruction_verilog_extra_block 

func (Op Cpy) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Cpy) Op_instruction_verilog_extra_modules 

func (Op Cpy) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Cpy) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Cpy) Op_instruction_verilog_internal_state 

func (Op Cpy) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Cpy) Op_instruction_verilog_reset 

func (Op Cpy) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Cpy) Op_instruction_verilog_state_machine 

func (op Cpy) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Cpy) Op_show_assembler 

func (op Cpy) Op_show_assembler(arch *Arch) string

func (Cpy) Required_modes 

func (op Cpy) Required_modes() (bool, []string)

func (Cpy) Required_shared 

func (op Cpy) Required_shared() (bool, []string)

func (Cpy) Simulate 

func (op Cpy) Simulate(vm *VM, instr string) error

The simulation does nothing

type Cset 

type Cset struct{}

func (Cset) AbstractAssembler 

func (Op Cset) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Cset) Assembler 

func (op Cset) Assembler(arch *Arch, words []string) (string, error)

func (Cset) Disassembler 

func (op Cset) Disassembler(arch *Arch, instr string) (string, error)

func (Cset) ExtraFiles 

func (Op Cset) ExtraFiles(arch *Arch) ([]string, []string)

func (Cset) Forbidden_modes 

func (op Cset) Forbidden_modes() (bool, []string)

func (Cset) Generate 

func (op Cset) Generate(arch *Arch) string

func (Cset) HLAssemblerInstructionMetadata 

func (Op Cset) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Cset) HLAssemblerMatch 

func (Op Cset) HLAssemblerMatch(arch *Arch) []string

func (Cset) HLAssemblerNormalize 

func (Op Cset) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Cset) OpInstructionVerilogHeader 

func (op Cset) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Cset) Op_get_desc 

func (op Cset) Op_get_desc() string

func (Cset) Op_get_instruction_len 

func (op Cset) Op_get_instruction_len(arch *Arch) int

func (Cset) Op_get_name 

func (op Cset) Op_get_name() string

func (Cset) Op_instruction_verilog_default_state 

func (Op Cset) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Cset) Op_instruction_verilog_extra_block 

func (Op Cset) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Cset) Op_instruction_verilog_extra_modules 

func (Op Cset) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Cset) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Cset) Op_instruction_verilog_internal_state 

func (Op Cset) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Cset) Op_instruction_verilog_reset 

func (Op Cset) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Cset) Op_instruction_verilog_state_machine 

func (op Cset) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Cset) Op_show_assembler 

func (op Cset) Op_show_assembler(arch *Arch) string

func (Cset) Required_modes 

func (op Cset) Required_modes() (bool, []string)

func (Cset) Required_shared 

func (op Cset) Required_shared() (bool, []string)

func (Cset) Simulate 

func (op Cset) Simulate(vm *VM, instr string) error

type Data 

type Data struct {
	Vars []string
}

The machine is an architecture provided with and execution code and an intial state

func (*Data) String 

func (d *Data) String() string

type Dec 

type Dec struct{}

func (Dec) AbstractAssembler 

func (Op Dec) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Dec) Assembler 

func (op Dec) Assembler(arch *Arch, words []string) (string, error)

func (Dec) Disassembler 

func (op Dec) Disassembler(arch *Arch, instr string) (string, error)

func (Dec) ExtraFiles 

func (Op Dec) ExtraFiles(arch *Arch) ([]string, []string)

func (Dec) Forbidden_modes 

func (op Dec) Forbidden_modes() (bool, []string)

func (Dec) Generate 

func (op Dec) Generate(arch *Arch) string

func (Dec) HLAssemblerInstructionMetadata 

func (Op Dec) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Dec) HLAssemblerMatch 

func (Op Dec) HLAssemblerMatch(arch *Arch) []string

func (Dec) HLAssemblerNormalize 

func (Op Dec) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Dec) OpInstructionVerilogHeader 

func (op Dec) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Dec) Op_get_desc 

func (op Dec) Op_get_desc() string

func (Dec) Op_get_instruction_len 

func (op Dec) Op_get_instruction_len(arch *Arch) int

func (Dec) Op_get_name 

func (op Dec) Op_get_name() string

func (Dec) Op_instruction_verilog_default_state 

func (Op Dec) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Dec) Op_instruction_verilog_extra_block 

func (Op Dec) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Dec) Op_instruction_verilog_extra_modules 

func (Op Dec) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Dec) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Dec) Op_instruction_verilog_internal_state 

func (Op Dec) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Dec) Op_instruction_verilog_reset 

func (Op Dec) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Dec) Op_instruction_verilog_state_machine 

func (op Dec) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Dec) Op_show_assembler 

func (op Dec) Op_show_assembler(arch *Arch) string

func (Dec) Required_modes 

func (op Dec) Required_modes() (bool, []string)

func (Dec) Required_shared 

func (op Dec) Required_shared() (bool, []string)

func (Dec) Simulate 

func (op Dec) Simulate(vm *VM, instr string) error

type Div 

type Div struct{}

The Div opcode is both a basic instruction and a template for other instructions.

func (Div) AbstractAssembler 

func (Op Div) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Div) Assembler 

func (op Div) Assembler(arch *Arch, words []string) (string, error)

func (Div) Disassembler 

func (op Div) Disassembler(arch *Arch, instr string) (string, error)

func (Div) ExtraFiles 

func (Op Div) ExtraFiles(arch *Arch) ([]string, []string)

func (Div) Forbidden_modes 

func (op Div) Forbidden_modes() (bool, []string)

func (Div) Generate 

func (op Div) Generate(arch *Arch) string

The random genaration does nothing

func (Div) HLAssemblerInstructionMetadata 

func (Op Div) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Div) HLAssemblerMatch 

func (Op Div) HLAssemblerMatch(arch *Arch) []string

func (Div) HLAssemblerNormalize 

func (Op Div) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Div) OpInstructionVerilogHeader 

func (op Div) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Div) Op_get_desc 

func (op Div) Op_get_desc() string

func (Div) Op_get_instruction_len 

func (op Div) Op_get_instruction_len(arch *Arch) int

func (Div) Op_get_name 

func (op Div) Op_get_name() string

func (Div) Op_instruction_internal_state 

func (op Div) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Div) Op_instruction_verilog_default_state 

func (Op Div) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Div) Op_instruction_verilog_extra_block 

func (Op Div) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Div) Op_instruction_verilog_extra_modules 

func (Op Div) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Div) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Div) Op_instruction_verilog_internal_state 

func (Op Div) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Div) Op_instruction_verilog_reset 

func (Op Div) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Div) Op_instruction_verilog_state_machine 

func (op Div) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Div) Op_show_assembler 

func (op Div) Op_show_assembler(arch *Arch) string

func (Div) Required_modes 

func (op Div) Required_modes() (bool, []string)

func (Div) Required_shared 

func (op Div) Required_shared() (bool, []string)

func (Div) Simulate 

func (op Div) Simulate(vm *VM, instr string) error

The Div opcode simulates the execution of a div instruction

type Divf 

type Divf struct{}

The Divf opcode is both a basic instruction and a template for other instructions.

func (Divf) AbstractAssembler 

func (Op Divf) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Divf) Assembler 

func (op Divf) Assembler(arch *Arch, words []string) (string, error)

func (Divf) Disassembler 

func (op Divf) Disassembler(arch *Arch, instr string) (string, error)

func (Divf) ExtraFiles 

func (Op Divf) ExtraFiles(arch *Arch) ([]string, []string)

func (Divf) Forbidden_modes 

func (op Divf) Forbidden_modes() (bool, []string)

func (Divf) Generate 

func (op Divf) Generate(arch *Arch) string

The random genaration does nothing

func (Divf) HLAssemblerInstructionMetadata 

func (Op Divf) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Divf) HLAssemblerMatch 

func (Op Divf) HLAssemblerMatch(arch *Arch) []string

func (Divf) HLAssemblerNormalize 

func (Op Divf) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Divf) OpInstructionVerilogHeader 

func (op Divf) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Divf) Op_get_desc 

func (op Divf) Op_get_desc() string

func (Divf) Op_get_instruction_len 

func (op Divf) Op_get_instruction_len(arch *Arch) int

func (Divf) Op_get_name 

func (op Divf) Op_get_name() string

func (Divf) Op_instruction_internal_state 

func (op Divf) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Divf) Op_instruction_verilog_default_state 

func (Op Divf) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Divf) Op_instruction_verilog_extra_block 

func (Op Divf) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Divf) Op_instruction_verilog_extra_modules 

func (Op Divf) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Divf) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Divf) Op_instruction_verilog_internal_state 

func (Op Divf) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Divf) Op_instruction_verilog_reset 

func (Op Divf) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Divf) Op_instruction_verilog_state_machine 

func (op Divf) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Divf) Op_show_assembler 

func (op Divf) Op_show_assembler(arch *Arch) string

func (Divf) Required_modes 

func (op Divf) Required_modes() (bool, []string)

func (Divf) Required_shared 

func (op Divf) Required_shared() (bool, []string)

func (Divf) Simulate 

func (op Divf) Simulate(vm *VM, instr string) error

The simulation does nothing

type Divf16 

type Divf16 struct{}

The Divf16 opcode is both a basic instruction and a template for other instructions.

func (Divf16) AbstractAssembler 

func (Op Divf16) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Divf16) Assembler 

func (op Divf16) Assembler(arch *Arch, words []string) (string, error)

func (Divf16) Disassembler 

func (op Divf16) Disassembler(arch *Arch, instr string) (string, error)

func (Divf16) ExtraFiles 

func (Op Divf16) ExtraFiles(arch *Arch) ([]string, []string)

func (Divf16) Forbidden_modes 

func (op Divf16) Forbidden_modes() (bool, []string)

func (Divf16) Generate 

func (op Divf16) Generate(arch *Arch) string

The random genaration does nothing

func (Divf16) HLAssemblerInstructionMetadata 

func (Op Divf16) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Divf16) HLAssemblerMatch 

func (Op Divf16) HLAssemblerMatch(arch *Arch) []string

func (Divf16) HLAssemblerNormalize 

func (Op Divf16) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Divf16) OpInstructionVerilogHeader 

func (op Divf16) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Divf16) Op_get_desc 

func (op Divf16) Op_get_desc() string

func (Divf16) Op_get_instruction_len 

func (op Divf16) Op_get_instruction_len(arch *Arch) int

func (Divf16) Op_get_name 

func (op Divf16) Op_get_name() string

func (Divf16) Op_instruction_internal_state 

func (op Divf16) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Divf16) Op_instruction_verilog_default_state 

func (Op Divf16) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Divf16) Op_instruction_verilog_extra_block 

func (Op Divf16) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Divf16) Op_instruction_verilog_extra_modules 

func (Op Divf16) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Divf16) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Divf16) Op_instruction_verilog_internal_state 

func (Op Divf16) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Divf16) Op_instruction_verilog_reset 

func (Op Divf16) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Divf16) Op_instruction_verilog_state_machine 

func (op Divf16) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Divf16) Op_show_assembler 

func (op Divf16) Op_show_assembler(arch *Arch) string

func (Divf16) Required_modes 

func (op Divf16) Required_modes() (bool, []string)

func (Divf16) Required_shared 

func (op Divf16) Required_shared() (bool, []string)

func (Divf16) Simulate 

func (op Divf16) Simulate(vm *VM, instr string) error

type Divp 

type Divp struct {
	// contains filtered or unexported fields
}

func (Divp) AbstractAssembler 

func (Op Divp) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Divp) Assembler 

func (op Divp) Assembler(arch *Arch, words []string) (string, error)

func (Divp) Disassembler 

func (op Divp) Disassembler(arch *Arch, instr string) (string, error)

func (Divp) ExtraFiles 

func (Op Divp) ExtraFiles(arch *Arch) ([]string, []string)

func (Divp) Forbidden_modes 

func (op Divp) Forbidden_modes() (bool, []string)

func (Divp) Generate 

func (op Divp) Generate(arch *Arch) string

The random genaration does nothing

func (Divp) HLAssemblerInstructionMetadata 

func (Op Divp) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Divp) HLAssemblerMatch 

func (Op Divp) HLAssemblerMatch(arch *Arch) []string

func (Divp) HLAssemblerNormalize 

func (Op Divp) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Divp) OpInstructionVerilogHeader 

func (op Divp) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Divp) Op_get_desc 

func (op Divp) Op_get_desc() string

func (Divp) Op_get_instruction_len 

func (op Divp) Op_get_instruction_len(arch *Arch) int

func (Divp) Op_get_name 

func (op Divp) Op_get_name() string

func (Divp) Op_instruction_internal_state 

func (op Divp) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Divp) Op_instruction_verilog_default_state 

func (Op Divp) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Divp) Op_instruction_verilog_extra_block 

func (Op Divp) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Divp) Op_instruction_verilog_extra_modules 

func (Op Divp) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Divp) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Divp) Op_instruction_verilog_internal_state 

func (Op Divp) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Divp) Op_instruction_verilog_reset 

func (Op Divp) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Divp) Op_instruction_verilog_state_machine 

func (op Divp) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Divp) Op_show_assembler 

func (op Divp) Op_show_assembler(arch *Arch) string

func (Divp) Required_modes 

func (op Divp) Required_modes() (bool, []string)

func (Divp) Required_shared 

func (op Divp) Required_shared() (bool, []string)

func (Divp) Simulate 

func (op Divp) Simulate(vm *VM, instr string) error

type Dpc 

type Dpc struct{}

The Dpc opcode is both a basic instruction and a template for other instructions.

func (Dpc) AbstractAssembler 

func (Op Dpc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Dpc) Assembler 

func (op Dpc) Assembler(arch *Arch, words []string) (string, error)

func (Dpc) Disassembler 

func (op Dpc) Disassembler(arch *Arch, instr string) (string, error)

func (Dpc) ExtraFiles 

func (Op Dpc) ExtraFiles(arch *Arch) ([]string, []string)

func (Dpc) Forbidden_modes 

func (op Dpc) Forbidden_modes() (bool, []string)

func (Dpc) Generate 

func (op Dpc) Generate(arch *Arch) string

The random genaration does nothing

func (Dpc) HLAssemblerInstructionMetadata 

func (Op Dpc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Dpc) HLAssemblerMatch 

func (Op Dpc) HLAssemblerMatch(arch *Arch) []string

func (Dpc) HLAssemblerNormalize 

func (Op Dpc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Dpc) OpInstructionVerilogHeader 

func (op Dpc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Dpc) Op_get_desc 

func (op Dpc) Op_get_desc() string

func (Dpc) Op_get_instruction_len 

func (op Dpc) Op_get_instruction_len(arch *Arch) int

func (Dpc) Op_get_name 

func (op Dpc) Op_get_name() string

func (Dpc) Op_instruction_internal_state 

func (op Dpc) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Dpc) Op_instruction_verilog_default_state 

func (Op Dpc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Dpc) Op_instruction_verilog_extra_block 

func (Op Dpc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Dpc) Op_instruction_verilog_extra_modules 

func (Op Dpc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Dpc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Dpc) Op_instruction_verilog_internal_state 

func (Op Dpc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Dpc) Op_instruction_verilog_reset 

func (Op Dpc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Dpc) Op_instruction_verilog_state_machine 

func (op Dpc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Dpc) Op_show_assembler 

func (op Dpc) Op_show_assembler(arch *Arch) string

func (Dpc) Required_modes 

func (op Dpc) Required_modes() (bool, []string)

func (Dpc) Required_shared 

func (op Dpc) Required_shared() (bool, []string)

func (Dpc) Simulate 

func (op Dpc) Simulate(vm *VM, instr string) error

The simulation does nothing

type DynCall 

type DynCall struct {
}

func (DynCall) CreateInstruction 

func (d DynCall) CreateInstruction(name string) (Opcode, error)

func (DynCall) GetName 

func (d DynCall) GetName() string

func (DynCall) HLAssemblerGeneratorList 

func (d DynCall) HLAssemblerGeneratorList(bmc *bmconfig.BmConfig, bl *bmline.BasmLine) []string

func (DynCall) HLAssemblerGeneratorMatch 

func (d DynCall) HLAssemblerGeneratorMatch(bmc *bmconfig.BmConfig) []string

func (DynCall) MatchName 

func (d DynCall) MatchName(name string) bool

type DynFixedPoint 

type DynFixedPoint struct {
}

func (DynFixedPoint) CreateInstruction 

func (d DynFixedPoint) CreateInstruction(name string) (Opcode, error)

func (DynFixedPoint) GetName 

func (d DynFixedPoint) GetName() string

func (DynFixedPoint) HLAssemblerGeneratorList 

func (d DynFixedPoint) HLAssemblerGeneratorList(bmc *bmconfig.BmConfig, bl *bmline.BasmLine) []string

func (DynFixedPoint) HLAssemblerGeneratorMatch 

func (d DynFixedPoint) HLAssemblerGeneratorMatch(bmc *bmconfig.BmConfig) []string

func (DynFixedPoint) MatchName 

func (d DynFixedPoint) MatchName(name string) bool

type DynFloPoCo 

type DynFloPoCo struct{}

func (DynFloPoCo) CreateInstruction 

func (d DynFloPoCo) CreateInstruction(name string) (Opcode, error)

func (DynFloPoCo) GetName 

func (d DynFloPoCo) GetName() string

func (DynFloPoCo) HLAssemblerGeneratorList 

func (d DynFloPoCo) HLAssemblerGeneratorList(bmc *bmconfig.BmConfig, bl *bmline.BasmLine) []string

func (DynFloPoCo) HLAssemblerGeneratorMatch 

func (d DynFloPoCo) HLAssemblerGeneratorMatch(bmc *bmconfig.BmConfig) []string

func (DynFloPoCo) MatchName 

func (d DynFloPoCo) MatchName(name string) bool

type DynLinearQuantizer 

type DynLinearQuantizer struct {
	Ranges *map[int]bmnumbers.LinearDataRange
}

func (DynLinearQuantizer) CreateInstruction 

func (d DynLinearQuantizer) CreateInstruction(name string) (Opcode, error)

func (DynLinearQuantizer) GetName 

func (d DynLinearQuantizer) GetName() string

func (DynLinearQuantizer) HLAssemblerGeneratorList 

func (d DynLinearQuantizer) HLAssemblerGeneratorList(bmc *bmconfig.BmConfig, bl *bmline.BasmLine) []string

func (DynLinearQuantizer) HLAssemblerGeneratorMatch 

func (d DynLinearQuantizer) HLAssemblerGeneratorMatch(bmc *bmconfig.BmConfig) []string

func (DynLinearQuantizer) MatchName 

func (d DynLinearQuantizer) MatchName(name string) bool

type DynOpStack 

type DynOpStack struct {
	// contains filtered or unexported fields
}

func (DynOpStack) AbstractAssembler 

func (op DynOpStack) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (DynOpStack) Assembler 

func (op DynOpStack) Assembler(arch *Arch, words []string) (string, error)

func (DynOpStack) Disassembler 

func (op DynOpStack) Disassembler(arch *Arch, instr string) (string, error)

func (DynOpStack) ExtraFiles 

func (op DynOpStack) ExtraFiles(arch *Arch) ([]string, []string)

func (DynOpStack) Forbidden_modes 

func (op DynOpStack) Forbidden_modes() (bool, []string)

func (DynOpStack) Generate 

func (op DynOpStack) Generate(arch *Arch) string

func (DynOpStack) HLAssemblerInstructionMetadata 

func (op DynOpStack) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (DynOpStack) HLAssemblerMatch 

func (op DynOpStack) HLAssemblerMatch(arch *Arch) []string

func (DynOpStack) HLAssemblerNormalize 

func (op DynOpStack) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (DynOpStack) OpInstructionVerilogHeader 

func (op DynOpStack) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (DynOpStack) Op_get_desc 

func (op DynOpStack) Op_get_desc() string

func (DynOpStack) Op_get_instruction_len 

func (op DynOpStack) Op_get_instruction_len(arch *Arch) int

func (DynOpStack) Op_get_name 

func (op DynOpStack) Op_get_name() string

func (DynOpStack) Op_instruction_verilog_default_state 

func (op DynOpStack) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (DynOpStack) Op_instruction_verilog_extra_block 

func (op DynOpStack) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (DynOpStack) Op_instruction_verilog_extra_modules 

func (op DynOpStack) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op DynOpStack) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (DynOpStack) Op_instruction_verilog_internal_state 

func (op DynOpStack) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (DynOpStack) Op_instruction_verilog_reset 

func (op DynOpStack) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (DynOpStack) Op_instruction_verilog_state_machine 

func (op DynOpStack) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (DynOpStack) Op_show_assembler 

func (op DynOpStack) Op_show_assembler(arch *Arch) string

func (DynOpStack) Required_modes 

func (op DynOpStack) Required_modes() (bool, []string)

func (DynOpStack) Required_shared 

func (op DynOpStack) Required_shared() (bool, []string)

func (DynOpStack) Simulate 

func (op DynOpStack) Simulate(vm *VM, instr string) error

type DynRsets 

type DynRsets struct {
}

func (DynRsets) CreateInstruction 

func (d DynRsets) CreateInstruction(name string) (Opcode, error)

func (DynRsets) GetName 

func (d DynRsets) GetName() string

func (DynRsets) HLAssemblerGeneratorList 

func (d DynRsets) HLAssemblerGeneratorList(bmc *bmconfig.BmConfig, line *bmline.BasmLine) []string

func (DynRsets) HLAssemblerGeneratorMatch 

func (d DynRsets) HLAssemblerGeneratorMatch(bmc *bmconfig.BmConfig) []string

func (DynRsets) MatchName 

func (d DynRsets) MatchName(name string) bool

type DynStack 

type DynStack struct {
}

func (DynStack) CreateInstruction 

func (d DynStack) CreateInstruction(name string) (Opcode, error)

func (DynStack) GetName 

func (d DynStack) GetName() string

func (DynStack) HLAssemblerGeneratorList 

func (d DynStack) HLAssemblerGeneratorList(bmc *bmconfig.BmConfig, bl *bmline.BasmLine) []string

func (DynStack) HLAssemblerGeneratorMatch 

func (d DynStack) HLAssemblerGeneratorMatch(bmc *bmconfig.BmConfig) []string

func (DynStack) MatchName 

func (d DynStack) MatchName(name string) bool

type DynamicInstruction 

type DynamicInstruction interface {
	GetName() string
	MatchName(string) bool
	CreateInstruction(string) (Opcode, error)
	HLAssemblerGeneratorMatch(*bmconfig.BmConfig) []string
	HLAssemblerGeneratorList(*bmconfig.BmConfig, *bmline.BasmLine) []string
}

type Expf 

type Expf struct{}

func (Expf) AbstractAssembler 

func (Op Expf) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Expf) Assembler 

func (op Expf) Assembler(arch *Arch, words []string) (string, error)

func (Expf) Disassembler 

func (op Expf) Disassembler(arch *Arch, instr string) (string, error)

func (Expf) ExtraFiles 

func (Op Expf) ExtraFiles(arch *Arch) ([]string, []string)

func (Expf) Forbidden_modes 

func (op Expf) Forbidden_modes() (bool, []string)

func (Expf) Generate 

func (op Expf) Generate(arch *Arch) string

func (Expf) HLAssemblerInstructionMetadata 

func (Op Expf) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Expf) HLAssemblerMatch 

func (Op Expf) HLAssemblerMatch(arch *Arch) []string

func (Expf) HLAssemblerNormalize 

func (Op Expf) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Expf) OpInstructionVerilogHeader 

func (op Expf) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Expf) Op_get_desc 

func (op Expf) Op_get_desc() string

func (Expf) Op_get_instruction_len 

func (op Expf) Op_get_instruction_len(arch *Arch) int

func (Expf) Op_get_name 

func (op Expf) Op_get_name() string

func (Expf) Op_instruction_verilog_default_state 

func (Op Expf) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Expf) Op_instruction_verilog_extra_block 

func (Op Expf) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Expf) Op_instruction_verilog_extra_modules 

func (Op Expf) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Expf) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Expf) Op_instruction_verilog_internal_state 

func (Op Expf) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Expf) Op_instruction_verilog_reset 

func (Op Expf) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Expf) Op_instruction_verilog_state_machine 

func (op Expf) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Expf) Op_show_assembler 

func (op Expf) Op_show_assembler(arch *Arch) string

func (Expf) Required_modes 

func (op Expf) Required_modes() (bool, []string)

func (Expf) Required_shared 

func (op Expf) Required_shared() (bool, []string)

func (Expf) Simulate 

func (op Expf) Simulate(vm *VM, instr string) error

type FixedPoint 

type FixedPoint struct {
	// contains filtered or unexported fields
}

The FixedPoint opcode is both a basic instruction and a template for other instructions.

func (FixedPoint) AbstractAssembler 

func (Op FixedPoint) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (FixedPoint) Assembler 

func (op FixedPoint) Assembler(arch *Arch, words []string) (string, error)

func (FixedPoint) Disassembler 

func (op FixedPoint) Disassembler(arch *Arch, instr string) (string, error)

func (FixedPoint) ExtraFiles 

func (Op FixedPoint) ExtraFiles(arch *Arch) ([]string, []string)

func (FixedPoint) Forbidden_modes 

func (op FixedPoint) Forbidden_modes() (bool, []string)

func (FixedPoint) Generate 

func (op FixedPoint) Generate(arch *Arch) string

The random genaration does nothing

func (FixedPoint) HLAssemblerInstructionMetadata 

func (Op FixedPoint) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (FixedPoint) HLAssemblerMatch 

func (Op FixedPoint) HLAssemblerMatch(arch *Arch) []string

func (FixedPoint) HLAssemblerNormalize 

func (Op FixedPoint) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (FixedPoint) OpInstructionVerilogHeader 

func (op FixedPoint) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (FixedPoint) Op_get_desc 

func (op FixedPoint) Op_get_desc() string

func (FixedPoint) Op_get_instruction_len 

func (op FixedPoint) Op_get_instruction_len(arch *Arch) int

func (FixedPoint) Op_get_name 

func (op FixedPoint) Op_get_name() string

func (FixedPoint) Op_instruction_internal_state 

func (op FixedPoint) Op_instruction_internal_state(arch *Arch, flavor string) string

func (FixedPoint) Op_instruction_verilog_default_state 

func (Op FixedPoint) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (FixedPoint) Op_instruction_verilog_extra_block 

func (Op FixedPoint) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (FixedPoint) Op_instruction_verilog_extra_modules 

func (op FixedPoint) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op FixedPoint) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (FixedPoint) Op_instruction_verilog_internal_state 

func (Op FixedPoint) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (FixedPoint) Op_instruction_verilog_reset 

func (Op FixedPoint) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (FixedPoint) Op_instruction_verilog_state_machine 

func (op FixedPoint) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (FixedPoint) Op_show_assembler 

func (op FixedPoint) Op_show_assembler(arch *Arch) string

func (FixedPoint) Required_modes 

func (op FixedPoint) Required_modes() (bool, []string)

func (FixedPoint) Required_shared 

func (op FixedPoint) Required_shared() (bool, []string)

func (FixedPoint) Simulate 

func (op FixedPoint) Simulate(vm *VM, instr string) error

type FloPoCo 

type FloPoCo struct {
	// contains filtered or unexported fields
}

The FloPoCo opcode is both a basic instruction and a template for other instructions.

func (FloPoCo) AbstractAssembler 

func (Op FloPoCo) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (FloPoCo) Assembler 

func (op FloPoCo) Assembler(arch *Arch, words []string) (string, error)

func (FloPoCo) Disassembler 

func (op FloPoCo) Disassembler(arch *Arch, instr string) (string, error)

func (FloPoCo) ExtraFiles 

func (Op FloPoCo) ExtraFiles(arch *Arch) ([]string, []string)

func (FloPoCo) Forbidden_modes 

func (op FloPoCo) Forbidden_modes() (bool, []string)

func (FloPoCo) Generate 

func (op FloPoCo) Generate(arch *Arch) string

The random genaration does nothing

func (FloPoCo) HLAssemblerInstructionMetadata 

func (Op FloPoCo) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (FloPoCo) HLAssemblerMatch 

func (Op FloPoCo) HLAssemblerMatch(arch *Arch) []string

func (FloPoCo) HLAssemblerNormalize 

func (Op FloPoCo) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (FloPoCo) OpInstructionVerilogHeader 

func (op FloPoCo) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (FloPoCo) Op_get_desc 

func (op FloPoCo) Op_get_desc() string

func (FloPoCo) Op_get_instruction_len 

func (op FloPoCo) Op_get_instruction_len(arch *Arch) int

func (FloPoCo) Op_get_name 

func (op FloPoCo) Op_get_name() string

func (FloPoCo) Op_instruction_internal_state 

func (op FloPoCo) Op_instruction_internal_state(arch *Arch, flavor string) string

func (FloPoCo) Op_instruction_verilog_default_state 

func (Op FloPoCo) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (FloPoCo) Op_instruction_verilog_extra_block 

func (Op FloPoCo) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (FloPoCo) Op_instruction_verilog_extra_modules 

func (Op FloPoCo) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op FloPoCo) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (FloPoCo) Op_instruction_verilog_internal_state 

func (Op FloPoCo) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (FloPoCo) Op_instruction_verilog_reset 

func (Op FloPoCo) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (FloPoCo) Op_instruction_verilog_state_machine 

func (op FloPoCo) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (FloPoCo) Op_show_assembler 

func (op FloPoCo) Op_show_assembler(arch *Arch) string

func (FloPoCo) Required_modes 

func (op FloPoCo) Required_modes() (bool, []string)

func (FloPoCo) Required_shared 

func (op FloPoCo) Required_shared() (bool, []string)

func (FloPoCo) Simulate 

func (op FloPoCo) Simulate(vm *VM, instr string) error

type Hit 

type Hit struct{}

The Hit opcode is both a basic instruction and a template for other instructions.

func (Hit) AbstractAssembler 

func (Op Hit) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Hit) Assembler 

func (op Hit) Assembler(arch *Arch, words []string) (string, error)

func (Hit) Disassembler 

func (op Hit) Disassembler(arch *Arch, instr string) (string, error)

func (Hit) ExtraFiles 

func (Op Hit) ExtraFiles(arch *Arch) ([]string, []string)

func (Hit) Forbidden_modes 

func (op Hit) Forbidden_modes() (bool, []string)

func (Hit) Generate 

func (op Hit) Generate(arch *Arch) string

The random genaration does nothing

func (Hit) HLAssemblerInstructionMetadata 

func (Op Hit) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Hit) HLAssemblerMatch 

func (Op Hit) HLAssemblerMatch(arch *Arch) []string

func (Hit) HLAssemblerNormalize 

func (Op Hit) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Hit) OpInstructionVerilogHeader 

func (op Hit) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Hit) Op_get_desc 

func (op Hit) Op_get_desc() string

func (Hit) Op_get_instruction_len 

func (op Hit) Op_get_instruction_len(arch *Arch) int

func (Hit) Op_get_name 

func (op Hit) Op_get_name() string

func (Hit) Op_instruction_verilog_default_state 

func (Op Hit) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Hit) Op_instruction_verilog_extra_block 

func (Op Hit) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Hit) Op_instruction_verilog_extra_modules 

func (Op Hit) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Hit) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Hit) Op_instruction_verilog_internal_state 

func (Op Hit) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Hit) Op_instruction_verilog_reset 

func (Op Hit) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Hit) Op_instruction_verilog_state_machine 

func (op Hit) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Hit) Op_show_assembler 

func (op Hit) Op_show_assembler(arch *Arch) string

func (Hit) Required_modes 

func (op Hit) Required_modes() (bool, []string)

func (Hit) Required_shared 

func (op Hit) Required_shared() (bool, []string)

func (Hit) Simulate 

func (op Hit) Simulate(vm *VM, instr string) error

The simulation does nothing

type Hlt 

type Hlt struct{}

The Hlt opcode is both a basic instruction and a template for other instructions.

func (Hlt) AbstractAssembler 

func (Op Hlt) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Hlt) Assembler 

func (op Hlt) Assembler(arch *Arch, words []string) (string, error)

func (Hlt) Disassembler 

func (op Hlt) Disassembler(arch *Arch, instr string) (string, error)

func (Hlt) ExtraFiles 

func (Op Hlt) ExtraFiles(arch *Arch) ([]string, []string)

func (Hlt) Forbidden_modes 

func (op Hlt) Forbidden_modes() (bool, []string)

func (Hlt) Generate 

func (op Hlt) Generate(arch *Arch) string

The random genaration does nothing

func (Hlt) HLAssemblerInstructionMetadata 

func (Op Hlt) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Hlt) HLAssemblerMatch 

func (Op Hlt) HLAssemblerMatch(arch *Arch) []string

func (Hlt) HLAssemblerNormalize 

func (Op Hlt) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Hlt) OpInstructionVerilogHeader 

func (op Hlt) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Hlt) Op_get_desc 

func (op Hlt) Op_get_desc() string

func (Hlt) Op_get_instruction_len 

func (op Hlt) Op_get_instruction_len(arch *Arch) int

func (Hlt) Op_get_name 

func (op Hlt) Op_get_name() string

func (Hlt) Op_instruction_verilog_default_state 

func (Op Hlt) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Hlt) Op_instruction_verilog_extra_block 

func (Op Hlt) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Hlt) Op_instruction_verilog_extra_modules 

func (Op Hlt) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Hlt) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Hlt) Op_instruction_verilog_internal_state 

func (Op Hlt) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Hlt) Op_instruction_verilog_reset 

func (Op Hlt) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Hlt) Op_instruction_verilog_state_machine 

func (op Hlt) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Hlt) Op_show_assembler 

func (op Hlt) Op_show_assembler(arch *Arch) string

func (Hlt) Required_modes 

func (op Hlt) Required_modes() (bool, []string)

func (Hlt) Required_shared 

func (op Hlt) Required_shared() (bool, []string)

func (Hlt) Simulate 

func (op Hlt) Simulate(vm *VM, instr string) error

The simulation does nothing

type HwOptimizations 

type HwOptimizations uint64

func HwOptimizationId 

func HwOptimizationId(name string) HwOptimizations

func SetHwOptimization 

func SetHwOptimization(current HwOptimizations, optimization HwOptimizations) HwOptimizations

func UnsetHwOptimization 

func UnsetHwOptimization(current HwOptimizations, optimization HwOptimizations) HwOptimizations

type I2r 

type I2r struct{}

func (I2r) AbstractAssembler 

func (Op I2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (I2r) Assembler 

func (op I2r) Assembler(arch *Arch, words []string) (string, error)

func (I2r) Disassembler 

func (op I2r) Disassembler(arch *Arch, instr string) (string, error)

func (I2r) ExtraFiles 

func (Op I2r) ExtraFiles(arch *Arch) ([]string, []string)

func (I2r) Forbidden_modes 

func (op I2r) Forbidden_modes() (bool, []string)

func (I2r) Generate 

func (op I2r) Generate(arch *Arch) string

func (I2r) HLAssemblerInstructionMetadata 

func (Op I2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (I2r) HLAssemblerMatch 

func (Op I2r) HLAssemblerMatch(arch *Arch) []string

func (I2r) HLAssemblerNormalize 

func (Op I2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (I2r) OpInstructionVerilogHeader 

func (op I2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (I2r) Op_get_desc 

func (op I2r) Op_get_desc() string

func (I2r) Op_get_instruction_len 

func (op I2r) Op_get_instruction_len(arch *Arch) int

func (I2r) Op_get_name 

func (op I2r) Op_get_name() string

func (I2r) Op_instruction_internal_state 

func (op I2r) Op_instruction_internal_state(arch *Arch, flavor string) string

func (I2r) Op_instruction_verilog_default_state 

func (Op I2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (I2r) Op_instruction_verilog_extra_block 

func (Op I2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (I2r) Op_instruction_verilog_extra_modules 

func (Op I2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op I2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (I2r) Op_instruction_verilog_internal_state 

func (Op I2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (I2r) Op_instruction_verilog_reset 

func (Op I2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (I2r) Op_instruction_verilog_state_machine 

func (op I2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (I2r) Op_show_assembler 

func (op I2r) Op_show_assembler(arch *Arch) string

func (I2r) Required_modes 

func (op I2r) Required_modes() (bool, []string)

func (I2r) Required_shared 

func (op I2r) Required_shared() (bool, []string)

func (I2r) Simulate 

func (op I2r) Simulate(vm *VM, instr string) error

type I2rw 

type I2rw struct{}

func (I2rw) AbstractAssembler 

func (Op I2rw) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (I2rw) Assembler 

func (op I2rw) Assembler(arch *Arch, words []string) (string, error)

func (I2rw) Disassembler 

func (op I2rw) Disassembler(arch *Arch, instr string) (string, error)

func (I2rw) ExtraFiles 

func (Op I2rw) ExtraFiles(arch *Arch) ([]string, []string)

func (I2rw) Forbidden_modes 

func (op I2rw) Forbidden_modes() (bool, []string)

func (I2rw) Generate 

func (op I2rw) Generate(arch *Arch) string

func (I2rw) HLAssemblerInstructionMetadata 

func (Op I2rw) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (I2rw) HLAssemblerMatch 

func (Op I2rw) HLAssemblerMatch(arch *Arch) []string

func (I2rw) HLAssemblerNormalize 

func (Op I2rw) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (I2rw) OpInstructionVerilogHeader 

func (op I2rw) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (I2rw) Op_get_desc 

func (op I2rw) Op_get_desc() string

func (I2rw) Op_get_instruction_len 

func (op I2rw) Op_get_instruction_len(arch *Arch) int

func (I2rw) Op_get_name 

func (op I2rw) Op_get_name() string

func (I2rw) Op_instruction_internal_state 

func (op I2rw) Op_instruction_internal_state(arch *Arch, flavor string) string

func (I2rw) Op_instruction_verilog_default_state 

func (Op I2rw) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (I2rw) Op_instruction_verilog_extra_block 

func (Op I2rw) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (I2rw) Op_instruction_verilog_extra_modules 

func (Op I2rw) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op I2rw) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (I2rw) Op_instruction_verilog_internal_state 

func (Op I2rw) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (I2rw) Op_instruction_verilog_reset 

func (Op I2rw) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (I2rw) Op_instruction_verilog_state_machine 

func (op I2rw) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (I2rw) Op_show_assembler 

func (op I2rw) Op_show_assembler(arch *Arch) string

func (I2rw) Required_modes 

func (op I2rw) Required_modes() (bool, []string)

func (I2rw) Required_shared 

func (op I2rw) Required_shared() (bool, []string)

func (I2rw) Simulate 

func (op I2rw) Simulate(vm *VM, instr string) error

type Inc 

type Inc struct{}

func (Inc) AbstractAssembler 

func (Op Inc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Inc) Assembler 

func (op Inc) Assembler(arch *Arch, words []string) (string, error)

func (Inc) Disassembler 

func (op Inc) Disassembler(arch *Arch, instr string) (string, error)

func (Inc) ExtraFiles 

func (Op Inc) ExtraFiles(arch *Arch) ([]string, []string)

func (Inc) Forbidden_modes 

func (op Inc) Forbidden_modes() (bool, []string)

func (Inc) Generate 

func (op Inc) Generate(arch *Arch) string

func (Inc) HLAssemblerInstructionMetadata 

func (Op Inc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Inc) HLAssemblerMatch 

func (Op Inc) HLAssemblerMatch(arch *Arch) []string

func (Inc) HLAssemblerNormalize 

func (Op Inc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Inc) OpInstructionVerilogHeader 

func (op Inc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Inc) Op_get_desc 

func (op Inc) Op_get_desc() string

func (Inc) Op_get_instruction_len 

func (op Inc) Op_get_instruction_len(arch *Arch) int

func (Inc) Op_get_name 

func (op Inc) Op_get_name() string

func (Inc) Op_instruction_verilog_default_state 

func (Op Inc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Inc) Op_instruction_verilog_extra_block 

func (Op Inc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Inc) Op_instruction_verilog_extra_modules 

func (Op Inc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Inc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Inc) Op_instruction_verilog_internal_state 

func (Op Inc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Inc) Op_instruction_verilog_reset 

func (Op Inc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Inc) Op_instruction_verilog_state_machine 

func (op Inc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Inc) Op_show_assembler 

func (op Inc) Op_show_assembler(arch *Arch) string

func (Inc) Required_modes 

func (op Inc) Required_modes() (bool, []string)

func (Inc) Required_shared 

func (op Inc) Required_shared() (bool, []string)

func (Inc) Simulate 

func (op Inc) Simulate(vm *VM, instr string) error

type Incc 

type Incc struct{}

func (Incc) AbstractAssembler 

func (Op Incc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Incc) Assembler 

func (op Incc) Assembler(arch *Arch, words []string) (string, error)

func (Incc) Disassembler 

func (op Incc) Disassembler(arch *Arch, instr string) (string, error)

func (Incc) ExtraFiles 

func (Op Incc) ExtraFiles(arch *Arch) ([]string, []string)

func (Incc) Forbidden_modes 

func (op Incc) Forbidden_modes() (bool, []string)

func (Incc) Generate 

func (op Incc) Generate(arch *Arch) string

func (Incc) HLAssemblerInstructionMetadata 

func (Op Incc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Incc) HLAssemblerMatch 

func (Op Incc) HLAssemblerMatch(arch *Arch) []string

func (Incc) HLAssemblerNormalize 

func (Op Incc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Incc) OpInstructionVerilogHeader 

func (op Incc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Incc) Op_get_desc 

func (op Incc) Op_get_desc() string

func (Incc) Op_get_instruction_len 

func (op Incc) Op_get_instruction_len(arch *Arch) int

func (Incc) Op_get_name 

func (op Incc) Op_get_name() string

func (Incc) Op_instruction_verilog_default_state 

func (Op Incc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Incc) Op_instruction_verilog_extra_block 

func (Op Incc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Incc) Op_instruction_verilog_extra_modules 

func (Op Incc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Incc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Incc) Op_instruction_verilog_internal_state 

func (Op Incc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Incc) Op_instruction_verilog_reset 

func (Op Incc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Incc) Op_instruction_verilog_state_machine 

func (op Incc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Incc) Op_show_assembler 

func (op Incc) Op_show_assembler(arch *Arch) string

func (Incc) Required_modes 

func (op Incc) Required_modes() (bool, []string)

func (Incc) Required_shared 

func (op Incc) Required_shared() (bool, []string)

func (Incc) Simulate 

func (op Incc) Simulate(vm *VM, instr string) error

type J 

type J struct{}

func (J) AbstractAssembler 

func (Op J) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (J) Assembler 

func (op J) Assembler(arch *Arch, words []string) (string, error)

func (J) Disassembler 

func (op J) Disassembler(arch *Arch, instr string) (string, error)

func (J) ExtraFiles 

func (Op J) ExtraFiles(arch *Arch) ([]string, []string)

func (J) Forbidden_modes 

func (op J) Forbidden_modes() (bool, []string)

func (J) Generate 

func (op J) Generate(arch *Arch) string

func (J) HLAssemblerInstructionMetadata 

func (Op J) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (J) HLAssemblerMatch 

func (Op J) HLAssemblerMatch(arch *Arch) []string

func (J) HLAssemblerNormalize 

func (Op J) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (J) OpInstructionVerilogHeader 

func (op J) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (J) Op_get_desc 

func (op J) Op_get_desc() string

func (J) Op_get_instruction_len 

func (op J) Op_get_instruction_len(arch *Arch) int

func (J) Op_get_name 

func (op J) Op_get_name() string

func (J) Op_instruction_verilog_default_state 

func (Op J) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (J) Op_instruction_verilog_extra_block 

func (Op J) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (J) Op_instruction_verilog_extra_modules 

func (Op J) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op J) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (J) Op_instruction_verilog_internal_state 

func (Op J) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (J) Op_instruction_verilog_reset 

func (Op J) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (J) Op_instruction_verilog_state_machine 

func (op J) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (J) Op_show_assembler 

func (op J) Op_show_assembler(arch *Arch) string

func (J) Required_modes 

func (op J) Required_modes() (bool, []string)

func (J) Required_shared 

func (op J) Required_shared() (bool, []string)

func (J) Simulate 

func (op J) Simulate(vm *VM, instr string) error

type Ja 

type Ja struct{}

func (Ja) AbstractAssembler 

func (op Ja) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Ja) Assembler 

func (op Ja) Assembler(arch *Arch, words []string) (string, error)

func (Ja) Disassembler 

func (op Ja) Disassembler(arch *Arch, instr string) (string, error)

func (Ja) ExtraFiles 

func (op Ja) ExtraFiles(arch *Arch) ([]string, []string)

func (Ja) Forbidden_modes 

func (op Ja) Forbidden_modes() (bool, []string)

func (Ja) Generate 

func (op Ja) Generate(arch *Arch) string

func (Ja) HLAssemblerInstructionMetadata 

func (op Ja) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Ja) HLAssemblerMatch 

func (op Ja) HLAssemblerMatch(arch *Arch) []string

func (Ja) HLAssemblerNormalize 

func (op Ja) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Ja) OpInstructionVerilogHeader 

func (op Ja) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Ja) Op_get_desc 

func (op Ja) Op_get_desc() string

func (Ja) Op_get_instruction_len 

func (op Ja) Op_get_instruction_len(arch *Arch) int

func (Ja) Op_get_name 

func (op Ja) Op_get_name() string

func (Ja) Op_instruction_verilog_default_state 

func (op Ja) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Ja) Op_instruction_verilog_extra_block 

func (op Ja) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Ja) Op_instruction_verilog_extra_modules 

func (op Ja) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Ja) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Ja) Op_instruction_verilog_internal_state 

func (op Ja) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Ja) Op_instruction_verilog_reset 

func (op Ja) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Ja) Op_instruction_verilog_state_machine 

func (op Ja) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Ja) Op_show_assembler 

func (op Ja) Op_show_assembler(arch *Arch) string

func (Ja) Required_modes 

func (op Ja) Required_modes() (bool, []string)

func (Ja) Required_shared 

func (op Ja) Required_shared() (bool, []string)

func (Ja) Simulate 

func (op Ja) Simulate(vm *VM, instr string) error

type Jc 

type Jc struct{}

func (Jc) AbstractAssembler 

func (Op Jc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jc) Assembler 

func (op Jc) Assembler(arch *Arch, words []string) (string, error)

func (Jc) Disassembler 

func (op Jc) Disassembler(arch *Arch, instr string) (string, error)

func (Jc) ExtraFiles 

func (Op Jc) ExtraFiles(arch *Arch) ([]string, []string)

func (Jc) Forbidden_modes 

func (op Jc) Forbidden_modes() (bool, []string)

func (Jc) Generate 

func (op Jc) Generate(arch *Arch) string

func (Jc) HLAssemblerInstructionMetadata 

func (Op Jc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jc) HLAssemblerMatch 

func (Op Jc) HLAssemblerMatch(arch *Arch) []string

func (Jc) HLAssemblerNormalize 

func (Op Jc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jc) OpInstructionVerilogHeader 

func (op Jc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Jc) Op_get_desc 

func (op Jc) Op_get_desc() string

func (Jc) Op_get_instruction_len 

func (op Jc) Op_get_instruction_len(arch *Arch) int

func (Jc) Op_get_name 

func (op Jc) Op_get_name() string

func (Jc) Op_instruction_verilog_default_state 

func (Op Jc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jc) Op_instruction_verilog_extra_block 

func (Op Jc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jc) Op_instruction_verilog_extra_modules 

func (Op Jc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jc) Op_instruction_verilog_internal_state 

func (Op Jc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jc) Op_instruction_verilog_reset 

func (Op Jc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jc) Op_instruction_verilog_state_machine 

func (op Jc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jc) Op_show_assembler 

func (op Jc) Op_show_assembler(arch *Arch) string

func (Jc) Required_modes 

func (op Jc) Required_modes() (bool, []string)

func (Jc) Required_shared 

func (op Jc) Required_shared() (bool, []string)

func (Jc) Simulate 

func (op Jc) Simulate(vm *VM, instr string) error

type Jcmpa 

type Jcmpa struct{}

func (Jcmpa) AbstractAssembler 

func (op Jcmpa) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jcmpa) Assembler 

func (op Jcmpa) Assembler(arch *Arch, words []string) (string, error)

func (Jcmpa) Disassembler 

func (op Jcmpa) Disassembler(arch *Arch, instr string) (string, error)

func (Jcmpa) ExtraFiles 

func (op Jcmpa) ExtraFiles(arch *Arch) ([]string, []string)

func (Jcmpa) Forbidden_modes 

func (op Jcmpa) Forbidden_modes() (bool, []string)

func (Jcmpa) Generate 

func (op Jcmpa) Generate(arch *Arch) string

func (Jcmpa) HLAssemblerInstructionMetadata 

func (op Jcmpa) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jcmpa) HLAssemblerMatch 

func (op Jcmpa) HLAssemblerMatch(arch *Arch) []string

func (Jcmpa) HLAssemblerNormalize 

func (op Jcmpa) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jcmpa) OpInstructionVerilogHeader 

func (op Jcmpa) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Jcmpa) Op_get_desc 

func (op Jcmpa) Op_get_desc() string

func (Jcmpa) Op_get_instruction_len 

func (op Jcmpa) Op_get_instruction_len(arch *Arch) int

func (Jcmpa) Op_get_name 

func (op Jcmpa) Op_get_name() string

func (Jcmpa) Op_instruction_verilog_default_state 

func (op Jcmpa) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jcmpa) Op_instruction_verilog_extra_block 

func (op Jcmpa) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jcmpa) Op_instruction_verilog_extra_modules 

func (op Jcmpa) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jcmpa) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jcmpa) Op_instruction_verilog_internal_state 

func (op Jcmpa) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jcmpa) Op_instruction_verilog_reset 

func (op Jcmpa) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jcmpa) Op_instruction_verilog_state_machine 

func (op Jcmpa) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jcmpa) Op_show_assembler 

func (op Jcmpa) Op_show_assembler(arch *Arch) string

func (Jcmpa) Required_modes 

func (op Jcmpa) Required_modes() (bool, []string)

func (Jcmpa) Required_shared 

func (op Jcmpa) Required_shared() (bool, []string)

func (Jcmpa) Simulate 

func (op Jcmpa) Simulate(vm *VM, instr string) error

type Jcmpl 

type Jcmpl struct{}

func (Jcmpl) AbstractAssembler 

func (op Jcmpl) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jcmpl) Assembler 

func (op Jcmpl) Assembler(arch *Arch, words []string) (string, error)

func (Jcmpl) Disassembler 

func (op Jcmpl) Disassembler(arch *Arch, instr string) (string, error)

func (Jcmpl) ExtraFiles 

func (op Jcmpl) ExtraFiles(arch *Arch) ([]string, []string)

func (Jcmpl) Forbidden_modes 

func (op Jcmpl) Forbidden_modes() (bool, []string)

func (Jcmpl) Generate 

func (op Jcmpl) Generate(arch *Arch) string

func (Jcmpl) HLAssemblerInstructionMetadata 

func (op Jcmpl) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jcmpl) HLAssemblerMatch 

func (op Jcmpl) HLAssemblerMatch(arch *Arch) []string

func (Jcmpl) HLAssemblerNormalize 

func (op Jcmpl) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jcmpl) OpInstructionVerilogHeader 

func (op Jcmpl) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Jcmpl) Op_get_desc 

func (op Jcmpl) Op_get_desc() string

func (Jcmpl) Op_get_instruction_len 

func (op Jcmpl) Op_get_instruction_len(arch *Arch) int

func (Jcmpl) Op_get_name 

func (op Jcmpl) Op_get_name() string

func (Jcmpl) Op_instruction_verilog_default_state 

func (op Jcmpl) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jcmpl) Op_instruction_verilog_extra_block 

func (op Jcmpl) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jcmpl) Op_instruction_verilog_extra_modules 

func (op Jcmpl) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jcmpl) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jcmpl) Op_instruction_verilog_internal_state 

func (op Jcmpl) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jcmpl) Op_instruction_verilog_reset 

func (op Jcmpl) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jcmpl) Op_instruction_verilog_state_machine 

func (op Jcmpl) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jcmpl) Op_show_assembler 

func (op Jcmpl) Op_show_assembler(arch *Arch) string

func (Jcmpl) Required_modes 

func (op Jcmpl) Required_modes() (bool, []string)

func (Jcmpl) Required_shared 

func (op Jcmpl) Required_shared() (bool, []string)

func (Jcmpl) Simulate 

func (op Jcmpl) Simulate(vm *VM, instr string) error

type Jcmpo 

type Jcmpo struct{}

func (Jcmpo) AbstractAssembler 

func (op Jcmpo) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jcmpo) Assembler 

func (op Jcmpo) Assembler(arch *Arch, words []string) (string, error)

func (Jcmpo) Disassembler 

func (op Jcmpo) Disassembler(arch *Arch, instr string) (string, error)

func (Jcmpo) ExtraFiles 

func (op Jcmpo) ExtraFiles(arch *Arch) ([]string, []string)

func (Jcmpo) Forbidden_modes 

func (op Jcmpo) Forbidden_modes() (bool, []string)

func (Jcmpo) Generate 

func (op Jcmpo) Generate(arch *Arch) string

func (Jcmpo) HLAssemblerInstructionMetadata 

func (op Jcmpo) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jcmpo) HLAssemblerMatch 

func (op Jcmpo) HLAssemblerMatch(arch *Arch) []string

func (Jcmpo) HLAssemblerNormalize 

func (op Jcmpo) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jcmpo) OpInstructionVerilogHeader 

func (op Jcmpo) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Jcmpo) Op_get_desc 

func (op Jcmpo) Op_get_desc() string

func (Jcmpo) Op_get_instruction_len 

func (op Jcmpo) Op_get_instruction_len(arch *Arch) int

func (Jcmpo) Op_get_name 

func (op Jcmpo) Op_get_name() string

func (Jcmpo) Op_instruction_verilog_default_state 

func (op Jcmpo) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jcmpo) Op_instruction_verilog_extra_block 

func (op Jcmpo) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jcmpo) Op_instruction_verilog_extra_modules 

func (op Jcmpo) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jcmpo) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jcmpo) Op_instruction_verilog_internal_state 

func (op Jcmpo) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jcmpo) Op_instruction_verilog_reset 

func (op Jcmpo) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jcmpo) Op_instruction_verilog_state_machine 

func (op Jcmpo) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jcmpo) Op_show_assembler 

func (op Jcmpo) Op_show_assembler(arch *Arch) string

func (Jcmpo) Required_modes 

func (op Jcmpo) Required_modes() (bool, []string)

func (Jcmpo) Required_shared 

func (op Jcmpo) Required_shared() (bool, []string)

func (Jcmpo) Simulate 

func (op Jcmpo) Simulate(vm *VM, instr string) error

type Jcmpria 

type Jcmpria struct{}

func (Jcmpria) AbstractAssembler 

func (Op Jcmpria) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jcmpria) Assembler 

func (op Jcmpria) Assembler(arch *Arch, words []string) (string, error)

func (Jcmpria) Disassembler 

func (op Jcmpria) Disassembler(arch *Arch, instr string) (string, error)

func (Jcmpria) ExtraFiles 

func (Op Jcmpria) ExtraFiles(arch *Arch) ([]string, []string)

func (Jcmpria) Forbidden_modes 

func (op Jcmpria) Forbidden_modes() (bool, []string)

func (Jcmpria) Generate 

func (op Jcmpria) Generate(arch *Arch) string

func (Jcmpria) HLAssemblerInstructionMetadata 

func (Op Jcmpria) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jcmpria) HLAssemblerMatch 

func (Op Jcmpria) HLAssemblerMatch(arch *Arch) []string

func (Jcmpria) HLAssemblerNormalize 

func (Op Jcmpria) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jcmpria) OpInstructionVerilogHeader 

func (op Jcmpria) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Jcmpria) Op_get_desc 

func (op Jcmpria) Op_get_desc() string

func (Jcmpria) Op_get_instruction_len 

func (op Jcmpria) Op_get_instruction_len(arch *Arch) int

func (Jcmpria) Op_get_name 

func (op Jcmpria) Op_get_name() string

func (Jcmpria) Op_instruction_verilog_default_state 

func (Op Jcmpria) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jcmpria) Op_instruction_verilog_extra_block 

func (Op Jcmpria) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jcmpria) Op_instruction_verilog_extra_modules 

func (Op Jcmpria) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jcmpria) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jcmpria) Op_instruction_verilog_internal_state 

func (Op Jcmpria) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jcmpria) Op_instruction_verilog_reset 

func (Op Jcmpria) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jcmpria) Op_instruction_verilog_state_machine 

func (op Jcmpria) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jcmpria) Op_show_assembler 

func (op Jcmpria) Op_show_assembler(arch *Arch) string

func (Jcmpria) Required_modes 

func (op Jcmpria) Required_modes() (bool, []string)

func (Jcmpria) Required_shared 

func (op Jcmpria) Required_shared() (bool, []string)

func (Jcmpria) Simulate 

func (op Jcmpria) Simulate(vm *VM, instr string) error

type Jcmprio 

type Jcmprio struct{}

func (Jcmprio) AbstractAssembler 

func (Op Jcmprio) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jcmprio) Assembler 

func (op Jcmprio) Assembler(arch *Arch, words []string) (string, error)

func (Jcmprio) Disassembler 

func (op Jcmprio) Disassembler(arch *Arch, instr string) (string, error)

func (Jcmprio) ExtraFiles 

func (Op Jcmprio) ExtraFiles(arch *Arch) ([]string, []string)

func (Jcmprio) Forbidden_modes 

func (op Jcmprio) Forbidden_modes() (bool, []string)

func (Jcmprio) Generate 

func (op Jcmprio) Generate(arch *Arch) string

func (Jcmprio) HLAssemblerInstructionMetadata 

func (Op Jcmprio) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jcmprio) HLAssemblerMatch 

func (Op Jcmprio) HLAssemblerMatch(arch *Arch) []string

func (Jcmprio) HLAssemblerNormalize 

func (Op Jcmprio) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jcmprio) OpInstructionVerilogHeader 

func (op Jcmprio) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Jcmprio) Op_get_desc 

func (op Jcmprio) Op_get_desc() string

func (Jcmprio) Op_get_instruction_len 

func (op Jcmprio) Op_get_instruction_len(arch *Arch) int

func (Jcmprio) Op_get_name 

func (op Jcmprio) Op_get_name() string

func (Jcmprio) Op_instruction_verilog_default_state 

func (Op Jcmprio) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jcmprio) Op_instruction_verilog_extra_block 

func (Op Jcmprio) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jcmprio) Op_instruction_verilog_extra_modules 

func (Op Jcmprio) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jcmprio) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jcmprio) Op_instruction_verilog_internal_state 

func (Op Jcmprio) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jcmprio) Op_instruction_verilog_reset 

func (Op Jcmprio) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jcmprio) Op_instruction_verilog_state_machine 

func (op Jcmprio) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jcmprio) Op_show_assembler 

func (op Jcmprio) Op_show_assembler(arch *Arch) string

func (Jcmprio) Required_modes 

func (op Jcmprio) Required_modes() (bool, []string)

func (Jcmprio) Required_shared 

func (op Jcmprio) Required_shared() (bool, []string)

func (Jcmprio) Simulate 

func (op Jcmprio) Simulate(vm *VM, instr string) error

type Je 

type Je struct{}

The Je opcode is both a basic instruction and a template for other instructions.

func (Je) AbstractAssembler 

func (Op Je) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Je) Assembler 

func (op Je) Assembler(arch *Arch, words []string) (string, error)

func (Je) Disassembler 

func (op Je) Disassembler(arch *Arch, instr string) (string, error)

func (Je) ExtraFiles 

func (Op Je) ExtraFiles(arch *Arch) ([]string, []string)

func (Je) Forbidden_modes 

func (op Je) Forbidden_modes() (bool, []string)

func (Je) Generate 

func (op Je) Generate(arch *Arch) string

The random genaration does nothing

func (Je) HLAssemblerInstructionMetadata 

func (Op Je) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Je) HLAssemblerMatch 

func (Op Je) HLAssemblerMatch(arch *Arch) []string

func (Je) HLAssemblerNormalize 

func (Op Je) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Je) OpInstructionVerilogHeader 

func (op Je) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Je) Op_get_desc 

func (op Je) Op_get_desc() string

func (Je) Op_get_instruction_len 

func (op Je) Op_get_instruction_len(arch *Arch) int

func (Je) Op_get_name 

func (op Je) Op_get_name() string

func (Je) Op_instruction_internal_state 

func (op Je) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Je) Op_instruction_verilog_default_state 

func (Op Je) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Je) Op_instruction_verilog_extra_block 

func (Op Je) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Je) Op_instruction_verilog_extra_modules 

func (Op Je) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Je) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Je) Op_instruction_verilog_internal_state 

func (Op Je) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Je) Op_instruction_verilog_reset 

func (Op Je) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Je) Op_instruction_verilog_state_machine 

func (op Je) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Je) Op_show_assembler 

func (op Je) Op_show_assembler(arch *Arch) string

func (Je) Required_modes 

func (op Je) Required_modes() (bool, []string)

func (Je) Required_shared 

func (op Je) Required_shared() (bool, []string)

func (Je) Simulate 

func (op Je) Simulate(vm *VM, instr string) error

The simulation does nothing

type Jgt0f 

type Jgt0f struct{}

The Jgt0f opcode is both a basic instruction and a template for other instructions.

func (Jgt0f) AbstractAssembler 

func (Op Jgt0f) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jgt0f) Assembler 

func (op Jgt0f) Assembler(arch *Arch, words []string) (string, error)

func (Jgt0f) Disassembler 

func (op Jgt0f) Disassembler(arch *Arch, instr string) (string, error)

func (Jgt0f) ExtraFiles 

func (Op Jgt0f) ExtraFiles(arch *Arch) ([]string, []string)

func (Jgt0f) Forbidden_modes 

func (op Jgt0f) Forbidden_modes() (bool, []string)

func (Jgt0f) Generate 

func (op Jgt0f) Generate(arch *Arch) string

The random genaration does nothing

func (Jgt0f) HLAssemblerInstructionMetadata 

func (Op Jgt0f) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jgt0f) HLAssemblerMatch 

func (Op Jgt0f) HLAssemblerMatch(arch *Arch) []string

func (Jgt0f) HLAssemblerNormalize 

func (Op Jgt0f) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jgt0f) OpInstructionVerilogHeader 

func (op Jgt0f) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Jgt0f) Op_get_desc 

func (op Jgt0f) Op_get_desc() string

func (Jgt0f) Op_get_instruction_len 

func (op Jgt0f) Op_get_instruction_len(arch *Arch) int

func (Jgt0f) Op_get_name 

func (op Jgt0f) Op_get_name() string

func (Jgt0f) Op_instruction_verilog_default_state 

func (Op Jgt0f) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jgt0f) Op_instruction_verilog_extra_block 

func (Op Jgt0f) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jgt0f) Op_instruction_verilog_extra_modules 

func (Op Jgt0f) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jgt0f) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jgt0f) Op_instruction_verilog_internal_state 

func (Op Jgt0f) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jgt0f) Op_instruction_verilog_reset 

func (Op Jgt0f) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jgt0f) Op_instruction_verilog_state_machine 

func (op Jgt0f) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jgt0f) Op_show_assembler 

func (op Jgt0f) Op_show_assembler(arch *Arch) string

func (Jgt0f) Required_modes 

func (op Jgt0f) Required_modes() (bool, []string)

func (Jgt0f) Required_shared 

func (op Jgt0f) Required_shared() (bool, []string)

func (Jgt0f) Simulate 

func (op Jgt0f) Simulate(vm *VM, instr string) error

The simulation does nothing

type Jo 

type Jo struct{}

func (Jo) AbstractAssembler 

func (op Jo) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jo) Assembler 

func (op Jo) Assembler(arch *Arch, words []string) (string, error)

func (Jo) Disassembler 

func (op Jo) Disassembler(arch *Arch, instr string) (string, error)

func (Jo) ExtraFiles 

func (op Jo) ExtraFiles(arch *Arch) ([]string, []string)

func (Jo) Forbidden_modes 

func (op Jo) Forbidden_modes() (bool, []string)

func (Jo) Generate 

func (op Jo) Generate(arch *Arch) string

func (Jo) HLAssemblerInstructionMetadata 

func (op Jo) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jo) HLAssemblerMatch 

func (op Jo) HLAssemblerMatch(arch *Arch) []string

func (Jo) HLAssemblerNormalize 

func (op Jo) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jo) OpInstructionVerilogHeader 

func (op Jo) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Jo) Op_get_desc 

func (op Jo) Op_get_desc() string

func (Jo) Op_get_instruction_len 

func (op Jo) Op_get_instruction_len(arch *Arch) int

func (Jo) Op_get_name 

func (op Jo) Op_get_name() string

func (Jo) Op_instruction_verilog_default_state 

func (op Jo) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jo) Op_instruction_verilog_extra_block 

func (op Jo) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jo) Op_instruction_verilog_extra_modules 

func (op Jo) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jo) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jo) Op_instruction_verilog_internal_state 

func (op Jo) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jo) Op_instruction_verilog_reset 

func (op Jo) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jo) Op_instruction_verilog_state_machine 

func (op Jo) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jo) Op_show_assembler 

func (op Jo) Op_show_assembler(arch *Arch) string

func (Jo) Required_modes 

func (op Jo) Required_modes() (bool, []string)

func (Jo) Required_shared 

func (op Jo) Required_shared() (bool, []string)

func (Jo) Simulate 

func (op Jo) Simulate(vm *VM, instr string) error

type Jri 

type Jri struct{}

func (Jri) AbstractAssembler 

func (Op Jri) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jri) Assembler 

func (op Jri) Assembler(arch *Arch, words []string) (string, error)

func (Jri) Disassembler 

func (op Jri) Disassembler(arch *Arch, instr string) (string, error)

func (Jri) ExtraFiles 

func (Op Jri) ExtraFiles(arch *Arch) ([]string, []string)

func (Jri) Forbidden_modes 

func (op Jri) Forbidden_modes() (bool, []string)

func (Jri) Generate 

func (op Jri) Generate(arch *Arch) string

func (Jri) HLAssemblerInstructionMetadata 

func (Op Jri) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jri) HLAssemblerMatch 

func (Op Jri) HLAssemblerMatch(arch *Arch) []string

func (Jri) HLAssemblerNormalize 

func (Op Jri) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jri) OpInstructionVerilogHeader 

func (op Jri) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Jri) Op_get_desc 

func (op Jri) Op_get_desc() string

func (Jri) Op_get_instruction_len 

func (op Jri) Op_get_instruction_len(arch *Arch) int

func (Jri) Op_get_name 

func (op Jri) Op_get_name() string

func (Jri) Op_instruction_verilog_default_state 

func (Op Jri) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jri) Op_instruction_verilog_extra_block 

func (Op Jri) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jri) Op_instruction_verilog_extra_modules 

func (Op Jri) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jri) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jri) Op_instruction_verilog_internal_state 

func (Op Jri) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jri) Op_instruction_verilog_reset 

func (Op Jri) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jri) Op_instruction_verilog_state_machine 

func (op Jri) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jri) Op_show_assembler 

func (op Jri) Op_show_assembler(arch *Arch) string

func (Jri) Required_modes 

func (op Jri) Required_modes() (bool, []string)

func (Jri) Required_shared 

func (op Jri) Required_shared() (bool, []string)

func (Jri) Simulate 

func (op Jri) Simulate(vm *VM, instr string) error

type Jria 

type Jria struct{}

func (Jria) AbstractAssembler 

func (Op Jria) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jria) Assembler 

func (op Jria) Assembler(arch *Arch, words []string) (string, error)

func (Jria) Disassembler 

func (op Jria) Disassembler(arch *Arch, instr string) (string, error)

func (Jria) ExtraFiles 

func (Op Jria) ExtraFiles(arch *Arch) ([]string, []string)

func (Jria) Forbidden_modes 

func (op Jria) Forbidden_modes() (bool, []string)

func (Jria) Generate 

func (op Jria) Generate(arch *Arch) string

func (Jria) HLAssemblerInstructionMetadata 

func (Op Jria) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jria) HLAssemblerMatch 

func (Op Jria) HLAssemblerMatch(arch *Arch) []string

func (Jria) HLAssemblerNormalize 

func (Op Jria) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jria) OpInstructionVerilogHeader 

func (op Jria) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Jria) Op_get_desc 

func (op Jria) Op_get_desc() string

func (Jria) Op_get_instruction_len 

func (op Jria) Op_get_instruction_len(arch *Arch) int

func (Jria) Op_get_name 

func (op Jria) Op_get_name() string

func (Jria) Op_instruction_verilog_default_state 

func (Op Jria) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jria) Op_instruction_verilog_extra_block 

func (Op Jria) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jria) Op_instruction_verilog_extra_modules 

func (Op Jria) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jria) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jria) Op_instruction_verilog_internal_state 

func (Op Jria) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jria) Op_instruction_verilog_reset 

func (Op Jria) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jria) Op_instruction_verilog_state_machine 

func (op Jria) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jria) Op_show_assembler 

func (op Jria) Op_show_assembler(arch *Arch) string

func (Jria) Required_modes 

func (op Jria) Required_modes() (bool, []string)

func (Jria) Required_shared 

func (op Jria) Required_shared() (bool, []string)

func (Jria) Simulate 

func (op Jria) Simulate(vm *VM, instr string) error

type Jrio 

type Jrio struct{}

func (Jrio) AbstractAssembler 

func (Op Jrio) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jrio) Assembler 

func (op Jrio) Assembler(arch *Arch, words []string) (string, error)

func (Jrio) Disassembler 

func (op Jrio) Disassembler(arch *Arch, instr string) (string, error)

func (Jrio) ExtraFiles 

func (Op Jrio) ExtraFiles(arch *Arch) ([]string, []string)

func (Jrio) Forbidden_modes 

func (op Jrio) Forbidden_modes() (bool, []string)

func (Jrio) Generate 

func (op Jrio) Generate(arch *Arch) string

func (Jrio) HLAssemblerInstructionMetadata 

func (Op Jrio) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jrio) HLAssemblerMatch 

func (Op Jrio) HLAssemblerMatch(arch *Arch) []string

func (Jrio) HLAssemblerNormalize 

func (Op Jrio) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jrio) OpInstructionVerilogHeader 

func (op Jrio) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Jrio) Op_get_desc 

func (op Jrio) Op_get_desc() string

func (Jrio) Op_get_instruction_len 

func (op Jrio) Op_get_instruction_len(arch *Arch) int

func (Jrio) Op_get_name 

func (op Jrio) Op_get_name() string

func (Jrio) Op_instruction_verilog_default_state 

func (Op Jrio) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jrio) Op_instruction_verilog_extra_block 

func (Op Jrio) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jrio) Op_instruction_verilog_extra_modules 

func (Op Jrio) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jrio) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jrio) Op_instruction_verilog_internal_state 

func (Op Jrio) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jrio) Op_instruction_verilog_reset 

func (Op Jrio) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jrio) Op_instruction_verilog_state_machine 

func (op Jrio) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jrio) Op_show_assembler 

func (op Jrio) Op_show_assembler(arch *Arch) string

func (Jrio) Required_modes 

func (op Jrio) Required_modes() (bool, []string)

func (Jrio) Required_shared 

func (op Jrio) Required_shared() (bool, []string)

func (Jrio) Simulate 

func (op Jrio) Simulate(vm *VM, instr string) error

type Jz 

type Jz struct{}

The Jz opcode is both a basic instruction and a template for other instructions.

func (Jz) AbstractAssembler 

func (Op Jz) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Jz) Assembler 

func (op Jz) Assembler(arch *Arch, words []string) (string, error)

func (Jz) Disassembler 

func (op Jz) Disassembler(arch *Arch, instr string) (string, error)

func (Jz) ExtraFiles 

func (Op Jz) ExtraFiles(arch *Arch) ([]string, []string)

func (Jz) Forbidden_modes 

func (op Jz) Forbidden_modes() (bool, []string)

func (Jz) Generate 

func (op Jz) Generate(arch *Arch) string

The random genaration does nothing

func (Jz) HLAssemblerInstructionMetadata 

func (Op Jz) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Jz) HLAssemblerMatch 

func (Op Jz) HLAssemblerMatch(arch *Arch) []string

func (Jz) HLAssemblerNormalize 

func (Op Jz) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Jz) OpInstructionVerilogHeader 

func (op Jz) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Jz) Op_get_desc 

func (op Jz) Op_get_desc() string

func (Jz) Op_get_instruction_len 

func (op Jz) Op_get_instruction_len(arch *Arch) int

func (Jz) Op_get_name 

func (op Jz) Op_get_name() string

func (Jz) Op_instruction_verilog_default_state 

func (Op Jz) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Jz) Op_instruction_verilog_extra_block 

func (Op Jz) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Jz) Op_instruction_verilog_extra_modules 

func (Op Jz) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Jz) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Jz) Op_instruction_verilog_internal_state 

func (Op Jz) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Jz) Op_instruction_verilog_reset 

func (Op Jz) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Jz) Op_instruction_verilog_state_machine 

func (op Jz) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Jz) Op_show_assembler 

func (op Jz) Op_show_assembler(arch *Arch) string

func (Jz) Required_modes 

func (op Jz) Required_modes() (bool, []string)

func (Jz) Required_shared 

func (op Jz) Required_shared() (bool, []string)

func (Jz) Simulate 

func (op Jz) Simulate(vm *VM, instr string) error

The simulation does nothing

type K2r 

type K2r struct{}

The opcode

func (K2r) AbstractAssembler 

func (Op K2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (K2r) Assembler 

func (op K2r) Assembler(arch *Arch, words []string) (string, error)

func (K2r) Disassembler 

func (op K2r) Disassembler(arch *Arch, instr string) (string, error)

func (K2r) ExtraFiles 

func (Op K2r) ExtraFiles(arch *Arch) ([]string, []string)

func (K2r) Forbidden_modes 

func (op K2r) Forbidden_modes() (bool, []string)

func (K2r) Generate 

func (op K2r) Generate(arch *Arch) string

The random genaration does nothing

func (K2r) HLAssemblerInstructionMetadata 

func (Op K2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (K2r) HLAssemblerMatch 

func (Op K2r) HLAssemblerMatch(arch *Arch) []string

func (K2r) HLAssemblerNormalize 

func (Op K2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (K2r) OpInstructionVerilogHeader 

func (op K2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (K2r) Op_get_desc 

func (op K2r) Op_get_desc() string

func (K2r) Op_get_instruction_len 

func (op K2r) Op_get_instruction_len(arch *Arch) int

func (K2r) Op_get_name 

func (op K2r) Op_get_name() string

func (K2r) Op_instruction_verilog_default_state 

func (Op K2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (K2r) Op_instruction_verilog_extra_block 

func (Op K2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (K2r) Op_instruction_verilog_extra_modules 

func (Op K2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op K2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (K2r) Op_instruction_verilog_internal_state 

func (Op K2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (K2r) Op_instruction_verilog_reset 

func (Op K2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (K2r) Op_instruction_verilog_state_machine 

func (op K2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (K2r) Op_show_assembler 

func (op K2r) Op_show_assembler(arch *Arch) string

func (K2r) Required_modes 

func (op K2r) Required_modes() (bool, []string)

func (K2r) Required_shared 

func (op K2r) Required_shared() (bool, []string)

func (K2r) Simulate 

func (op K2r) Simulate(vm *VM, instr string) error

The simulation does nothing

type Kbd 

type Kbd struct{}

func (Kbd) GetArchHeader 

func (op Kbd) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Kbd) GetArchParams 

func (op Kbd) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Kbd) GetCPParams 

func (op Kbd) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Kbd) Shortname 

func (op Kbd) Shortname() string

func (Kbd) Shr_get_name 

func (op Kbd) Shr_get_name() string

type Lfsr8 

type Lfsr8 struct{}

func (Lfsr8) GetArchHeader 

func (op Lfsr8) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Lfsr8) GetArchParams 

func (op Lfsr8) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Lfsr8) GetCPParams 

func (op Lfsr8) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Lfsr8) Shortname 

func (op Lfsr8) Shortname() string

func (Lfsr8) Shr_get_name 

func (op Lfsr8) Shr_get_name() string

type Lfsr82r 

type Lfsr82r struct{}

The Lfsr82r opcode is both a basic instruction and a template for other instructions.

func (Lfsr82r) AbstractAssembler 

func (Op Lfsr82r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Lfsr82r) Assembler 

func (op Lfsr82r) Assembler(arch *Arch, words []string) (string, error)

func (Lfsr82r) Disassembler 

func (op Lfsr82r) Disassembler(arch *Arch, instr string) (string, error)

func (Lfsr82r) ExtraFiles 

func (Op Lfsr82r) ExtraFiles(arch *Arch) ([]string, []string)

func (Lfsr82r) Forbidden_modes 

func (op Lfsr82r) Forbidden_modes() (bool, []string)

func (Lfsr82r) Generate 

func (op Lfsr82r) Generate(arch *Arch) string

The random genaration does nothing

func (Lfsr82r) HLAssemblerInstructionMetadata 

func (Op Lfsr82r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Lfsr82r) HLAssemblerMatch 

func (Op Lfsr82r) HLAssemblerMatch(arch *Arch) []string

func (Lfsr82r) HLAssemblerNormalize 

func (Op Lfsr82r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Lfsr82r) OpInstructionVerilogHeader 

func (op Lfsr82r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Lfsr82r) Op_get_desc 

func (op Lfsr82r) Op_get_desc() string

func (Lfsr82r) Op_get_instruction_len 

func (op Lfsr82r) Op_get_instruction_len(arch *Arch) int

func (Lfsr82r) Op_get_name 

func (op Lfsr82r) Op_get_name() string

func (Lfsr82r) Op_instruction_verilog_default_state 

func (Op Lfsr82r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Lfsr82r) Op_instruction_verilog_extra_block 

func (Op Lfsr82r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Lfsr82r) Op_instruction_verilog_extra_modules 

func (Op Lfsr82r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Lfsr82r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Lfsr82r) Op_instruction_verilog_internal_state 

func (Op Lfsr82r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Lfsr82r) Op_instruction_verilog_reset 

func (Op Lfsr82r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Lfsr82r) Op_instruction_verilog_state_machine 

func (op Lfsr82r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Lfsr82r) Op_show_assembler 

func (op Lfsr82r) Op_show_assembler(arch *Arch) string

func (Lfsr82r) Required_modes 

func (op Lfsr82r) Required_modes() (bool, []string)

func (Lfsr82r) Required_shared 

func (op Lfsr82r) Required_shared() (bool, []string)

func (Lfsr82r) Simulate 

func (op Lfsr82r) Simulate(vm *VM, instr string) error

The simulation does nothing

type LinearQuantizer 

type LinearQuantizer struct {
	// contains filtered or unexported fields
}

The LinearQuantizer opcode is both a basic instruction and a template for other instructions.

func (LinearQuantizer) AbstractAssembler 

func (Op LinearQuantizer) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (LinearQuantizer) Assembler 

func (op LinearQuantizer) Assembler(arch *Arch, words []string) (string, error)

func (LinearQuantizer) Disassembler 

func (op LinearQuantizer) Disassembler(arch *Arch, instr string) (string, error)

func (LinearQuantizer) ExtraFiles 

func (Op LinearQuantizer) ExtraFiles(arch *Arch) ([]string, []string)

func (LinearQuantizer) Forbidden_modes 

func (op LinearQuantizer) Forbidden_modes() (bool, []string)

func (LinearQuantizer) Generate 

func (op LinearQuantizer) Generate(arch *Arch) string

The random genaration does nothing

func (LinearQuantizer) HLAssemblerInstructionMetadata 

func (Op LinearQuantizer) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (LinearQuantizer) HLAssemblerMatch 

func (Op LinearQuantizer) HLAssemblerMatch(arch *Arch) []string

func (LinearQuantizer) HLAssemblerNormalize 

func (Op LinearQuantizer) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (LinearQuantizer) OpInstructionVerilogHeader 

func (op LinearQuantizer) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (LinearQuantizer) Op_get_desc 

func (op LinearQuantizer) Op_get_desc() string

func (LinearQuantizer) Op_get_instruction_len 

func (op LinearQuantizer) Op_get_instruction_len(arch *Arch) int

func (LinearQuantizer) Op_get_name 

func (op LinearQuantizer) Op_get_name() string

func (LinearQuantizer) Op_instruction_internal_state 

func (op LinearQuantizer) Op_instruction_internal_state(arch *Arch, flavor string) string

func (LinearQuantizer) Op_instruction_verilog_default_state 

func (Op LinearQuantizer) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (LinearQuantizer) Op_instruction_verilog_extra_block 

func (Op LinearQuantizer) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (LinearQuantizer) Op_instruction_verilog_extra_modules 

func (op LinearQuantizer) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op LinearQuantizer) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (LinearQuantizer) Op_instruction_verilog_internal_state 

func (Op LinearQuantizer) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (LinearQuantizer) Op_instruction_verilog_reset 

func (Op LinearQuantizer) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (LinearQuantizer) Op_instruction_verilog_state_machine 

func (op LinearQuantizer) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (LinearQuantizer) Op_show_assembler 

func (op LinearQuantizer) Op_show_assembler(arch *Arch) string

func (LinearQuantizer) Required_modes 

func (op LinearQuantizer) Required_modes() (bool, []string)

func (LinearQuantizer) Required_shared 

func (op LinearQuantizer) Required_shared() (bool, []string)

func (LinearQuantizer) Simulate 

func (op LinearQuantizer) Simulate(vm *VM, instr string) error

type M2r 

type M2r struct{}

func (M2r) AbstractAssembler 

func (Op M2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (M2r) Assembler 

func (op M2r) Assembler(arch *Arch, words []string) (string, error)

func (M2r) Disassembler 

func (op M2r) Disassembler(arch *Arch, instr string) (string, error)

func (M2r) ExtraFiles 

func (Op M2r) ExtraFiles(arch *Arch) ([]string, []string)

func (M2r) Forbidden_modes 

func (op M2r) Forbidden_modes() (bool, []string)

func (M2r) Generate 

func (op M2r) Generate(arch *Arch) string

func (M2r) HLAssemblerInstructionMetadata 

func (Op M2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (M2r) HLAssemblerMatch 

func (Op M2r) HLAssemblerMatch(arch *Arch) []string

func (M2r) HLAssemblerNormalize 

func (Op M2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (M2r) OpInstructionVerilogHeader 

func (op M2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (M2r) Op_get_desc 

func (op M2r) Op_get_desc() string

func (M2r) Op_get_instruction_len 

func (op M2r) Op_get_instruction_len(arch *Arch) int

func (M2r) Op_get_name 

func (op M2r) Op_get_name() string

func (M2r) Op_instruction_verilog_default_state 

func (Op M2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (M2r) Op_instruction_verilog_extra_block 

func (Op M2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (M2r) Op_instruction_verilog_extra_modules 

func (Op M2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op M2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (M2r) Op_instruction_verilog_internal_state 

func (Op M2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (M2r) Op_instruction_verilog_reset 

func (Op M2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (M2r) Op_instruction_verilog_state_machine 

func (op M2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (M2r) Op_show_assembler 

func (op M2r) Op_show_assembler(arch *Arch) string

func (M2r) Required_modes 

func (op M2r) Required_modes() (bool, []string)

func (M2r) Required_shared 

func (op M2r) Required_shared() (bool, []string)

func (M2r) Simulate 

func (op M2r) Simulate(vm *VM, instr string) error

type M2rri 

type M2rri struct{}

func (M2rri) AbstractAssembler 

func (Op M2rri) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (M2rri) Assembler 

func (op M2rri) Assembler(arch *Arch, words []string) (string, error)

func (M2rri) Disassembler 

func (op M2rri) Disassembler(arch *Arch, instr string) (string, error)

func (M2rri) ExtraFiles 

func (Op M2rri) ExtraFiles(arch *Arch) ([]string, []string)

func (M2rri) Forbidden_modes 

func (op M2rri) Forbidden_modes() (bool, []string)

func (M2rri) Generate 

func (op M2rri) Generate(arch *Arch) string

func (M2rri) HLAssemblerInstructionMetadata 

func (Op M2rri) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (M2rri) HLAssemblerMatch 

func (Op M2rri) HLAssemblerMatch(arch *Arch) []string

func (M2rri) HLAssemblerNormalize 

func (Op M2rri) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (M2rri) OpInstructionVerilogHeader 

func (op M2rri) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (M2rri) Op_get_desc 

func (op M2rri) Op_get_desc() string

func (M2rri) Op_get_instruction_len 

func (op M2rri) Op_get_instruction_len(arch *Arch) int

func (M2rri) Op_get_name 

func (op M2rri) Op_get_name() string

func (M2rri) Op_instruction_verilog_default_state 

func (Op M2rri) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (M2rri) Op_instruction_verilog_extra_block 

func (Op M2rri) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (M2rri) Op_instruction_verilog_extra_modules 

func (Op M2rri) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op M2rri) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (M2rri) Op_instruction_verilog_internal_state 

func (Op M2rri) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (M2rri) Op_instruction_verilog_reset 

func (Op M2rri) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (M2rri) Op_instruction_verilog_state_machine 

func (op M2rri) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (M2rri) Op_show_assembler 

func (op M2rri) Op_show_assembler(arch *Arch) string

func (M2rri) Required_modes 

func (op M2rri) Required_modes() (bool, []string)

func (M2rri) Required_shared 

func (op M2rri) Required_shared() (bool, []string)

func (M2rri) Simulate 

func (op M2rri) Simulate(vm *VM, instr string) error

type Machine 

type Machine struct {
	Arch
	Program
	Data
}

The machine is an architecture provided with and execution code and an intial state

func (*Machine) ConstraintCheck 

func (mach *Machine) ConstraintCheck() (string, bool)

func (*Machine) Descr 

func (mach *Machine) Descr() string

func (*Machine) Disassembler 

func (mach *Machine) Disassembler() (string, error)

func (*Machine) Instructions_alias 

func (mach *Machine) Instructions_alias() (string, error)

func (*Machine) Jsoner 

func (mach *Machine) Jsoner() *Machine_json

func (*Machine) MelCopy 

func (mach *Machine) MelCopy() mel.Me3li

func (*Machine) MelInit 

func (mach *Machine) MelInit(c *mel.MelConfig, ep *mel.EvolutionParameters)

func (*Machine) Program_alias 

func (mach *Machine) Program_alias() (string, error)

func (*Machine) Specs 

func (mach *Machine) Specs() string

func (*Machine) String 

func (mach *Machine) String() string

type Machine_json 

type Machine_json struct {
	Modes              []string
	Rsize              uint8
	WordSize           uint8
	R                  uint8 // Number of n-bit registers
	N                  uint8 // Number of n-bit inputs
	M                  uint8 // Number of n-bit outputs
	L                  uint8 // Number of n-bit memory banks internal to the processor 2^
	O                  uint8 // Number of ROM cells 2^
	Shared_constraints string
	Op                 []string
	Slocs              []string
	Vars               []string
}

func (*Machine_json) Dejsoner 

func (machj *Machine_json) Dejsoner() *Machine

type Mod 

type Mod struct{}

The Mod opcode is both a basic instruction and a template for other instructions.

func (Mod) AbstractAssembler 

func (Op Mod) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Mod) Assembler 

func (op Mod) Assembler(arch *Arch, words []string) (string, error)

func (Mod) Disassembler 

func (op Mod) Disassembler(arch *Arch, instr string) (string, error)

func (Mod) ExtraFiles 

func (Op Mod) ExtraFiles(arch *Arch) ([]string, []string)

func (Mod) Forbidden_modes 

func (op Mod) Forbidden_modes() (bool, []string)

func (Mod) Generate 

func (op Mod) Generate(arch *Arch) string

The random genaration does nothing

func (Mod) HLAssemblerInstructionMetadata 

func (Op Mod) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Mod) HLAssemblerMatch 

func (Op Mod) HLAssemblerMatch(arch *Arch) []string

func (Mod) HLAssemblerNormalize 

func (Op Mod) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Mod) OpInstructionVerilogHeader 

func (op Mod) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Mod) Op_get_desc 

func (op Mod) Op_get_desc() string

func (Mod) Op_get_instruction_len 

func (op Mod) Op_get_instruction_len(arch *Arch) int

func (Mod) Op_get_name 

func (op Mod) Op_get_name() string

func (Mod) Op_instruction_internal_state 

func (op Mod) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Mod) Op_instruction_verilog_default_state 

func (Op Mod) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Mod) Op_instruction_verilog_extra_block 

func (Op Mod) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Mod) Op_instruction_verilog_extra_modules 

func (Op Mod) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Mod) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Mod) Op_instruction_verilog_internal_state 

func (Op Mod) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Mod) Op_instruction_verilog_reset 

func (Op Mod) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Mod) Op_instruction_verilog_state_machine 

func (op Mod) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Mod) Op_show_assembler 

func (op Mod) Op_show_assembler(arch *Arch) string

func (Mod) Required_modes 

func (op Mod) Required_modes() (bool, []string)

func (Mod) Required_shared 

func (op Mod) Required_shared() (bool, []string)

func (Mod) Simulate 

func (op Mod) Simulate(vm *VM, instr string) error

The simulation does nothing

type Mulc 

type Mulc struct{}

The Mulc opcode is both a basic instruction and a template for other instructions.

func (Mulc) AbstractAssembler 

func (Op Mulc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Mulc) Assembler 

func (op Mulc) Assembler(arch *Arch, words []string) (string, error)

func (Mulc) Disassembler 

func (op Mulc) Disassembler(arch *Arch, instr string) (string, error)

func (Mulc) ExtraFiles 

func (Op Mulc) ExtraFiles(arch *Arch) ([]string, []string)

func (Mulc) Forbidden_modes 

func (op Mulc) Forbidden_modes() (bool, []string)

func (Mulc) Generate 

func (op Mulc) Generate(arch *Arch) string

The random genaration does nothing

func (Mulc) HLAssemblerInstructionMetadata 

func (Op Mulc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Mulc) HLAssemblerMatch 

func (Op Mulc) HLAssemblerMatch(arch *Arch) []string

func (Mulc) HLAssemblerNormalize 

func (Op Mulc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Mulc) OpInstructionVerilogHeader 

func (op Mulc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Mulc) Op_get_desc 

func (op Mulc) Op_get_desc() string

func (Mulc) Op_get_instruction_len 

func (op Mulc) Op_get_instruction_len(arch *Arch) int

func (Mulc) Op_get_name 

func (op Mulc) Op_get_name() string

func (Mulc) Op_instruction_internal_state 

func (op Mulc) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Mulc) Op_instruction_verilog_default_state 

func (Op Mulc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Mulc) Op_instruction_verilog_extra_block 

func (Op Mulc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Mulc) Op_instruction_verilog_extra_modules 

func (Op Mulc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Mulc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Mulc) Op_instruction_verilog_internal_state 

func (Op Mulc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Mulc) Op_instruction_verilog_reset 

func (Op Mulc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Mulc) Op_instruction_verilog_state_machine 

func (op Mulc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Mulc) Op_show_assembler 

func (op Mulc) Op_show_assembler(arch *Arch) string

func (Mulc) Required_modes 

func (op Mulc) Required_modes() (bool, []string)

func (Mulc) Required_shared 

func (op Mulc) Required_shared() (bool, []string)

func (Mulc) Simulate 

func (op Mulc) Simulate(vm *VM, instr string) error

The simulation does nothing

type Mult 

type Mult struct{}

The Mult opcode is both a basic instruction and a template for other instructions.

func (Mult) AbstractAssembler 

func (Op Mult) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Mult) Assembler 

func (op Mult) Assembler(arch *Arch, words []string) (string, error)

func (Mult) Disassembler 

func (op Mult) Disassembler(arch *Arch, instr string) (string, error)

func (Mult) ExtraFiles 

func (Op Mult) ExtraFiles(arch *Arch) ([]string, []string)

func (Mult) Forbidden_modes 

func (op Mult) Forbidden_modes() (bool, []string)

func (Mult) Generate 

func (op Mult) Generate(arch *Arch) string

The random genaration does nothing

func (Mult) HLAssemblerInstructionMetadata 

func (Op Mult) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Mult) HLAssemblerMatch 

func (Op Mult) HLAssemblerMatch(arch *Arch) []string

func (Mult) HLAssemblerNormalize 

func (Op Mult) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Mult) OpInstructionVerilogHeader 

func (op Mult) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Mult) Op_get_desc 

func (op Mult) Op_get_desc() string

func (Mult) Op_get_instruction_len 

func (op Mult) Op_get_instruction_len(arch *Arch) int

func (Mult) Op_get_name 

func (op Mult) Op_get_name() string

func (Mult) Op_instruction_internal_state 

func (op Mult) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Mult) Op_instruction_verilog_default_state 

func (Op Mult) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Mult) Op_instruction_verilog_extra_block 

func (Op Mult) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Mult) Op_instruction_verilog_extra_modules 

func (Op Mult) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Mult) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Mult) Op_instruction_verilog_internal_state 

func (Op Mult) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Mult) Op_instruction_verilog_reset 

func (Op Mult) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Mult) Op_instruction_verilog_state_machine 

func (op Mult) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Mult) Op_show_assembler 

func (op Mult) Op_show_assembler(arch *Arch) string

func (Mult) Required_modes 

func (op Mult) Required_modes() (bool, []string)

func (Mult) Required_shared 

func (op Mult) Required_shared() (bool, []string)

func (Mult) Simulate 

func (op Mult) Simulate(vm *VM, instr string) error

The simulation does nothing

type Multf 

type Multf struct{}

func (Multf) AbstractAssembler 

func (Op Multf) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Multf) Assembler 

func (op Multf) Assembler(arch *Arch, words []string) (string, error)

func (Multf) Disassembler 

func (op Multf) Disassembler(arch *Arch, instr string) (string, error)

func (Multf) ExtraFiles 

func (Op Multf) ExtraFiles(arch *Arch) ([]string, []string)

func (Multf) Forbidden_modes 

func (op Multf) Forbidden_modes() (bool, []string)

func (Multf) Generate 

func (op Multf) Generate(arch *Arch) string

The random genaration does nothing

func (Multf) HLAssemblerInstructionMetadata 

func (Op Multf) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Multf) HLAssemblerMatch 

func (Op Multf) HLAssemblerMatch(arch *Arch) []string

func (Multf) HLAssemblerNormalize 

func (Op Multf) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Multf) OpInstructionVerilogHeader 

func (op Multf) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Multf) Op_get_desc 

func (op Multf) Op_get_desc() string

func (Multf) Op_get_instruction_len 

func (op Multf) Op_get_instruction_len(arch *Arch) int

func (Multf) Op_get_name 

func (op Multf) Op_get_name() string

func (Multf) Op_instruction_internal_state 

func (op Multf) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Multf) Op_instruction_verilog_default_state 

func (Op Multf) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Multf) Op_instruction_verilog_extra_block 

func (Op Multf) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Multf) Op_instruction_verilog_extra_modules 

func (Op Multf) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Multf) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Multf) Op_instruction_verilog_internal_state 

func (Op Multf) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Multf) Op_instruction_verilog_reset 

func (Op Multf) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Multf) Op_instruction_verilog_state_machine 

func (op Multf) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Multf) Op_show_assembler 

func (op Multf) Op_show_assembler(arch *Arch) string

func (Multf) Required_modes 

func (op Multf) Required_modes() (bool, []string)

func (Multf) Required_shared 

func (op Multf) Required_shared() (bool, []string)

func (Multf) Simulate 

func (op Multf) Simulate(vm *VM, instr string) error

type Multf16 

type Multf16 struct{}

func (Multf16) AbstractAssembler 

func (Op Multf16) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Multf16) Assembler 

func (op Multf16) Assembler(arch *Arch, words []string) (string, error)

func (Multf16) Disassembler 

func (op Multf16) Disassembler(arch *Arch, instr string) (string, error)

func (Multf16) ExtraFiles 

func (Op Multf16) ExtraFiles(arch *Arch) ([]string, []string)

func (Multf16) Forbidden_modes 

func (op Multf16) Forbidden_modes() (bool, []string)

func (Multf16) Generate 

func (op Multf16) Generate(arch *Arch) string

The random genaration does nothing

func (Multf16) HLAssemblerInstructionMetadata 

func (Op Multf16) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Multf16) HLAssemblerMatch 

func (Op Multf16) HLAssemblerMatch(arch *Arch) []string

func (Multf16) HLAssemblerNormalize 

func (Op Multf16) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Multf16) OpInstructionVerilogHeader 

func (op Multf16) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Multf16) Op_get_desc 

func (op Multf16) Op_get_desc() string

func (Multf16) Op_get_instruction_len 

func (op Multf16) Op_get_instruction_len(arch *Arch) int

func (Multf16) Op_get_name 

func (op Multf16) Op_get_name() string

func (Multf16) Op_instruction_internal_state 

func (op Multf16) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Multf16) Op_instruction_verilog_default_state 

func (Op Multf16) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Multf16) Op_instruction_verilog_extra_block 

func (Op Multf16) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Multf16) Op_instruction_verilog_extra_modules 

func (Op Multf16) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Multf16) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Multf16) Op_instruction_verilog_internal_state 

func (Op Multf16) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Multf16) Op_instruction_verilog_reset 

func (Op Multf16) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Multf16) Op_instruction_verilog_state_machine 

func (op Multf16) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Multf16) Op_show_assembler 

func (op Multf16) Op_show_assembler(arch *Arch) string

func (Multf16) Required_modes 

func (op Multf16) Required_modes() (bool, []string)

func (Multf16) Required_shared 

func (op Multf16) Required_shared() (bool, []string)

func (Multf16) Simulate 

func (op Multf16) Simulate(vm *VM, instr string) error

type Multp 

type Multp struct {
	// contains filtered or unexported fields
}

func (Multp) AbstractAssembler 

func (Op Multp) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Multp) Assembler 

func (op Multp) Assembler(arch *Arch, words []string) (string, error)

func (Multp) Disassembler 

func (op Multp) Disassembler(arch *Arch, instr string) (string, error)

func (Multp) ExtraFiles 

func (Op Multp) ExtraFiles(arch *Arch) ([]string, []string)

func (Multp) Forbidden_modes 

func (op Multp) Forbidden_modes() (bool, []string)

func (Multp) Generate 

func (op Multp) Generate(arch *Arch) string

The random genaration does nothing

func (Multp) HLAssemblerInstructionMetadata 

func (Op Multp) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Multp) HLAssemblerMatch 

func (Op Multp) HLAssemblerMatch(arch *Arch) []string

func (Multp) HLAssemblerNormalize 

func (Op Multp) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Multp) OpInstructionVerilogHeader 

func (op Multp) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Multp) Op_get_desc 

func (op Multp) Op_get_desc() string

func (Multp) Op_get_instruction_len 

func (op Multp) Op_get_instruction_len(arch *Arch) int

func (Multp) Op_get_name 

func (op Multp) Op_get_name() string

func (Multp) Op_instruction_internal_state 

func (op Multp) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Multp) Op_instruction_verilog_default_state 

func (Op Multp) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Multp) Op_instruction_verilog_extra_block 

func (Op Multp) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Multp) Op_instruction_verilog_extra_modules 

func (Op Multp) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Multp) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Multp) Op_instruction_verilog_internal_state 

func (Op Multp) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Multp) Op_instruction_verilog_reset 

func (Op Multp) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Multp) Op_instruction_verilog_state_machine 

func (op Multp) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Multp) Op_show_assembler 

func (op Multp) Op_show_assembler(arch *Arch) string

func (Multp) Required_modes 

func (op Multp) Required_modes() (bool, []string)

func (Multp) Required_shared 

func (op Multp) Required_shared() (bool, []string)

func (Multp) Simulate 

func (op Multp) Simulate(vm *VM, instr string) error

type Nand 

type Nand struct{}

The Nand opcode is both a basic instruction and a template for other instructions.

func (Nand) AbstractAssembler 

func (Op Nand) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Nand) Assembler 

func (op Nand) Assembler(arch *Arch, words []string) (string, error)

func (Nand) Disassembler 

func (op Nand) Disassembler(arch *Arch, instr string) (string, error)

func (Nand) ExtraFiles 

func (Op Nand) ExtraFiles(arch *Arch) ([]string, []string)

func (Nand) Forbidden_modes 

func (op Nand) Forbidden_modes() (bool, []string)

func (Nand) Generate 

func (op Nand) Generate(arch *Arch) string

The random genaration does nothing

func (Nand) HLAssemblerInstructionMetadata 

func (Op Nand) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Nand) HLAssemblerMatch 

func (Op Nand) HLAssemblerMatch(arch *Arch) []string

func (Nand) HLAssemblerNormalize 

func (Op Nand) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Nand) OpInstructionVerilogHeader 

func (op Nand) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Nand) Op_get_desc 

func (op Nand) Op_get_desc() string

func (Nand) Op_get_instruction_len 

func (op Nand) Op_get_instruction_len(arch *Arch) int

func (Nand) Op_get_name 

func (op Nand) Op_get_name() string

func (Nand) Op_instruction_internal_state 

func (op Nand) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Nand) Op_instruction_verilog_default_state 

func (Op Nand) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Nand) Op_instruction_verilog_extra_block 

func (Op Nand) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Nand) Op_instruction_verilog_extra_modules 

func (Op Nand) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Nand) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Nand) Op_instruction_verilog_internal_state 

func (Op Nand) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Nand) Op_instruction_verilog_reset 

func (Op Nand) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Nand) Op_instruction_verilog_state_machine 

func (op Nand) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Nand) Op_show_assembler 

func (op Nand) Op_show_assembler(arch *Arch) string

func (Nand) Required_modes 

func (op Nand) Required_modes() (bool, []string)

func (Nand) Required_shared 

func (op Nand) Required_shared() (bool, []string)

func (Nand) Simulate 

func (op Nand) Simulate(vm *VM, instr string) error

The simulation does nothing

type Nop 

type Nop struct{}

The Nop opcode is both a basic instruction and a template for other instructions.

func (Nop) AbstractAssembler 

func (Op Nop) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Nop) Assembler 

func (op Nop) Assembler(arch *Arch, words []string) (string, error)

func (Nop) Disassembler 

func (op Nop) Disassembler(arch *Arch, instr string) (string, error)

func (Nop) ExtraFiles 

func (Op Nop) ExtraFiles(arch *Arch) ([]string, []string)

func (Nop) Forbidden_modes 

func (op Nop) Forbidden_modes() (bool, []string)

func (Nop) Generate 

func (op Nop) Generate(arch *Arch) string

The random genaration does nothing

func (Nop) HLAssemblerInstructionMetadata 

func (Op Nop) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Nop) HLAssemblerMatch 

func (Op Nop) HLAssemblerMatch(arch *Arch) []string

func (Nop) HLAssemblerNormalize 

func (Op Nop) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Nop) OpInstructionVerilogHeader 

func (op Nop) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Nop) Op_get_desc 

func (op Nop) Op_get_desc() string

func (Nop) Op_get_instruction_len 

func (op Nop) Op_get_instruction_len(arch *Arch) int

func (Nop) Op_get_name 

func (op Nop) Op_get_name() string

func (Nop) Op_instruction_verilog_default_state 

func (Op Nop) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Nop) Op_instruction_verilog_extra_block 

func (Op Nop) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Nop) Op_instruction_verilog_extra_modules 

func (Op Nop) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Nop) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Nop) Op_instruction_verilog_internal_state 

func (Op Nop) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Nop) Op_instruction_verilog_reset 

func (Op Nop) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Nop) Op_instruction_verilog_state_machine 

func (op Nop) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Nop) Op_show_assembler 

func (op Nop) Op_show_assembler(arch *Arch) string

func (Nop) Required_modes 

func (op Nop) Required_modes() (bool, []string)

func (Nop) Required_shared 

func (op Nop) Required_shared() (bool, []string)

func (Nop) Simulate 

func (op Nop) Simulate(vm *VM, instr string) error

The simulation does nothing

type Nor 

type Nor struct{}

The And opcode is both a basic instruction and a template for other instructions.

func (Nor) AbstractAssembler 

func (Op Nor) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Nor) Assembler 

func (op Nor) Assembler(arch *Arch, words []string) (string, error)

func (Nor) Disassembler 

func (op Nor) Disassembler(arch *Arch, instr string) (string, error)

func (Nor) ExtraFiles 

func (Op Nor) ExtraFiles(arch *Arch) ([]string, []string)

func (Nor) Forbidden_modes 

func (op Nor) Forbidden_modes() (bool, []string)

func (Nor) Generate 

func (op Nor) Generate(arch *Arch) string

The random genaration does nothing

func (Nor) HLAssemblerInstructionMetadata 

func (Op Nor) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Nor) HLAssemblerMatch 

func (Op Nor) HLAssemblerMatch(arch *Arch) []string

func (Nor) HLAssemblerNormalize 

func (Op Nor) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Nor) OpInstructionVerilogHeader 

func (op Nor) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Nor) Op_get_desc 

func (op Nor) Op_get_desc() string

func (Nor) Op_get_instruction_len 

func (op Nor) Op_get_instruction_len(arch *Arch) int

func (Nor) Op_get_name 

func (op Nor) Op_get_name() string

func (Nor) Op_instruction_internal_state 

func (op Nor) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Nor) Op_instruction_verilog_default_state 

func (Op Nor) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Nor) Op_instruction_verilog_extra_block 

func (Op Nor) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Nor) Op_instruction_verilog_extra_modules 

func (Op Nor) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Nor) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Nor) Op_instruction_verilog_internal_state 

func (Op Nor) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Nor) Op_instruction_verilog_reset 

func (Op Nor) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Nor) Op_instruction_verilog_state_machine 

func (op Nor) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Nor) Op_show_assembler 

func (op Nor) Op_show_assembler(arch *Arch) string

func (Nor) Required_modes 

func (op Nor) Required_modes() (bool, []string)

func (Nor) Required_shared 

func (op Nor) Required_shared() (bool, []string)

func (Nor) Simulate 

func (op Nor) Simulate(vm *VM, instr string) error

The simulation does nothing

type Not 

type Not struct{}

The And opcode is both a basic instruction and a template for other instructions.

func (Not) AbstractAssembler 

func (Op Not) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Not) Assembler 

func (op Not) Assembler(arch *Arch, words []string) (string, error)

func (Not) Disassembler 

func (op Not) Disassembler(arch *Arch, instr string) (string, error)

func (Not) ExtraFiles 

func (Op Not) ExtraFiles(arch *Arch) ([]string, []string)

func (Not) Forbidden_modes 

func (op Not) Forbidden_modes() (bool, []string)

func (Not) Generate 

func (op Not) Generate(arch *Arch) string

The random genaration does nothing

func (Not) HLAssemblerInstructionMetadata 

func (Op Not) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Not) HLAssemblerMatch 

func (Op Not) HLAssemblerMatch(arch *Arch) []string

func (Not) HLAssemblerNormalize 

func (Op Not) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Not) OpInstructionVerilogHeader 

func (op Not) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Not) Op_get_desc 

func (op Not) Op_get_desc() string

func (Not) Op_get_instruction_len 

func (op Not) Op_get_instruction_len(arch *Arch) int

func (Not) Op_get_name 

func (op Not) Op_get_name() string

func (Not) Op_instruction_internal_state 

func (op Not) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Not) Op_instruction_verilog_default_state 

func (Op Not) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Not) Op_instruction_verilog_extra_block 

func (Op Not) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Not) Op_instruction_verilog_extra_modules 

func (Op Not) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Not) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Not) Op_instruction_verilog_internal_state 

func (Op Not) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Not) Op_instruction_verilog_reset 

func (Op Not) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Not) Op_instruction_verilog_state_machine 

func (op Not) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Not) Op_show_assembler 

func (op Not) Op_show_assembler(arch *Arch) string

func (Not) Required_modes 

func (op Not) Required_modes() (bool, []string)

func (Not) Required_shared 

func (op Not) Required_shared() (bool, []string)

func (Not) Simulate 

func (op Not) Simulate(vm *VM, instr string) error

The simulation does nothing

type Opcode 

type Opcode interface {
	Op_get_name() string
	Op_get_desc() string
	Op_show_assembler(*Arch) string
	Op_get_instruction_len(*Arch) int
	OpInstructionVerilogHeader(*Config, *Arch, string, string) string
	Op_instruction_verilog_reset(*Arch, string) string
	Op_instruction_verilog_internal_state(*Arch, string) string
	Op_instruction_verilog_default_state(*Arch, string) string
	Op_instruction_verilog_state_machine(*Config, *Arch, *bmreqs.ReqRoot, string) string
	Op_instruction_verilog_footer(*Arch, string) string
	Op_instruction_verilog_extra_modules(*Arch, string) ([]string, []string)
	Op_instruction_verilog_extra_block(*Arch, string, uint8, string, []string) string
	AbstractAssembler(*Arch, []string) ([]UsageNotify, error)
	Assembler(*Arch, []string) (string, error)
	HLAssemblerMatch(*Arch) []string
	HLAssemblerNormalize(*Arch, *bmreqs.ReqRoot, string, *bmline.BasmLine) (*bmline.BasmLine, error)
	HLAssemblerInstructionMetadata(*Arch, *bmline.BasmLine) (*bmmeta.BasmMeta, error)
	Disassembler(*Arch, string) (string, error)
	Simulate(*VM, string) error
	Generate(*Arch) string
	Required_shared() (bool, []string)
	Required_modes() (bool, []string)
	Forbidden_modes() (bool, []string)
	ExtraFiles(arch *Arch) ([]string, []string)
}

type Or 

type Or struct{}

The And opcode is both a basic instruction and a template for other instructions.

func (Or) AbstractAssembler 

func (Op Or) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Or) Assembler 

func (op Or) Assembler(arch *Arch, words []string) (string, error)

func (Or) Disassembler 

func (op Or) Disassembler(arch *Arch, instr string) (string, error)

func (Or) ExtraFiles 

func (Op Or) ExtraFiles(arch *Arch) ([]string, []string)

func (Or) Forbidden_modes 

func (op Or) Forbidden_modes() (bool, []string)

func (Or) Generate 

func (op Or) Generate(arch *Arch) string

The random genaration does nothing

func (Or) HLAssemblerInstructionMetadata 

func (Op Or) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Or) HLAssemblerMatch 

func (Op Or) HLAssemblerMatch(arch *Arch) []string

func (Or) HLAssemblerNormalize 

func (Op Or) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Or) OpInstructionVerilogHeader 

func (op Or) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Or) Op_get_desc 

func (op Or) Op_get_desc() string

func (Or) Op_get_instruction_len 

func (op Or) Op_get_instruction_len(arch *Arch) int

func (Or) Op_get_name 

func (op Or) Op_get_name() string

func (Or) Op_instruction_internal_state 

func (op Or) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Or) Op_instruction_verilog_default_state 

func (Op Or) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Or) Op_instruction_verilog_extra_block 

func (Op Or) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Or) Op_instruction_verilog_extra_modules 

func (Op Or) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Or) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Or) Op_instruction_verilog_internal_state 

func (Op Or) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Or) Op_instruction_verilog_reset 

func (Op Or) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Or) Op_instruction_verilog_state_machine 

func (op Or) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Or) Op_show_assembler 

func (op Or) Op_show_assembler(arch *Arch) string

func (Or) Required_modes 

func (op Or) Required_modes() (bool, []string)

func (Or) Required_shared 

func (op Or) Required_shared() (bool, []string)

func (Or) Simulate 

func (op Or) Simulate(vm *VM, instr string) error

The simulation does nothing

type Prerror 

type Prerror struct {
	// contains filtered or unexported fields
}

func (Prerror) Error 

func (e Prerror) Error() string

type Program 

type Program struct {
	Slocs []string
}

The machine is an architecture provided with and execution code and an intial state

func (*Program) String 

func (prog *Program) String() string

type Q2r 

type Q2r struct{}

The Q2r opcode

func (Q2r) AbstractAssembler 

func (Op Q2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Q2r) Assembler 

func (op Q2r) Assembler(arch *Arch, words []string) (string, error)

func (Q2r) Disassembler 

func (op Q2r) Disassembler(arch *Arch, instr string) (string, error)

func (Q2r) ExtraFiles 

func (Op Q2r) ExtraFiles(arch *Arch) ([]string, []string)

func (Q2r) Forbidden_modes 

func (op Q2r) Forbidden_modes() (bool, []string)

func (Q2r) Generate 

func (op Q2r) Generate(arch *Arch) string

The random genaration does nothing

func (Q2r) HLAssemblerInstructionMetadata 

func (Op Q2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Q2r) HLAssemblerMatch 

func (Op Q2r) HLAssemblerMatch(arch *Arch) []string

func (Q2r) HLAssemblerNormalize 

func (Op Q2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Q2r) OpInstructionVerilogHeader 

func (op Q2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (Q2r) Op_get_desc 

func (op Q2r) Op_get_desc() string

func (Q2r) Op_get_instruction_len 

func (op Q2r) Op_get_instruction_len(arch *Arch) int

func (Q2r) Op_get_name 

func (op Q2r) Op_get_name() string

func (Q2r) Op_instruction_verilog_default_state 

func (Op Q2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Q2r) Op_instruction_verilog_extra_block 

func (Op Q2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Q2r) Op_instruction_verilog_extra_modules 

func (Op Q2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Q2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Q2r) Op_instruction_verilog_internal_state 

func (Op Q2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Q2r) Op_instruction_verilog_reset 

func (Op Q2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Q2r) Op_instruction_verilog_state_machine 

func (op Q2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Q2r) Op_show_assembler 

func (op Q2r) Op_show_assembler(arch *Arch) string

func (Q2r) Required_modes 

func (op Q2r) Required_modes() (bool, []string)

func (Q2r) Required_shared 

func (op Q2r) Required_shared() (bool, []string)

func (Q2r) Simulate 

func (op Q2r) Simulate(vm *VM, instr string) error

The simulation does nothing

type Queue 

type Queue struct{}

func (Queue) GetArchHeader 

func (op Queue) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Queue) GetArchParams 

func (op Queue) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Queue) GetCPParams 

func (op Queue) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Queue) Shortname 

func (op Queue) Shortname() string

func (Queue) Shr_get_name 

func (op Queue) Shr_get_name() string

type R2m 

type R2m struct{}

func (R2m) AbstractAssembler 

func (Op R2m) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2m) Assembler 

func (op R2m) Assembler(arch *Arch, words []string) (string, error)

func (R2m) Disassembler 

func (op R2m) Disassembler(arch *Arch, instr string) (string, error)

func (R2m) ExtraFiles 

func (Op R2m) ExtraFiles(arch *Arch) ([]string, []string)

func (R2m) Forbidden_modes 

func (op R2m) Forbidden_modes() (bool, []string)

func (R2m) Generate 

func (op R2m) Generate(arch *Arch) string

The random genaration does nothing

func (R2m) HLAssemblerInstructionMetadata 

func (Op R2m) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2m) HLAssemblerMatch 

func (Op R2m) HLAssemblerMatch(arch *Arch) []string

func (R2m) HLAssemblerNormalize 

func (Op R2m) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2m) OpInstructionVerilogHeader 

func (op R2m) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2m) Op_get_desc 

func (op R2m) Op_get_desc() string

func (R2m) Op_get_instruction_len 

func (op R2m) Op_get_instruction_len(arch *Arch) int

func (R2m) Op_get_name 

func (op R2m) Op_get_name() string

func (R2m) Op_instruction_verilog_default_state 

func (Op R2m) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2m) Op_instruction_verilog_extra_block 

func (Op R2m) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2m) Op_instruction_verilog_extra_modules 

func (Op R2m) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2m) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2m) Op_instruction_verilog_internal_state 

func (Op R2m) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2m) Op_instruction_verilog_reset 

func (Op R2m) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2m) Op_instruction_verilog_state_machine 

func (op R2m) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2m) Op_show_assembler 

func (op R2m) Op_show_assembler(arch *Arch) string

func (R2m) Required_modes 

func (op R2m) Required_modes() (bool, []string)

func (R2m) Required_shared 

func (op R2m) Required_shared() (bool, []string)

func (R2m) Simulate 

func (op R2m) Simulate(vm *VM, instr string) error

The simulation does nothing

type R2mri 

type R2mri struct{}

The R2mri opcode is both a basic instruction and a template for other instructions.

func (R2mri) AbstractAssembler 

func (Op R2mri) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2mri) Assembler 

func (op R2mri) Assembler(arch *Arch, words []string) (string, error)

func (R2mri) Disassembler 

func (op R2mri) Disassembler(arch *Arch, instr string) (string, error)

func (R2mri) ExtraFiles 

func (Op R2mri) ExtraFiles(arch *Arch) ([]string, []string)

func (R2mri) Forbidden_modes 

func (op R2mri) Forbidden_modes() (bool, []string)

func (R2mri) Generate 

func (op R2mri) Generate(arch *Arch) string

The random genaration does nothing

func (R2mri) HLAssemblerInstructionMetadata 

func (Op R2mri) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2mri) HLAssemblerMatch 

func (Op R2mri) HLAssemblerMatch(arch *Arch) []string

func (R2mri) HLAssemblerNormalize 

func (Op R2mri) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2mri) OpInstructionVerilogHeader 

func (op R2mri) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2mri) Op_get_desc 

func (op R2mri) Op_get_desc() string

func (R2mri) Op_get_instruction_len 

func (op R2mri) Op_get_instruction_len(arch *Arch) int

func (R2mri) Op_get_name 

func (op R2mri) Op_get_name() string

func (R2mri) Op_instruction_verilog_default_state 

func (Op R2mri) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2mri) Op_instruction_verilog_extra_block 

func (Op R2mri) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2mri) Op_instruction_verilog_extra_modules 

func (Op R2mri) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2mri) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2mri) Op_instruction_verilog_internal_state 

func (Op R2mri) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2mri) Op_instruction_verilog_reset 

func (Op R2mri) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2mri) Op_instruction_verilog_state_machine 

func (op R2mri) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2mri) Op_show_assembler 

func (op R2mri) Op_show_assembler(arch *Arch) string

func (R2mri) Required_modes 

func (op R2mri) Required_modes() (bool, []string)

func (R2mri) Required_shared 

func (op R2mri) Required_shared() (bool, []string)

func (R2mri) Simulate 

func (op R2mri) Simulate(vm *VM, instr string) error

The simulation does nothing

type R2o 

type R2o struct{}

func (R2o) AbstractAssembler 

func (Op R2o) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2o) Assembler 

func (op R2o) Assembler(arch *Arch, words []string) (string, error)

func (R2o) Disassembler 

func (op R2o) Disassembler(arch *Arch, instr string) (string, error)

func (R2o) ExtraFiles 

func (Op R2o) ExtraFiles(arch *Arch) ([]string, []string)

func (R2o) Forbidden_modes 

func (op R2o) Forbidden_modes() (bool, []string)

func (R2o) Generate 

func (op R2o) Generate(arch *Arch) string

func (R2o) HLAssemblerInstructionMetadata 

func (Op R2o) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2o) HLAssemblerMatch 

func (Op R2o) HLAssemblerMatch(arch *Arch) []string

func (R2o) HLAssemblerNormalize 

func (Op R2o) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2o) OpInstructionVerilogHeader 

func (op R2o) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2o) Op_get_desc 

func (op R2o) Op_get_desc() string

func (R2o) Op_get_instruction_len 

func (op R2o) Op_get_instruction_len(arch *Arch) int

func (R2o) Op_get_name 

func (op R2o) Op_get_name() string

func (R2o) Op_instruction_internal_state 

func (op R2o) Op_instruction_internal_state(arch *Arch, flavor string) string

func (R2o) Op_instruction_verilog_default_state 

func (Op R2o) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2o) Op_instruction_verilog_extra_block 

func (Op R2o) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2o) Op_instruction_verilog_extra_modules 

func (Op R2o) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2o) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2o) Op_instruction_verilog_internal_state 

func (Op R2o) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2o) Op_instruction_verilog_reset 

func (Op R2o) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2o) Op_instruction_verilog_state_machine 

func (op R2o) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2o) Op_show_assembler 

func (op R2o) Op_show_assembler(arch *Arch) string

func (R2o) Required_modes 

func (op R2o) Required_modes() (bool, []string)

func (R2o) Required_shared 

func (op R2o) Required_shared() (bool, []string)

func (R2o) Simulate 

func (op R2o) Simulate(vm *VM, instr string) error

type R2owa 

type R2owa struct{}

func (R2owa) AbstractAssembler 

func (Op R2owa) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2owa) Assembler 

func (op R2owa) Assembler(arch *Arch, words []string) (string, error)

func (R2owa) Disassembler 

func (op R2owa) Disassembler(arch *Arch, instr string) (string, error)

func (R2owa) ExtraFiles 

func (Op R2owa) ExtraFiles(arch *Arch) ([]string, []string)

func (R2owa) Forbidden_modes 

func (op R2owa) Forbidden_modes() (bool, []string)

func (R2owa) Generate 

func (op R2owa) Generate(arch *Arch) string

func (R2owa) HLAssemblerInstructionMetadata 

func (Op R2owa) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2owa) HLAssemblerMatch 

func (Op R2owa) HLAssemblerMatch(arch *Arch) []string

func (R2owa) HLAssemblerNormalize 

func (Op R2owa) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2owa) OpInstructionVerilogHeader 

func (op R2owa) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2owa) Op_get_desc 

func (op R2owa) Op_get_desc() string

func (R2owa) Op_get_instruction_len 

func (op R2owa) Op_get_instruction_len(arch *Arch) int

func (R2owa) Op_get_name 

func (op R2owa) Op_get_name() string

func (R2owa) Op_instruction_internal_state 

func (op R2owa) Op_instruction_internal_state(arch *Arch, flavor string) string

func (R2owa) Op_instruction_verilog_default_state 

func (Op R2owa) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2owa) Op_instruction_verilog_extra_block 

func (Op R2owa) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2owa) Op_instruction_verilog_extra_modules 

func (Op R2owa) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2owa) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2owa) Op_instruction_verilog_internal_state 

func (Op R2owa) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2owa) Op_instruction_verilog_reset 

func (Op R2owa) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2owa) Op_instruction_verilog_state_machine 

func (op R2owa) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2owa) Op_show_assembler 

func (op R2owa) Op_show_assembler(arch *Arch) string

func (R2owa) Required_modes 

func (op R2owa) Required_modes() (bool, []string)

func (R2owa) Required_shared 

func (op R2owa) Required_shared() (bool, []string)

func (R2owa) Simulate 

func (op R2owa) Simulate(vm *VM, instr string) error

type R2owaa 

type R2owaa struct{}

func (R2owaa) AbstractAssembler 

func (Op R2owaa) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2owaa) Assembler 

func (op R2owaa) Assembler(arch *Arch, words []string) (string, error)

func (R2owaa) Disassembler 

func (op R2owaa) Disassembler(arch *Arch, instr string) (string, error)

func (R2owaa) ExtraFiles 

func (Op R2owaa) ExtraFiles(arch *Arch) ([]string, []string)

func (R2owaa) Forbidden_modes 

func (op R2owaa) Forbidden_modes() (bool, []string)

func (R2owaa) Generate 

func (op R2owaa) Generate(arch *Arch) string

func (R2owaa) HLAssemblerInstructionMetadata 

func (Op R2owaa) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2owaa) HLAssemblerMatch 

func (Op R2owaa) HLAssemblerMatch(arch *Arch) []string

func (R2owaa) HLAssemblerNormalize 

func (Op R2owaa) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2owaa) OpInstructionVerilogHeader 

func (op R2owaa) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2owaa) Op_get_desc 

func (op R2owaa) Op_get_desc() string

func (R2owaa) Op_get_instruction_len 

func (op R2owaa) Op_get_instruction_len(arch *Arch) int

func (R2owaa) Op_get_name 

func (op R2owaa) Op_get_name() string

func (R2owaa) Op_instruction_internal_state 

func (op R2owaa) Op_instruction_internal_state(arch *Arch, flavor string) string

func (R2owaa) Op_instruction_verilog_default_state 

func (Op R2owaa) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2owaa) Op_instruction_verilog_extra_block 

func (Op R2owaa) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2owaa) Op_instruction_verilog_extra_modules 

func (Op R2owaa) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2owaa) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2owaa) Op_instruction_verilog_internal_state 

func (Op R2owaa) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2owaa) Op_instruction_verilog_reset 

func (Op R2owaa) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2owaa) Op_instruction_verilog_state_machine 

func (op R2owaa) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2owaa) Op_show_assembler 

func (op R2owaa) Op_show_assembler(arch *Arch) string

func (R2owaa) Required_modes 

func (op R2owaa) Required_modes() (bool, []string)

func (R2owaa) Required_shared 

func (op R2owaa) Required_shared() (bool, []string)

func (R2owaa) Simulate 

func (op R2owaa) Simulate(vm *VM, instr string) error

type R2q 

type R2q struct{}

The R2q opcode

func (R2q) AbstractAssembler 

func (Op R2q) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2q) Assembler 

func (op R2q) Assembler(arch *Arch, words []string) (string, error)

func (R2q) Disassembler 

func (op R2q) Disassembler(arch *Arch, instr string) (string, error)

func (R2q) ExtraFiles 

func (Op R2q) ExtraFiles(arch *Arch) ([]string, []string)

func (R2q) Forbidden_modes 

func (op R2q) Forbidden_modes() (bool, []string)

func (R2q) Generate 

func (op R2q) Generate(arch *Arch) string

The random genaration does nothing

func (R2q) HLAssemblerInstructionMetadata 

func (Op R2q) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2q) HLAssemblerMatch 

func (Op R2q) HLAssemblerMatch(arch *Arch) []string

func (R2q) HLAssemblerNormalize 

func (Op R2q) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2q) OpInstructionVerilogHeader 

func (op R2q) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (R2q) Op_get_desc 

func (op R2q) Op_get_desc() string

func (R2q) Op_get_instruction_len 

func (op R2q) Op_get_instruction_len(arch *Arch) int

func (R2q) Op_get_name 

func (op R2q) Op_get_name() string

func (R2q) Op_instruction_verilog_default_state 

func (Op R2q) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2q) Op_instruction_verilog_extra_block 

func (Op R2q) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2q) Op_instruction_verilog_extra_modules 

func (Op R2q) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2q) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2q) Op_instruction_verilog_internal_state 

func (Op R2q) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2q) Op_instruction_verilog_reset 

func (Op R2q) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2q) Op_instruction_verilog_state_machine 

func (op R2q) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2q) Op_show_assembler 

func (op R2q) Op_show_assembler(arch *Arch) string

func (R2q) Required_modes 

func (op R2q) Required_modes() (bool, []string)

func (R2q) Required_shared 

func (op R2q) Required_shared() (bool, []string)

func (R2q) Simulate 

func (op R2q) Simulate(vm *VM, instr string) error

The simulation does nothing

type R2s 

type R2s struct{}

The R2s opcode is both a basic instruction and a template for other instructions.

func (R2s) AbstractAssembler 

func (Op R2s) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2s) Assembler 

func (op R2s) Assembler(arch *Arch, words []string) (string, error)

func (R2s) Disassembler 

func (op R2s) Disassembler(arch *Arch, instr string) (string, error)

func (R2s) ExtraFiles 

func (Op R2s) ExtraFiles(arch *Arch) ([]string, []string)

func (R2s) Forbidden_modes 

func (op R2s) Forbidden_modes() (bool, []string)

func (R2s) Generate 

func (op R2s) Generate(arch *Arch) string

The random genaration does nothing

func (R2s) HLAssemblerInstructionMetadata 

func (Op R2s) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2s) HLAssemblerMatch 

func (Op R2s) HLAssemblerMatch(arch *Arch) []string

func (R2s) HLAssemblerNormalize 

func (Op R2s) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2s) OpInstructionVerilogHeader 

func (op R2s) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2s) Op_get_desc 

func (op R2s) Op_get_desc() string

func (R2s) Op_get_instruction_len 

func (op R2s) Op_get_instruction_len(arch *Arch) int

func (R2s) Op_get_name 

func (op R2s) Op_get_name() string

func (R2s) Op_instruction_verilog_default_state 

func (Op R2s) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2s) Op_instruction_verilog_extra_block 

func (Op R2s) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2s) Op_instruction_verilog_extra_modules 

func (Op R2s) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2s) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2s) Op_instruction_verilog_internal_state 

func (Op R2s) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2s) Op_instruction_verilog_reset 

func (Op R2s) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2s) Op_instruction_verilog_state_machine 

func (op R2s) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2s) Op_show_assembler 

func (op R2s) Op_show_assembler(arch *Arch) string

func (R2s) Required_modes 

func (op R2s) Required_modes() (bool, []string)

func (R2s) Required_shared 

func (op R2s) Required_shared() (bool, []string)

func (R2s) Simulate 

func (op R2s) Simulate(vm *VM, instr string) error

The simulation does nothing

type R2t 

type R2t struct{}

The R2t opcode

func (R2t) AbstractAssembler 

func (Op R2t) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2t) Assembler 

func (op R2t) Assembler(arch *Arch, words []string) (string, error)

func (R2t) Disassembler 

func (op R2t) Disassembler(arch *Arch, instr string) (string, error)

func (R2t) ExtraFiles 

func (Op R2t) ExtraFiles(arch *Arch) ([]string, []string)

func (R2t) Forbidden_modes 

func (op R2t) Forbidden_modes() (bool, []string)

func (R2t) Generate 

func (op R2t) Generate(arch *Arch) string

The random genaration does nothing

func (R2t) HLAssemblerInstructionMetadata 

func (Op R2t) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2t) HLAssemblerMatch 

func (Op R2t) HLAssemblerMatch(arch *Arch) []string

func (R2t) HLAssemblerNormalize 

func (Op R2t) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2t) OpInstructionVerilogHeader 

func (op R2t) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (R2t) Op_get_desc 

func (op R2t) Op_get_desc() string

func (R2t) Op_get_instruction_len 

func (op R2t) Op_get_instruction_len(arch *Arch) int

func (R2t) Op_get_name 

func (op R2t) Op_get_name() string

func (R2t) Op_instruction_verilog_default_state 

func (Op R2t) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2t) Op_instruction_verilog_extra_block 

func (Op R2t) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2t) Op_instruction_verilog_extra_modules 

func (Op R2t) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2t) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2t) Op_instruction_verilog_internal_state 

func (Op R2t) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2t) Op_instruction_verilog_reset 

func (Op R2t) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2t) Op_instruction_verilog_state_machine 

func (op R2t) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2t) Op_show_assembler 

func (op R2t) Op_show_assembler(arch *Arch) string

func (R2t) Required_modes 

func (op R2t) Required_modes() (bool, []string)

func (R2t) Required_shared 

func (op R2t) Required_shared() (bool, []string)

func (R2t) Simulate 

func (op R2t) Simulate(vm *VM, instr string) error

The simulation does nothing

type R2u 

type R2u struct{}

The R2u opcode

func (R2u) AbstractAssembler 

func (Op R2u) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2u) Assembler 

func (op R2u) Assembler(arch *Arch, words []string) (string, error)

func (R2u) Disassembler 

func (op R2u) Disassembler(arch *Arch, instr string) (string, error)

func (R2u) ExtraFiles 

func (Op R2u) ExtraFiles(arch *Arch) ([]string, []string)

func (R2u) Forbidden_modes 

func (op R2u) Forbidden_modes() (bool, []string)

func (R2u) Generate 

func (op R2u) Generate(arch *Arch) string

The random genaration does nothing

func (R2u) HLAssemblerInstructionMetadata 

func (Op R2u) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2u) HLAssemblerMatch 

func (Op R2u) HLAssemblerMatch(arch *Arch) []string

func (R2u) HLAssemblerNormalize 

func (Op R2u) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2u) OpInstructionVerilogHeader 

func (op R2u) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (R2u) Op_get_desc 

func (op R2u) Op_get_desc() string

func (R2u) Op_get_instruction_len 

func (op R2u) Op_get_instruction_len(arch *Arch) int

func (R2u) Op_get_name 

func (op R2u) Op_get_name() string

func (R2u) Op_instruction_verilog_default_state 

func (Op R2u) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2u) Op_instruction_verilog_extra_block 

func (Op R2u) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2u) Op_instruction_verilog_extra_modules 

func (Op R2u) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2u) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2u) Op_instruction_verilog_internal_state 

func (Op R2u) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2u) Op_instruction_verilog_reset 

func (Op R2u) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2u) Op_instruction_verilog_state_machine 

func (op R2u) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2u) Op_show_assembler 

func (op R2u) Op_show_assembler(arch *Arch) string

func (R2u) Required_modes 

func (op R2u) Required_modes() (bool, []string)

func (R2u) Required_shared 

func (op R2u) Required_shared() (bool, []string)

func (R2u) Simulate 

func (op R2u) Simulate(vm *VM, instr string) error

The simulation does nothing

type R2v 

type R2v struct{}

The R2v opcode

func (R2v) AbstractAssembler 

func (Op R2v) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2v) Assembler 

func (op R2v) Assembler(arch *Arch, words []string) (string, error)

func (R2v) Disassembler 

func (op R2v) Disassembler(arch *Arch, instr string) (string, error)

func (R2v) ExtraFiles 

func (Op R2v) ExtraFiles(arch *Arch) ([]string, []string)

func (R2v) Forbidden_modes 

func (op R2v) Forbidden_modes() (bool, []string)

func (R2v) Generate 

func (op R2v) Generate(arch *Arch) string

The random genaration does nothing

func (R2v) HLAssemblerInstructionMetadata 

func (Op R2v) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2v) HLAssemblerMatch 

func (Op R2v) HLAssemblerMatch(arch *Arch) []string

func (R2v) HLAssemblerNormalize 

func (Op R2v) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2v) OpInstructionVerilogHeader 

func (op R2v) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2v) Op_get_desc 

func (op R2v) Op_get_desc() string

func (R2v) Op_get_instruction_len 

func (op R2v) Op_get_instruction_len(arch *Arch) int

func (R2v) Op_get_name 

func (op R2v) Op_get_name() string

func (R2v) Op_instruction_verilog_default_state 

func (Op R2v) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2v) Op_instruction_verilog_extra_block 

func (Op R2v) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2v) Op_instruction_verilog_extra_modules 

func (Op R2v) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2v) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2v) Op_instruction_verilog_internal_state 

func (Op R2v) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2v) Op_instruction_verilog_reset 

func (Op R2v) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2v) Op_instruction_verilog_state_machine 

func (op R2v) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2v) Op_show_assembler 

func (op R2v) Op_show_assembler(arch *Arch) string

func (R2v) Required_modes 

func (op R2v) Required_modes() (bool, []string)

func (R2v) Required_shared 

func (op R2v) Required_shared() (bool, []string)

func (R2v) Simulate 

func (op R2v) Simulate(vm *VM, instr string) error

The simulation does nothing

type R2vri 

type R2vri struct{}

The Add opcode is both a basic instruction and a template for other instructions.

func (R2vri) AbstractAssembler 

func (Op R2vri) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (R2vri) Assembler 

func (op R2vri) Assembler(arch *Arch, words []string) (string, error)

func (R2vri) Disassembler 

func (op R2vri) Disassembler(arch *Arch, instr string) (string, error)

func (R2vri) ExtraFiles 

func (Op R2vri) ExtraFiles(arch *Arch) ([]string, []string)

func (R2vri) Forbidden_modes 

func (op R2vri) Forbidden_modes() (bool, []string)

func (R2vri) Generate 

func (op R2vri) Generate(arch *Arch) string

The random genaration does nothing

func (R2vri) HLAssemblerInstructionMetadata 

func (Op R2vri) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (R2vri) HLAssemblerMatch 

func (Op R2vri) HLAssemblerMatch(arch *Arch) []string

func (R2vri) HLAssemblerNormalize 

func (Op R2vri) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (R2vri) OpInstructionVerilogHeader 

func (op R2vri) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (R2vri) Op_get_desc 

func (op R2vri) Op_get_desc() string

func (R2vri) Op_get_instruction_len 

func (op R2vri) Op_get_instruction_len(arch *Arch) int

func (R2vri) Op_get_name 

func (op R2vri) Op_get_name() string

func (R2vri) Op_instruction_verilog_default_state 

func (Op R2vri) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (R2vri) Op_instruction_verilog_extra_block 

func (Op R2vri) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (R2vri) Op_instruction_verilog_extra_modules 

func (Op R2vri) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op R2vri) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (R2vri) Op_instruction_verilog_internal_state 

func (Op R2vri) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (R2vri) Op_instruction_verilog_reset 

func (Op R2vri) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (R2vri) Op_instruction_verilog_state_machine 

func (op R2vri) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (R2vri) Op_show_assembler 

func (op R2vri) Op_show_assembler(arch *Arch) string

func (R2vri) Required_modes 

func (op R2vri) Required_modes() (bool, []string)

func (R2vri) Required_shared 

func (op R2vri) Required_shared() (bool, []string)

func (R2vri) Simulate 

func (op R2vri) Simulate(vm *VM, instr string) error

The simulation does nothing

type Ram 

type Ram struct {
	L uint8 // Number of n-bit memory banks
}

The Ram ,actually not used since the processor only have internal memory

func (*Ram) Write_verilog 

func (ram *Ram) Write_verilog(conf *Config, mach *Machine, ram_module_name string, flavor string) string

TODO Error handling

type Ro2r 

type Ro2r struct{}

func (Ro2r) AbstractAssembler 

func (Op Ro2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Ro2r) Assembler 

func (op Ro2r) Assembler(arch *Arch, words []string) (string, error)

func (Ro2r) Disassembler 

func (op Ro2r) Disassembler(arch *Arch, instr string) (string, error)

func (Ro2r) ExtraFiles 

func (Op Ro2r) ExtraFiles(arch *Arch) ([]string, []string)

func (Ro2r) Forbidden_modes 

func (op Ro2r) Forbidden_modes() (bool, []string)

func (Ro2r) Generate 

func (op Ro2r) Generate(arch *Arch) string

func (Ro2r) HLAssemblerInstructionMetadata 

func (Op Ro2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Ro2r) HLAssemblerMatch 

func (Op Ro2r) HLAssemblerMatch(arch *Arch) []string

func (Ro2r) HLAssemblerNormalize 

func (Op Ro2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Ro2r) OpInstructionVerilogHeader 

func (op Ro2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Ro2r) Op_get_desc 

func (op Ro2r) Op_get_desc() string

func (Ro2r) Op_get_instruction_len 

func (op Ro2r) Op_get_instruction_len(arch *Arch) int

func (Ro2r) Op_get_name 

func (op Ro2r) Op_get_name() string

func (Ro2r) Op_instruction_internal_state 

func (op Ro2r) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Ro2r) Op_instruction_verilog_default_state 

func (Op Ro2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Ro2r) Op_instruction_verilog_extra_block 

func (Op Ro2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Ro2r) Op_instruction_verilog_extra_modules 

func (Op Ro2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Ro2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Ro2r) Op_instruction_verilog_internal_state 

func (Op Ro2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Ro2r) Op_instruction_verilog_reset 

func (Op Ro2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Ro2r) Op_instruction_verilog_state_machine 

func (op Ro2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Ro2r) Op_show_assembler 

func (op Ro2r) Op_show_assembler(arch *Arch) string

func (Ro2r) Required_modes 

func (op Ro2r) Required_modes() (bool, []string)

func (Ro2r) Required_shared 

func (op Ro2r) Required_shared() (bool, []string)

func (Ro2r) Simulate 

func (op Ro2r) Simulate(vm *VM, instr string) error

type Ro2rri 

type Ro2rri struct{}

func (Ro2rri) AbstractAssembler 

func (Op Ro2rri) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Ro2rri) Assembler 

func (op Ro2rri) Assembler(arch *Arch, words []string) (string, error)

func (Ro2rri) Disassembler 

func (op Ro2rri) Disassembler(arch *Arch, instr string) (string, error)

func (Ro2rri) ExtraFiles 

func (Op Ro2rri) ExtraFiles(arch *Arch) ([]string, []string)

func (Ro2rri) Forbidden_modes 

func (op Ro2rri) Forbidden_modes() (bool, []string)

func (Ro2rri) Generate 

func (op Ro2rri) Generate(arch *Arch) string

func (Ro2rri) HLAssemblerInstructionMetadata 

func (Op Ro2rri) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Ro2rri) HLAssemblerMatch 

func (Op Ro2rri) HLAssemblerMatch(arch *Arch) []string

func (Ro2rri) HLAssemblerNormalize 

func (Op Ro2rri) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Ro2rri) OpInstructionVerilogHeader 

func (op Ro2rri) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Ro2rri) Op_get_desc 

func (op Ro2rri) Op_get_desc() string

func (Ro2rri) Op_get_instruction_len 

func (op Ro2rri) Op_get_instruction_len(arch *Arch) int

func (Ro2rri) Op_get_name 

func (op Ro2rri) Op_get_name() string

func (Ro2rri) Op_instruction_internal_state 

func (op Ro2rri) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Ro2rri) Op_instruction_verilog_default_state 

func (Op Ro2rri) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Ro2rri) Op_instruction_verilog_extra_block 

func (Op Ro2rri) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Ro2rri) Op_instruction_verilog_extra_modules 

func (Op Ro2rri) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Ro2rri) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Ro2rri) Op_instruction_verilog_internal_state 

func (Op Ro2rri) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Ro2rri) Op_instruction_verilog_reset 

func (Op Ro2rri) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Ro2rri) Op_instruction_verilog_state_machine 

func (op Ro2rri) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Ro2rri) Op_show_assembler 

func (op Ro2rri) Op_show_assembler(arch *Arch) string

func (Ro2rri) Required_modes 

func (op Ro2rri) Required_modes() (bool, []string)

func (Ro2rri) Required_shared 

func (op Ro2rri) Required_shared() (bool, []string)

func (Ro2rri) Simulate 

func (op Ro2rri) Simulate(vm *VM, instr string) error

type Rom 

type Rom struct {
	O uint8 // Number of ROM cells (the program storage)
}

The Rom

func (*Rom) String 

func (rom *Rom) String() string

func (*Rom) Write_verilog 

func (rom *Rom) Write_verilog(mach *Machine, rom_module_name string, flavor string) string

type Rsc 

type Rsc struct{}

The Rsc opcode is both a basic instruction and a template for other instructions.

func (Rsc) AbstractAssembler 

func (Op Rsc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Rsc) Assembler 

func (op Rsc) Assembler(arch *Arch, words []string) (string, error)

func (Rsc) Disassembler 

func (op Rsc) Disassembler(arch *Arch, instr string) (string, error)

func (Rsc) ExtraFiles 

func (Op Rsc) ExtraFiles(arch *Arch) ([]string, []string)

func (Rsc) Forbidden_modes 

func (op Rsc) Forbidden_modes() (bool, []string)

func (Rsc) Generate 

func (op Rsc) Generate(arch *Arch) string

The random genaration does nothing

func (Rsc) HLAssemblerInstructionMetadata 

func (Op Rsc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Rsc) HLAssemblerMatch 

func (Op Rsc) HLAssemblerMatch(arch *Arch) []string

func (Rsc) HLAssemblerNormalize 

func (Op Rsc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Rsc) OpInstructionVerilogHeader 

func (op Rsc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Rsc) Op_get_desc 

func (op Rsc) Op_get_desc() string

func (Rsc) Op_get_instruction_len 

func (op Rsc) Op_get_instruction_len(arch *Arch) int

func (Rsc) Op_get_name 

func (op Rsc) Op_get_name() string

func (Rsc) Op_instruction_internal_state 

func (op Rsc) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Rsc) Op_instruction_verilog_default_state 

func (Op Rsc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Rsc) Op_instruction_verilog_extra_block 

func (Op Rsc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Rsc) Op_instruction_verilog_extra_modules 

func (Op Rsc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Rsc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Rsc) Op_instruction_verilog_internal_state 

func (Op Rsc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Rsc) Op_instruction_verilog_reset 

func (Op Rsc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Rsc) Op_instruction_verilog_state_machine 

func (op Rsc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Rsc) Op_show_assembler 

func (op Rsc) Op_show_assembler(arch *Arch) string

func (Rsc) Required_modes 

func (op Rsc) Required_modes() (bool, []string)

func (Rsc) Required_shared 

func (op Rsc) Required_shared() (bool, []string)

func (Rsc) Simulate 

func (op Rsc) Simulate(vm *VM, instr string) error

The simulation does nothing

type Rset 

type Rset struct{}

func (Rset) AbstractAssembler 

func (Op Rset) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Rset) Assembler 

func (op Rset) Assembler(arch *Arch, words []string) (string, error)

func (Rset) Disassembler 

func (op Rset) Disassembler(arch *Arch, instr string) (string, error)

func (Rset) ExtraFiles 

func (Op Rset) ExtraFiles(arch *Arch) ([]string, []string)

func (Rset) Forbidden_modes 

func (op Rset) Forbidden_modes() (bool, []string)

func (Rset) Generate 

func (op Rset) Generate(arch *Arch) string

func (Rset) HLAssemblerInstructionMetadata 

func (Op Rset) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Rset) HLAssemblerMatch 

func (Op Rset) HLAssemblerMatch(arch *Arch) []string

func (Rset) HLAssemblerNormalize 

func (Op Rset) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Rset) OpInstructionVerilogHeader 

func (op Rset) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Rset) Op_get_desc 

func (op Rset) Op_get_desc() string

func (Rset) Op_get_instruction_len 

func (op Rset) Op_get_instruction_len(arch *Arch) int

func (Rset) Op_get_name 

func (op Rset) Op_get_name() string

func (Rset) Op_instruction_internal_state 

func (op Rset) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Rset) Op_instruction_verilog_default_state 

func (Op Rset) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Rset) Op_instruction_verilog_extra_block 

func (Op Rset) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Rset) Op_instruction_verilog_extra_modules 

func (Op Rset) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Rset) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Rset) Op_instruction_verilog_internal_state 

func (Op Rset) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Rset) Op_instruction_verilog_reset 

func (Op Rset) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Rset) Op_instruction_verilog_state_machine 

func (op Rset) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Rset) Op_show_assembler 

func (op Rset) Op_show_assembler(arch *Arch) string

func (Rset) Required_modes 

func (op Rset) Required_modes() (bool, []string)

func (Rset) Required_shared 

func (op Rset) Required_shared() (bool, []string)

func (Rset) Simulate 

func (op Rset) Simulate(vm *VM, instr string) error

type Rsets 

type Rsets struct {
	// contains filtered or unexported fields
}

func (Rsets) AbstractAssembler 

func (Op Rsets) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Rsets) Assembler 

func (op Rsets) Assembler(arch *Arch, words []string) (string, error)

func (Rsets) Disassembler 

func (op Rsets) Disassembler(arch *Arch, instr string) (string, error)

func (Rsets) ExtraFiles 

func (op Rsets) ExtraFiles(arch *Arch) ([]string, []string)

func (Rsets) Forbidden_modes 

func (op Rsets) Forbidden_modes() (bool, []string)

func (Rsets) Generate 

func (op Rsets) Generate(arch *Arch) string

func (Rsets) HLAssemblerInstructionMetadata 

func (op Rsets) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Rsets) HLAssemblerMatch 

func (op Rsets) HLAssemblerMatch(arch *Arch) []string

func (Rsets) HLAssemblerNormalize 

func (op Rsets) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Rsets) OpInstructionVerilogHeader 

func (op Rsets) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Rsets) Op_get_desc 

func (op Rsets) Op_get_desc() string

func (Rsets) Op_get_instruction_len 

func (op Rsets) Op_get_instruction_len(arch *Arch) int

func (Rsets) Op_get_name 

func (op Rsets) Op_get_name() string

func (Rsets) Op_instruction_internal_state 

func (op Rsets) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Rsets) Op_instruction_verilog_default_state 

func (Op Rsets) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Rsets) Op_instruction_verilog_extra_block 

func (op Rsets) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Rsets) Op_instruction_verilog_extra_modules 

func (Op Rsets) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Rsets) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Rsets) Op_instruction_verilog_internal_state 

func (Op Rsets) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Rsets) Op_instruction_verilog_reset 

func (Op Rsets) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Rsets) Op_instruction_verilog_state_machine 

func (op Rsets) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Rsets) Op_show_assembler 

func (op Rsets) Op_show_assembler(arch *Arch) string

func (Rsets) Required_modes 

func (op Rsets) Required_modes() (bool, []string)

func (Rsets) Required_shared 

func (op Rsets) Required_shared() (bool, []string)

func (Rsets) Simulate 

func (op Rsets) Simulate(vm *VM, instr string) error

type RuntimeInfo 

type RuntimeInfo struct {
	HeaderFlags map[string]bool
}

func (*RuntimeInfo) Check 

func (ri *RuntimeInfo) Check(flag string) bool

func (*RuntimeInfo) Init 

func (ri *RuntimeInfo) Init()

type S2r 

type S2r struct{}

The S2r opcode is both a basic instruction and a template for other instructions.

func (S2r) AbstractAssembler 

func (Op S2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (S2r) Assembler 

func (op S2r) Assembler(arch *Arch, words []string) (string, error)

func (S2r) Disassembler 

func (op S2r) Disassembler(arch *Arch, instr string) (string, error)

func (S2r) ExtraFiles 

func (Op S2r) ExtraFiles(arch *Arch) ([]string, []string)

func (S2r) Forbidden_modes 

func (op S2r) Forbidden_modes() (bool, []string)

func (S2r) Generate 

func (op S2r) Generate(arch *Arch) string

The random genaration does nothing

func (S2r) HLAssemblerInstructionMetadata 

func (Op S2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (S2r) HLAssemblerMatch 

func (Op S2r) HLAssemblerMatch(arch *Arch) []string

func (S2r) HLAssemblerNormalize 

func (Op S2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (S2r) OpInstructionVerilogHeader 

func (op S2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (S2r) Op_get_desc 

func (op S2r) Op_get_desc() string

func (S2r) Op_get_instruction_len 

func (op S2r) Op_get_instruction_len(arch *Arch) int

func (S2r) Op_get_name 

func (op S2r) Op_get_name() string

func (S2r) Op_instruction_verilog_default_state 

func (Op S2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (S2r) Op_instruction_verilog_extra_block 

func (Op S2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (S2r) Op_instruction_verilog_extra_modules 

func (Op S2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op S2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (S2r) Op_instruction_verilog_internal_state 

func (Op S2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (S2r) Op_instruction_verilog_reset 

func (Op S2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (S2r) Op_instruction_verilog_state_machine 

func (op S2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (S2r) Op_show_assembler 

func (op S2r) Op_show_assembler(arch *Arch) string

func (S2r) Required_modes 

func (op S2r) Required_modes() (bool, []string)

func (S2r) Required_shared 

func (op S2r) Required_shared() (bool, []string)

func (S2r) Simulate 

func (op S2r) Simulate(vm *VM, instr string) error

The simulation does nothing

type Saj 

type Saj struct{}

The Saj opcode is both a basic instruction and a template for other instructions.

func (Saj) AbstractAssembler 

func (Op Saj) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Saj) Assembler 

func (op Saj) Assembler(arch *Arch, words []string) (string, error)

func (Saj) Disassembler 

func (op Saj) Disassembler(arch *Arch, instr string) (string, error)

func (Saj) ExtraFiles 

func (Op Saj) ExtraFiles(arch *Arch) ([]string, []string)

func (Saj) Forbidden_modes 

func (op Saj) Forbidden_modes() (bool, []string)

func (Saj) Generate 

func (op Saj) Generate(arch *Arch) string

The random genaration does nothing

func (Saj) HLAssemblerInstructionMetadata 

func (Op Saj) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Saj) HLAssemblerMatch 

func (Op Saj) HLAssemblerMatch(arch *Arch) []string

func (Saj) HLAssemblerNormalize 

func (Op Saj) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Saj) OpInstructionVerilogHeader 

func (op Saj) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Saj) Op_get_desc 

func (op Saj) Op_get_desc() string

func (Saj) Op_get_instruction_len 

func (op Saj) Op_get_instruction_len(arch *Arch) int

func (Saj) Op_get_name 

func (op Saj) Op_get_name() string

func (Saj) Op_instruction_internal_state 

func (op Saj) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Saj) Op_instruction_verilog_default_state 

func (Op Saj) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Saj) Op_instruction_verilog_extra_block 

func (Op Saj) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Saj) Op_instruction_verilog_extra_modules 

func (Op Saj) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Saj) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Saj) Op_instruction_verilog_internal_state 

func (Op Saj) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Saj) Op_instruction_verilog_reset 

func (Op Saj) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Saj) Op_instruction_verilog_state_machine 

func (op Saj) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Saj) Op_show_assembler 

func (op Saj) Op_show_assembler(arch *Arch) string

func (Saj) Required_modes 

func (op Saj) Required_modes() (bool, []string)

func (Saj) Required_shared 

func (op Saj) Required_shared() (bool, []string)

func (Saj) Simulate 

func (op Saj) Simulate(vm *VM, instr string) error

The simulation does nothing

type Sbc 

type Sbc struct{}

The Sbc opcode is both a basic instruction and a template for other instructions.

func (Sbc) AbstractAssembler 

func (Op Sbc) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Sbc) Assembler 

func (op Sbc) Assembler(arch *Arch, words []string) (string, error)

func (Sbc) Disassembler 

func (op Sbc) Disassembler(arch *Arch, instr string) (string, error)

func (Sbc) ExtraFiles 

func (Op Sbc) ExtraFiles(arch *Arch) ([]string, []string)

func (Sbc) Forbidden_modes 

func (op Sbc) Forbidden_modes() (bool, []string)

func (Sbc) Generate 

func (op Sbc) Generate(arch *Arch) string

The random genaration does nothing

func (Sbc) HLAssemblerInstructionMetadata 

func (Op Sbc) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Sbc) HLAssemblerMatch 

func (Op Sbc) HLAssemblerMatch(arch *Arch) []string

func (Sbc) HLAssemblerNormalize 

func (Op Sbc) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Sbc) OpInstructionVerilogHeader 

func (op Sbc) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Sbc) Op_get_desc 

func (op Sbc) Op_get_desc() string

func (Sbc) Op_get_instruction_len 

func (op Sbc) Op_get_instruction_len(arch *Arch) int

func (Sbc) Op_get_name 

func (op Sbc) Op_get_name() string

func (Sbc) Op_instruction_internal_state 

func (op Sbc) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Sbc) Op_instruction_verilog_default_state 

func (Op Sbc) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Sbc) Op_instruction_verilog_extra_block 

func (Op Sbc) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Sbc) Op_instruction_verilog_extra_modules 

func (Op Sbc) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Sbc) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Sbc) Op_instruction_verilog_internal_state 

func (Op Sbc) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Sbc) Op_instruction_verilog_reset 

func (Op Sbc) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Sbc) Op_instruction_verilog_state_machine 

func (op Sbc) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Sbc) Op_show_assembler 

func (op Sbc) Op_show_assembler(arch *Arch) string

func (Sbc) Required_modes 

func (op Sbc) Required_modes() (bool, []string)

func (Sbc) Required_shared 

func (op Sbc) Required_shared() (bool, []string)

func (Sbc) Simulate 

func (op Sbc) Simulate(vm *VM, instr string) error

The simulation does nothing

type Sharedel 

type Sharedel interface {
	Shr_get_name() string
	Shortname() string
	GetArchHeader(*Arch, string, int) string // returns the architecture header for the shared element
	GetArchParams(*Arch, string, int) string // returns the architecture module parameters for the shared element
	GetCPParams(*Arch, string, int) string   // returns the processor (CP) module internal parameters for the shared element
}

type Sharedmem 

type Sharedmem struct{}

func (Sharedmem) GetArchHeader 

func (op Sharedmem) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Sharedmem) GetArchParams 

func (op Sharedmem) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Sharedmem) GetCPParams 

func (op Sharedmem) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Sharedmem) Shortname 

func (op Sharedmem) Shortname() string

func (Sharedmem) Shr_get_name 

func (op Sharedmem) Shr_get_name() string

type Sic 

type Sic struct{}

func (Sic) AbstractAssembler 

func (Op Sic) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Sic) Assembler 

func (op Sic) Assembler(arch *Arch, words []string) (string, error)

func (Sic) Disassembler 

func (op Sic) Disassembler(arch *Arch, instr string) (string, error)

func (Sic) ExtraFiles 

func (Op Sic) ExtraFiles(arch *Arch) ([]string, []string)

func (Sic) Forbidden_modes 

func (op Sic) Forbidden_modes() (bool, []string)

func (Sic) Generate 

func (op Sic) Generate(arch *Arch) string

func (Sic) HLAssemblerInstructionMetadata 

func (Op Sic) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Sic) HLAssemblerMatch 

func (Op Sic) HLAssemblerMatch(arch *Arch) []string

func (Sic) HLAssemblerNormalize 

func (Op Sic) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Sic) OpInstructionVerilogHeader 

func (op Sic) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Sic) Op_get_desc 

func (op Sic) Op_get_desc() string

func (Sic) Op_get_instruction_len 

func (op Sic) Op_get_instruction_len(arch *Arch) int

func (Sic) Op_get_name 

func (op Sic) Op_get_name() string

func (Sic) Op_instruction_internal_state 

func (op Sic) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Sic) Op_instruction_verilog_default_state 

func (Op Sic) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Sic) Op_instruction_verilog_extra_block 

func (Op Sic) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Sic) Op_instruction_verilog_extra_modules 

func (Op Sic) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Sic) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Sic) Op_instruction_verilog_internal_state 

func (Op Sic) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Sic) Op_instruction_verilog_reset 

func (Op Sic) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Sic) Op_instruction_verilog_state_machine 

func (op Sic) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Sic) Op_show_assembler 

func (op Sic) Op_show_assembler(arch *Arch) string

func (Sic) Required_modes 

func (op Sic) Required_modes() (bool, []string)

func (Sic) Required_shared 

func (op Sic) Required_shared() (bool, []string)

func (Sic) Simulate 

func (op Sic) Simulate(vm *VM, instr string) error

type Sim_config 

type Sim_config struct {
	Show_pc          bool
	Show_instruction bool
	Show_disasm      bool
	Show_regs_pre    bool
	Show_regs_post   bool
	Show_io_pre      bool
	Show_io_post     bool
}

func (*Sim_config) Init 

func (sc *Sim_config) Init(s *simbox.Simbox, vm *VM) error

type Sim_drive 

type Sim_drive struct {
	Injectables []*interface{}
	AbsSet      map[uint64]Sim_tick_set
}

func (*Sim_drive) Init 

func (sd *Sim_drive) Init(s *simbox.Simbox, vm *VM) error

type Sim_report 

type Sim_report struct {
	Reportables []*interface{}
	AbsGet      map[uint64]Sim_tick_get
}

func (*Sim_report) Init 

func (sd *Sim_report) Init(s *simbox.Simbox, vm *VM) error

type Sim_tick_get 

type Sim_tick_get map[int]interface{}

This is initializated when the simulation starts and filled on the way

type Sim_tick_set 

type Sim_tick_set map[int]interface{}

Simbox rules are converted in a sim drive when the simulation starts and applied during the simulation

type Stack 

type Stack struct{}

func (Stack) GetArchHeader 

func (op Stack) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Stack) GetArchParams 

func (op Stack) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Stack) GetCPParams 

func (op Stack) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Stack) Shortname 

func (op Stack) Shortname() string

func (Stack) Shr_get_name 

func (op Stack) Shr_get_name() string

type Sub 

type Sub struct{}

The Sub opcode is both a basic instruction and a template for other instructions.

func (Sub) AbstractAssembler 

func (Op Sub) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Sub) Assembler 

func (op Sub) Assembler(arch *Arch, words []string) (string, error)

func (Sub) Disassembler 

func (op Sub) Disassembler(arch *Arch, instr string) (string, error)

func (Sub) ExtraFiles 

func (Op Sub) ExtraFiles(arch *Arch) ([]string, []string)

func (Sub) Forbidden_modes 

func (op Sub) Forbidden_modes() (bool, []string)

func (Sub) Generate 

func (op Sub) Generate(arch *Arch) string

The random genaration does nothing

func (Sub) HLAssemblerInstructionMetadata 

func (Op Sub) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Sub) HLAssemblerMatch 

func (Op Sub) HLAssemblerMatch(arch *Arch) []string

func (Sub) HLAssemblerNormalize 

func (Op Sub) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Sub) OpInstructionVerilogHeader 

func (op Sub) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Sub) Op_get_desc 

func (op Sub) Op_get_desc() string

func (Sub) Op_get_instruction_len 

func (op Sub) Op_get_instruction_len(arch *Arch) int

func (Sub) Op_get_name 

func (op Sub) Op_get_name() string

func (Sub) Op_instruction_internal_state 

func (op Sub) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Sub) Op_instruction_verilog_default_state 

func (Op Sub) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Sub) Op_instruction_verilog_extra_block 

func (Op Sub) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Sub) Op_instruction_verilog_extra_modules 

func (Op Sub) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Sub) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Sub) Op_instruction_verilog_internal_state 

func (Op Sub) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Sub) Op_instruction_verilog_reset 

func (Op Sub) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Sub) Op_instruction_verilog_state_machine 

func (op Sub) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Sub) Op_show_assembler 

func (op Sub) Op_show_assembler(arch *Arch) string

func (Sub) Required_modes 

func (op Sub) Required_modes() (bool, []string)

func (Sub) Required_shared 

func (op Sub) Required_shared() (bool, []string)

func (Sub) Simulate 

func (op Sub) Simulate(vm *VM, instr string) error

The simulation does nothing

type T2r 

type T2r struct{}

The T2r opcode

func (T2r) AbstractAssembler 

func (Op T2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (T2r) Assembler 

func (op T2r) Assembler(arch *Arch, words []string) (string, error)

func (T2r) Disassembler 

func (op T2r) Disassembler(arch *Arch, instr string) (string, error)

func (T2r) ExtraFiles 

func (Op T2r) ExtraFiles(arch *Arch) ([]string, []string)

func (T2r) Forbidden_modes 

func (op T2r) Forbidden_modes() (bool, []string)

func (T2r) Generate 

func (op T2r) Generate(arch *Arch) string

The random genaration does nothing

func (T2r) HLAssemblerInstructionMetadata 

func (Op T2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (T2r) HLAssemblerMatch 

func (Op T2r) HLAssemblerMatch(arch *Arch) []string

func (T2r) HLAssemblerNormalize 

func (Op T2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (T2r) OpInstructionVerilogHeader 

func (op T2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (T2r) Op_get_desc 

func (op T2r) Op_get_desc() string

func (T2r) Op_get_instruction_len 

func (op T2r) Op_get_instruction_len(arch *Arch) int

func (T2r) Op_get_name 

func (op T2r) Op_get_name() string

func (T2r) Op_instruction_verilog_default_state 

func (Op T2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (T2r) Op_instruction_verilog_extra_block 

func (Op T2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (T2r) Op_instruction_verilog_extra_modules 

func (Op T2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op T2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (T2r) Op_instruction_verilog_internal_state 

func (Op T2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (T2r) Op_instruction_verilog_reset 

func (Op T2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (T2r) Op_instruction_verilog_state_machine 

func (op T2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (T2r) Op_show_assembler 

func (op T2r) Op_show_assembler(arch *Arch) string

func (T2r) Required_modes 

func (op T2r) Required_modes() (bool, []string)

func (T2r) Required_shared 

func (op T2r) Required_shared() (bool, []string)

func (T2r) Simulate 

func (op T2r) Simulate(vm *VM, instr string) error

The simulation does nothing

type U2r 

type U2r struct{}

The U2r opcode

func (U2r) AbstractAssembler 

func (Op U2r) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (U2r) Assembler 

func (op U2r) Assembler(arch *Arch, words []string) (string, error)

func (U2r) Disassembler 

func (op U2r) Disassembler(arch *Arch, instr string) (string, error)

func (U2r) ExtraFiles 

func (Op U2r) ExtraFiles(arch *Arch) ([]string, []string)

func (U2r) Forbidden_modes 

func (op U2r) Forbidden_modes() (bool, []string)

func (U2r) Generate 

func (op U2r) Generate(arch *Arch) string

The random genaration does nothing

func (U2r) HLAssemblerInstructionMetadata 

func (Op U2r) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (U2r) HLAssemblerMatch 

func (Op U2r) HLAssemblerMatch(arch *Arch) []string

func (U2r) HLAssemblerNormalize 

func (Op U2r) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (U2r) OpInstructionVerilogHeader 

func (op U2r) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pName string) string

func (U2r) Op_get_desc 

func (op U2r) Op_get_desc() string

func (U2r) Op_get_instruction_len 

func (op U2r) Op_get_instruction_len(arch *Arch) int

func (U2r) Op_get_name 

func (op U2r) Op_get_name() string

func (U2r) Op_instruction_verilog_default_state 

func (Op U2r) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (U2r) Op_instruction_verilog_extra_block 

func (Op U2r) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (U2r) Op_instruction_verilog_extra_modules 

func (Op U2r) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op U2r) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (U2r) Op_instruction_verilog_internal_state 

func (Op U2r) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (U2r) Op_instruction_verilog_reset 

func (Op U2r) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (U2r) Op_instruction_verilog_state_machine 

func (op U2r) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (U2r) Op_show_assembler 

func (op U2r) Op_show_assembler(arch *Arch) string

func (U2r) Required_modes 

func (op U2r) Required_modes() (bool, []string)

func (U2r) Required_shared 

func (op U2r) Required_shared() (bool, []string)

func (U2r) Simulate 

func (op U2r) Simulate(vm *VM, instr string) error

The simulation does nothing

type Uart 

type Uart struct{}

func (Uart) GetArchHeader 

func (op Uart) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Uart) GetArchParams 

func (op Uart) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Uart) GetCPParams 

func (op Uart) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Uart) Shortname 

func (op Uart) Shortname() string

func (Uart) Shr_get_name 

func (op Uart) Shr_get_name() string

type UsageNotify 

type UsageNotify struct {
	ComponentType uint8
	Components    string
	Componenti    int
}

type VM 

type VM struct {
	CpID      uint32
	Mach      *Machine
	Registers []interface{}
	Memory    []interface{}
	Inputs    []interface{}
	Outputs   []interface{}

	InputsValid  []bool
	OutputsValid []bool

	InputsRecv  []bool
	OutputsRecv []bool

	Pc           uint64
	Extra_states map[string]interface{}
	CmdChan      chan []byte
}

func (*VM) CopyState 

func (vm *VM) CopyState(vmsource *VM)

func (*VM) DumpIO 

func (vm *VM) DumpIO() string

func (*VM) DumpRegisters 

func (vm *VM) DumpRegisters() string

func (*VM) GetElementLocation 

func (vm *VM) GetElementLocation(mnemonic string) (*interface{}, error)

func (*VM) Init 

func (vm *VM) Init() error

func (*VM) Step 

func (vm *VM) Step(psc *Sim_config) (string, error)

type Vtextmem 

type Vtextmem struct{}

func (Vtextmem) GetArchHeader 

func (op Vtextmem) GetArchHeader(arch *Arch, shared_constraint string, seq int) string

func (Vtextmem) GetArchParams 

func (op Vtextmem) GetArchParams(arch *Arch, shared_constraint string, seq int) string

func (Vtextmem) GetCPParams 

func (op Vtextmem) GetCPParams(arch *Arch, shared_constraint string, seq int) string

func (Vtextmem) Shortname 

func (op Vtextmem) Shortname() string

func (Vtextmem) Shr_get_name 

func (op Vtextmem) Shr_get_name() string

type Wrd 

type Wrd struct{}

func (Wrd) AbstractAssembler 

func (Op Wrd) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Wrd) Assembler 

func (op Wrd) Assembler(arch *Arch, words []string) (string, error)

func (Wrd) Disassembler 

func (op Wrd) Disassembler(arch *Arch, instr string) (string, error)

func (Wrd) ExtraFiles 

func (Op Wrd) ExtraFiles(arch *Arch) ([]string, []string)

func (Wrd) Forbidden_modes 

func (op Wrd) Forbidden_modes() (bool, []string)

func (Wrd) Generate 

func (op Wrd) Generate(arch *Arch) string

func (Wrd) HLAssemblerInstructionMetadata 

func (Op Wrd) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Wrd) HLAssemblerMatch 

func (Op Wrd) HLAssemblerMatch(arch *Arch) []string

func (Wrd) HLAssemblerNormalize 

func (Op Wrd) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Wrd) OpInstructionVerilogHeader 

func (op Wrd) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Wrd) Op_get_desc 

func (op Wrd) Op_get_desc() string

func (Wrd) Op_get_instruction_len 

func (op Wrd) Op_get_instruction_len(arch *Arch) int

func (Wrd) Op_get_name 

func (op Wrd) Op_get_name() string

func (Wrd) Op_instruction_verilog_default_state 

func (Op Wrd) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Wrd) Op_instruction_verilog_extra_block 

func (Op Wrd) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Wrd) Op_instruction_verilog_extra_modules 

func (Op Wrd) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Wrd) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Wrd) Op_instruction_verilog_internal_state 

func (Op Wrd) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Wrd) Op_instruction_verilog_reset 

func (Op Wrd) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Wrd) Op_instruction_verilog_state_machine 

func (op Wrd) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Wrd) Op_show_assembler 

func (op Wrd) Op_show_assembler(arch *Arch) string

func (Wrd) Required_modes 

func (op Wrd) Required_modes() (bool, []string)

func (Wrd) Required_shared 

func (op Wrd) Required_shared() (bool, []string)

func (Wrd) Simulate 

func (op Wrd) Simulate(vm *VM, instr string) error

type Wwr 

type Wwr struct{}

func (Wwr) AbstractAssembler 

func (Op Wwr) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Wwr) Assembler 

func (op Wwr) Assembler(arch *Arch, words []string) (string, error)

func (Wwr) Disassembler 

func (op Wwr) Disassembler(arch *Arch, instr string) (string, error)

func (Wwr) ExtraFiles 

func (Op Wwr) ExtraFiles(arch *Arch) ([]string, []string)

func (Wwr) Forbidden_modes 

func (op Wwr) Forbidden_modes() (bool, []string)

func (Wwr) Generate 

func (op Wwr) Generate(arch *Arch) string

func (Wwr) HLAssemblerInstructionMetadata 

func (Op Wwr) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Wwr) HLAssemblerMatch 

func (Op Wwr) HLAssemblerMatch(arch *Arch) []string

func (Wwr) HLAssemblerNormalize 

func (Op Wwr) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Wwr) OpInstructionVerilogHeader 

func (op Wwr) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Wwr) Op_get_desc 

func (op Wwr) Op_get_desc() string

func (Wwr) Op_get_instruction_len 

func (op Wwr) Op_get_instruction_len(arch *Arch) int

func (Wwr) Op_get_name 

func (op Wwr) Op_get_name() string

func (Wwr) Op_instruction_verilog_default_state 

func (Op Wwr) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Wwr) Op_instruction_verilog_extra_block 

func (Op Wwr) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Wwr) Op_instruction_verilog_extra_modules 

func (Op Wwr) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Wwr) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Wwr) Op_instruction_verilog_internal_state 

func (Op Wwr) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Wwr) Op_instruction_verilog_reset 

func (Op Wwr) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Wwr) Op_instruction_verilog_state_machine 

func (op Wwr) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Wwr) Op_show_assembler 

func (op Wwr) Op_show_assembler(arch *Arch) string

func (Wwr) Required_modes 

func (op Wwr) Required_modes() (bool, []string)

func (Wwr) Required_shared 

func (op Wwr) Required_shared() (bool, []string)

func (Wwr) Simulate 

func (op Wwr) Simulate(vm *VM, instr string) error

type Xnor 

type Xnor struct{}

The Xnor opcode is both a basic instruction and a template for other instructions.

func (Xnor) AbstractAssembler 

func (Op Xnor) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Xnor) Assembler 

func (op Xnor) Assembler(arch *Arch, words []string) (string, error)

func (Xnor) Disassembler 

func (op Xnor) Disassembler(arch *Arch, instr string) (string, error)

func (Xnor) ExtraFiles 

func (Op Xnor) ExtraFiles(arch *Arch) ([]string, []string)

func (Xnor) Forbidden_modes 

func (op Xnor) Forbidden_modes() (bool, []string)

func (Xnor) Generate 

func (op Xnor) Generate(arch *Arch) string

The random genaration does nothing

func (Xnor) HLAssemblerInstructionMetadata 

func (Op Xnor) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Xnor) HLAssemblerMatch 

func (Op Xnor) HLAssemblerMatch(arch *Arch) []string

func (Xnor) HLAssemblerNormalize 

func (Op Xnor) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Xnor) OpInstructionVerilogHeader 

func (op Xnor) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Xnor) Op_get_desc 

func (op Xnor) Op_get_desc() string

func (Xnor) Op_get_instruction_len 

func (op Xnor) Op_get_instruction_len(arch *Arch) int

func (Xnor) Op_get_name 

func (op Xnor) Op_get_name() string

func (Xnor) Op_instruction_internal_state 

func (op Xnor) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Xnor) Op_instruction_verilog_default_state 

func (Op Xnor) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Xnor) Op_instruction_verilog_extra_block 

func (Op Xnor) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Xnor) Op_instruction_verilog_extra_modules 

func (Op Xnor) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Xnor) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Xnor) Op_instruction_verilog_internal_state 

func (Op Xnor) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Xnor) Op_instruction_verilog_reset 

func (Op Xnor) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Xnor) Op_instruction_verilog_state_machine 

func (op Xnor) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Xnor) Op_show_assembler 

func (op Xnor) Op_show_assembler(arch *Arch) string

func (Xnor) Required_modes 

func (op Xnor) Required_modes() (bool, []string)

func (Xnor) Required_shared 

func (op Xnor) Required_shared() (bool, []string)

func (Xnor) Simulate 

func (op Xnor) Simulate(vm *VM, instr string) error

The simulation does nothing

type Xor 

type Xor struct{}

The And opcode is both a basic instruction and a template for other instructions.

func (Xor) AbstractAssembler 

func (Op Xor) AbstractAssembler(arch *Arch, words []string) ([]UsageNotify, error)

func (Xor) Assembler 

func (op Xor) Assembler(arch *Arch, words []string) (string, error)

func (Xor) Disassembler 

func (op Xor) Disassembler(arch *Arch, instr string) (string, error)

func (Xor) ExtraFiles 

func (Op Xor) ExtraFiles(arch *Arch) ([]string, []string)

func (Xor) Forbidden_modes 

func (op Xor) Forbidden_modes() (bool, []string)

func (Xor) Generate 

func (op Xor) Generate(arch *Arch) string

The random genaration does nothing

func (Xor) HLAssemblerInstructionMetadata 

func (Op Xor) HLAssemblerInstructionMetadata(arch *Arch, line *bmline.BasmLine) (*bmmeta.BasmMeta, error)

func (Xor) HLAssemblerMatch 

func (Op Xor) HLAssemblerMatch(arch *Arch) []string

func (Xor) HLAssemblerNormalize 

func (Op Xor) HLAssemblerNormalize(arch *Arch, rg *bmreqs.ReqRoot, node string, line *bmline.BasmLine) (*bmline.BasmLine, error)

func (Xor) OpInstructionVerilogHeader 

func (op Xor) OpInstructionVerilogHeader(conf *Config, arch *Arch, flavor string, pname string) string

func (Xor) Op_get_desc 

func (op Xor) Op_get_desc() string

func (Xor) Op_get_instruction_len 

func (op Xor) Op_get_instruction_len(arch *Arch) int

func (Xor) Op_get_name 

func (op Xor) Op_get_name() string

func (Xor) Op_instruction_internal_state 

func (op Xor) Op_instruction_internal_state(arch *Arch, flavor string) string

func (Xor) Op_instruction_verilog_default_state 

func (Op Xor) Op_instruction_verilog_default_state(arch *Arch, flavor string) string

func (Xor) Op_instruction_verilog_extra_block 

func (Op Xor) Op_instruction_verilog_extra_block(arch *Arch, flavor string, level uint8, blockname string, objects []string) string

func (Xor) Op_instruction_verilog_extra_modules 

func (Op Xor) Op_instruction_verilog_extra_modules(arch *Arch, flavor string) ([]string, []string)
func (op Xor) Op_instruction_verilog_footer(arch *Arch, flavor string) string

func (Xor) Op_instruction_verilog_internal_state 

func (Op Xor) Op_instruction_verilog_internal_state(arch *Arch, flavor string) string

func (Xor) Op_instruction_verilog_reset 

func (Op Xor) Op_instruction_verilog_reset(arch *Arch, flavor string) string

func (Xor) Op_instruction_verilog_state_machine 

func (op Xor) Op_instruction_verilog_state_machine(conf *Config, arch *Arch, rg *bmreqs.ReqRoot, flavor string) string

func (Xor) Op_show_assembler 

func (op Xor) Op_show_assembler(arch *Arch) string

func (Xor) Required_modes 

func (op Xor) Required_modes() (bool, []string)

func (Xor) Required_shared 

func (op Xor) Required_shared() (bool, []string)

func (Xor) Simulate 

func (op Xor) Simulate(vm *VM, instr string) error

The simulation does nothing

Source Files

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