README
¶
cpuid
Package cpuid provides information about the CPU running the current program.
CPU features are detected on startup, and kept for fast access through the life of the application. Currently x86 / x64 (AMD64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.
You can access the CPU information by accessing the shared CPU variable of the cpuid library.
Package home: https://github.com/klauspost/cpuid
features
CPU Instructions
- CMOV (i686 CMOV)
- NX (NX (No-Execute) bit)
- AMD3DNOW (AMD 3DNOW)
- AMD3DNOWEXT (AMD 3DNowExt)
- MMX (standard MMX)
- MMXEXT (SSE integer functions or AMD MMX ext)
- SSE (SSE functions)
- SSE2 (P4 SSE functions)
- SSE3 (Prescott SSE3 functions)
- SSSE3 (Conroe SSSE3 functions)
- SSE4 (Penryn SSE4.1 functions)
- SSE4A (AMD Barcelona microarchitecture SSE4a instructions)
- SSE42 (Nehalem SSE4.2 functions)
- AVX (AVX functions)
- AVX2 (AVX2 functions)
- FMA3 (Intel FMA 3)
- FMA4 (Bulldozer FMA4 functions)
- XOP (Bulldozer XOP functions)
- F16C (Half-precision floating-point conversion)
- BMI1 (Bit Manipulation Instruction Set 1)
- BMI2 (Bit Manipulation Instruction Set 2)
- TBM (AMD Trailing Bit Manipulation)
- LZCNT (LZCNT instruction)
- POPCNT (POPCNT instruction)
- AESNI (Advanced Encryption Standard New Instructions)
- CLMUL (Carry-less Multiplication)
- HTT (Hyperthreading (enabled))
- HLE (Hardware Lock Elision)
- RTM (Restricted Transactional Memory)
- RDRAND (RDRAND instruction is available)
- RDSEED (RDSEED instruction is available)
- ADX (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
- SHA (Intel SHA Extensions)
- AVX512F (AVX-512 Foundation)
- AVX512DQ (AVX-512 Doubleword and Quadword Instructions)
- AVX512IFMA (AVX-512 Integer Fused Multiply-Add Instructions)
- AVX512PF (AVX-512 Prefetch Instructions)
- AVX512ER (AVX-512 Exponential and Reciprocal Instructions)
- AVX512CD (AVX-512 Conflict Detection Instructions)
- AVX512BW (AVX-512 Byte and Word Instructions)
- AVX512VL (AVX-512 Vector Length Extensions)
- AVX512VBMI (AVX-512 Vector Bit Manipulation Instructions)
- MPX (Intel MPX (Memory Protection Extensions))
- ERMS (Enhanced REP MOVSB/STOSB)
- RDTSCP (RDTSCP Instruction)
- CX16 (CMPXCHG16B Instruction)
- SGX (Software Guard Extensions, with activation details)
Performance
- RDTSCP() Returns current cycle count. Can be used for benchmarking.
- SSE2SLOW (SSE2 is supported, but usually not faster)
- SSE3SLOW (SSE3 is supported, but usually not faster)
- ATOM (Atom processor, some SSSE3 instructions are slower)
- Cache line (Probable size of a cache line).
- L1, L2, L3 Cache size on newer Intel/AMD CPUs.
Cpu Vendor/VM
- Intel
- AMD
- VIA
- Transmeta
- NSC
- KVM (Kernel-based Virtual Machine)
- MSVM (Microsoft Hyper-V or Windows Virtual PC)
- VMware
- XenHVM
installing
go get github.com/klauspost/cpuid
example
package main
import (
"fmt"
"github.com/klauspost/cpuid"
)
func main() {
// Print basic CPU information:
fmt.Println("Name:", cpuid.CPU.BrandName)
fmt.Println("PhysicalCores:", cpuid.CPU.PhysicalCores)
fmt.Println("ThreadsPerCore:", cpuid.CPU.ThreadsPerCore)
fmt.Println("LogicalCores:", cpuid.CPU.LogicalCores)
fmt.Println("Family", cpuid.CPU.Family, "Model:", cpuid.CPU.Model)
fmt.Println("Features:", cpuid.CPU.Features)
fmt.Println("Cacheline bytes:", cpuid.CPU.CacheLine)
fmt.Println("L1 Data Cache:", cpuid.CPU.Cache.L1D, "bytes")
fmt.Println("L1 Instruction Cache:", cpuid.CPU.Cache.L1D, "bytes")
fmt.Println("L2 Cache:", cpuid.CPU.Cache.L2, "bytes")
fmt.Println("L3 Cache:", cpuid.CPU.Cache.L3, "bytes")
// Test if we have a specific feature:
if cpuid.CPU.SSE() {
fmt.Println("We have Streaming SIMD Extensions")
}
}
Sample output:
>go run main.go
Name: Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz
PhysicalCores: 2
ThreadsPerCore: 2
LogicalCores: 4
Family 6 Model: 42
Features: CMOV,MMX,MMXEXT,SSE,SSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX,AESNI,CLMUL
Cacheline bytes: 64
We have Streaming SIMD Extensions
private package
In the "private" folder you can find an autogenerated version of the library you can include in your own packages.
For this purpose all exports are removed, and functions and constants are lowercased.
This is not a recommended way of using the library, but provided for convenience, if it is difficult for you to use external packages.
license
This code is published under an MIT license. See LICENSE file for more information.
Documentation
¶
Overview ¶
Package cpuid provides information about the CPU running the current program.
CPU features are detected on startup, and kept for fast access through the life of the application. Currently x86 / x64 (AMD64) is supported.
You can access the CPU information by accessing the shared CPU variable of the cpuid library.
Package home: https://github.com/klauspost/cpuid
Index ¶
- Constants
- func Detect()
- type CPUInfo
- func (c CPUInfo) ADX() bool
- func (c CPUInfo) AMD() bool
- func (c CPUInfo) AVX() bool
- func (c CPUInfo) AVX2() bool
- func (c CPUInfo) AVX512BW() bool
- func (c CPUInfo) AVX512CD() bool
- func (c CPUInfo) AVX512DQ() bool
- func (c CPUInfo) AVX512ER() bool
- func (c CPUInfo) AVX512F() bool
- func (c CPUInfo) AVX512IFMA() bool
- func (c CPUInfo) AVX512PF() bool
- func (c CPUInfo) AVX512VBMI() bool
- func (c CPUInfo) AVX512VL() bool
- func (c CPUInfo) AesNi() bool
- func (c CPUInfo) Amd3dnow() bool
- func (c CPUInfo) Amd3dnowExt() bool
- func (c CPUInfo) Atom() bool
- func (c CPUInfo) BMI1() bool
- func (c CPUInfo) BMI2() bool
- func (c CPUInfo) CX16() bool
- func (c CPUInfo) Clmul() bool
- func (c CPUInfo) Cmov() bool
- func (c CPUInfo) ERMS() bool
- func (c CPUInfo) F16C() bool
- func (c CPUInfo) FMA3() bool
- func (c CPUInfo) FMA4() bool
- func (c CPUInfo) HLE() bool
- func (c CPUInfo) HTT() bool
- func (c CPUInfo) Ia32TscAux() uint32
- func (c CPUInfo) Intel() bool
- func (c CPUInfo) LogicalCPU() int
- func (c CPUInfo) Lzcnt() bool
- func (c CPUInfo) MMX() bool
- func (c CPUInfo) MMXExt() bool
- func (c CPUInfo) MPX() bool
- func (c CPUInfo) NSC() bool
- func (c CPUInfo) NX() bool
- func (c CPUInfo) Popcnt() bool
- func (c CPUInfo) RDTSCP() bool
- func (c CPUInfo) RTCounter() uint64
- func (c CPUInfo) RTM() bool
- func (c CPUInfo) Rdrand() bool
- func (c CPUInfo) Rdseed() bool
- func (c CPUInfo) SHA() bool
- func (c CPUInfo) SSE() bool
- func (c CPUInfo) SSE2() bool
- func (c CPUInfo) SSE2Slow() bool
- func (c CPUInfo) SSE3() bool
- func (c CPUInfo) SSE3Slow() bool
- func (c CPUInfo) SSE4() bool
- func (c CPUInfo) SSE42() bool
- func (c CPUInfo) SSE4A() bool
- func (c CPUInfo) SSSE3() bool
- func (c CPUInfo) TBM() bool
- func (c CPUInfo) Transmeta() bool
- func (c CPUInfo) VIA() bool
- func (c CPUInfo) VM() bool
- func (c CPUInfo) XOP() bool
- type Flags
- type SGXSupport
- type Vendor
Constants ¶
const ( CMOV = 1 << iota // i686 CMOV NX // NX (No-Execute) bit AMD3DNOW // AMD 3DNOW AMD3DNOWEXT // AMD 3DNowExt MMX // standard MMX MMXEXT // SSE integer functions or AMD MMX ext SSE // SSE functions SSE2 // P4 SSE functions SSE3 // Prescott SSE3 functions SSSE3 // Conroe SSSE3 functions SSE4 // Penryn SSE4.1 functions SSE4A // AMD Barcelona microarchitecture SSE4a instructions SSE42 // Nehalem SSE4.2 functions AVX // AVX functions AVX2 // AVX2 functions FMA3 // Intel FMA 3 FMA4 // Bulldozer FMA4 functions XOP // Bulldozer XOP functions F16C // Half-precision floating-point conversion BMI1 // Bit Manipulation Instruction Set 1 BMI2 // Bit Manipulation Instruction Set 2 TBM // AMD Trailing Bit Manipulation LZCNT // LZCNT instruction POPCNT // POPCNT instruction AESNI // Advanced Encryption Standard New Instructions CLMUL // Carry-less Multiplication HTT // Hyperthreading (enabled) HLE // Hardware Lock Elision RTM // Restricted Transactional Memory RDRAND // RDRAND instruction is available RDSEED // RDSEED instruction is available ADX // Intel ADX (Multi-Precision Add-Carry Instruction Extensions) SHA // Intel SHA Extensions AVX512F // AVX-512 Foundation AVX512DQ // AVX-512 Doubleword and Quadword Instructions AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions AVX512PF // AVX-512 Prefetch Instructions AVX512ER // AVX-512 Exponential and Reciprocal Instructions AVX512CD // AVX-512 Conflict Detection Instructions AVX512BW // AVX-512 Byte and Word Instructions AVX512VL // AVX-512 Vector Length Extensions AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions MPX // Intel MPX (Memory Protection Extensions) ERMS // Enhanced REP MOVSB/STOSB RDTSCP // RDTSCP Instruction CX16 // CMPXCHG16B Instruction SGX // Software Guard Extensions // Performance indicators SSE2SLOW // SSE2 is supported, but usually not faster SSE3SLOW // SSE3 is supported, but usually not faster ATOM // Atom processor, some SSSE3 instructions are slower )
Variables ¶
This section is empty.
Functions ¶
func Detect ¶
func Detect()
Detect will re-detect current CPU info. This will replace the content of the exported CPU variable.
Unless you expect the CPU to change while you are running your program you should not need to call this function. If you call this, you must ensure that no other goroutine is accessing the exported CPU variable.
Types ¶
type CPUInfo ¶
type CPUInfo struct { BrandName string // Brand name reported by the CPU VendorID Vendor // Comparable CPU vendor ID Features Flags // Features of the CPU PhysicalCores int // Number of physical processor cores in your CPU. Will be 0 if undetectable. ThreadsPerCore int // Number of threads per physical core. Will be 1 if undetectable. LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable. Family int // CPU family number Model int // CPU model number CacheLine int // Cache line size in bytes. Will be 0 if undetectable. Cache struct { L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected L2 int // L2 Cache (per core or shared). Will be -1 if undetected L3 int // L3 Instruction Cache (per core or shared). Will be -1 if undetected } SGX SGXSupport // contains filtered or unexported fields }
CPUInfo contains information about the detected system CPU.
var CPU CPUInfo
CPU contains information about the CPU as detected on startup, or when Detect last was called.
Use this as the primary entry point to you data, this way queries are
func (CPUInfo) ADX ¶
ADX indicates support of Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
func (CPUInfo) AVX ¶
AVX indicates support of AVX instructions and operating system support of AVX instructions
func (CPUInfo) AVX512DQ ¶
AVX512DQ indicates support of AVX-512 Doubleword and Quadword Instructions
func (CPUInfo) AVX512ER ¶
AVX512ER indicates support of AVX-512 Exponential and Reciprocal Instructions
func (CPUInfo) AVX512IFMA ¶
AVX512IFMA indicates support of AVX-512 Integer Fused Multiply-Add Instructions
func (CPUInfo) AVX512VBMI ¶
AVX512VBMI indicates support of AVX-512 Vector Bit Manipulation Instructions
func (CPUInfo) AesNi ¶
AesNi indicates support of AES-NI instructions (Advanced Encryption Standard New Instructions)
func (CPUInfo) Amd3dnowExt ¶
Amd3dnowExt indicates support of AMD 3DNOW! Extended instructions
func (CPUInfo) Ia32TscAux ¶
Ia32TscAux returns the IA32_TSC_AUX part of the RDTSCP. This variable is OS dependent, but on Linux contains information about the current cpu/core the code is running on. If the RDTSCP instruction isn't supported on the CPU, the value 0 is returned.
func (CPUInfo) LogicalCPU ¶
LogicalCPU will return the Logical CPU the code is currently executing on. This is likely to change when the OS re-schedules the running thread to another CPU. If the current core cannot be detected, -1 will be returned.
func (CPUInfo) MMXExt ¶
MMXExt indicates support of MMXEXT instructions (SSE integer functions or AMD MMX ext)
func (CPUInfo) RTCounter ¶
RTCounter returns the 64-bit time-stamp counter Uses the RDTSCP instruction. The value 0 is returned if the CPU does not support the instruction.
func (CPUInfo) SSE4A ¶
SSE4A indicates support of AMD Barcelona microarchitecture SSE4a instructions
type Flags ¶
type Flags uint64
Flags contains detected cpu features and caracteristics