x86

package
v0.3.0 Latest Latest
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 Go to latest Published: Aug 21, 2018 License: BSD-3-Clause Imports: 8 Imported by: 0

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Index

Constants

View Source 
const (
	Rex  = (1 << 6)
	RexW = Rex | (1 << 3)
	RexR = Rex | (1 << 2)
	RexX = Rex | (1 << 1)
	RexB = Rex | (1 << 0)
)
View Source 
const (
	ModMem       = mod(0)
	ModMemDisp8  = mod((0 << 7) | (1 << 6))
	ModMemDisp32 = mod((1 << 7) | (0 << 6))
	ModReg       = mod((1 << 7) | (1 << 6))
)
View Source 
const (
	MemSIB    = byte((1 << 2))
	MemDisp32 = byte((1 << 2) | (1 << 0))
)
View Source 
const (
	NoIndex = regs.R((1 << 2))
	NoBase  = regs.R((1 << 2) | (1 << 0))
)
View Source 
const (
	RegResult         = regs.Result // rax or xmm0
	RegShiftCount     = regs.R(1)   // rcx
	RegScratch        = regs.R(2)   // rdx or xmm2
	RegImportArgCount = regs.R(2)   // rdx
	RegImportSigIndex = regs.R(3)   // rbx
	RegStackPtr       = regs.R(4)   // rsp
	RegSuspendFlag    = regs.R(9)   // r9
	RegTextBase       = regs.R(12)  // r12
	RegStackLimit     = regs.R(13)  // r13
	RegMemoryBase     = regs.R(14)  // r14
	RegMemoryLimit    = regs.R(15)  // r15

	RegTrapHandlerMMX     = regs.R(0) // mm0
	RegMemoryGrowLimitMMX = regs.R(1) // mm1
	RegScratchMMX         = regs.R(2) // mm2
)
View Source 
const (
	FunctionAlignment = 16
	PaddingByte       = 0xcc // int3 instruction
)

Variables

This section is empty.

Functions

This section is empty.

Types

type ISA added in v0.3.0 

type ISA struct{}

func (ISA) AlignFunction added in v0.3.0 

func (ISA) AlignFunction(code gen.Buffer)

func (ISA) AvailRegs added in v0.3.0 

func (ISA) AvailRegs() uint64

func (ISA) BinaryOp added in v0.3.0 

func (ISA) BinaryOp(code gen.RegCoder, oper uint16, a, b values.Operand) values.Operand

func (ISA) ClearInsnCache added in v0.3.0 

func (ISA) ClearInsnCache()

func (ISA) ConversionOp added in v0.3.0 

func (ISA) ConversionOp(code gen.RegCoder, oper uint16, resultType wasm.Type, source values.Operand) (result values.Operand)

func (ISA) LoadOp added in v0.3.0 

func (ISA) LoadOp(code gen.RegCoder, oper uint16, index values.Operand, resultType wasm.Type, offset uint32) (result values.Operand)

LoadOp makes sure that index gets zero-extended if it's a VarReg operand.

func (ISA) OpAddImmToStackPtr added in v0.3.0 

func (ISA) OpAddImmToStackPtr(code gen.Buffer, offset int32)

func (ISA) OpAddToStackPtr added in v0.3.0 

func (ISA) OpAddToStackPtr(code gen.Buffer, source regs.R)

func (ISA) OpBranch added in v0.3.0 

func (ISA) OpBranch(code gen.Buffer, addr int32) int32

func (ISA) OpBranchIf added in v0.3.0 

func (ISA) OpBranchIf(code gen.Coder, x values.Operand, yes bool, addr int32) (sites []int32)

func (ISA) OpBranchIfOutOfBounds added in v0.3.0 

func (ISA) OpBranchIfOutOfBounds(code gen.Buffer, indexReg regs.R, upperBound, addr int32) int32

OpBranchIfOutOfBounds must not allocate registers. indexReg will be zero-extended.

func (ISA) OpBranchIndirect32 added in v0.3.0 

func (ISA) OpBranchIndirect32(code gen.Buffer, reg regs.R, regZeroExt bool)

OpBranchIndirect32 must not allocate registers. The supplied register is trashed.

func (ISA) OpCall added in v0.3.0 

func (ISA) OpCall(code gen.Buffer, addr int32) (retAddr int32)

func (ISA) OpCallIndirect added in v0.3.0 

func (ISA) OpCallIndirect(code gen.Coder, tableLen, sigIndex int32) int32

OpCallIndirect using table index located in result register.

func (ISA) OpClearIntResultReg added in v0.3.0 

func (ISA) OpClearIntResultReg(code gen.Buffer)

OpClearIntResultReg may update CPU's condition flags.

func (ISA) OpCopyStack added in v0.3.0 

func (ISA) OpCopyStack(code gen.Buffer, targetOffset, sourceOffset int32)

OpCopyStack must not allocate registers.

func (ISA) OpCurrentMemory added in v0.3.0 

func (ISA) OpCurrentMemory(code gen.Buffer) values.Operand

func (ISA) OpEnterExitTrapHandler added in v0.3.0 

func (ISA) OpEnterExitTrapHandler(code gen.Buffer)

func (ISA) OpEnterFunction added in v0.3.0 

func (ISA) OpEnterFunction(code gen.Coder)

func (ISA) OpEnterImportFunction added in v0.3.0 

func (ISA) OpEnterImportFunction(code gen.Buffer, absAddr uint64, variadic bool, argCount, sigIndex int)

func (ISA) OpEnterTrapHandler added in v0.3.0 

func (ISA) OpEnterTrapHandler(code gen.Buffer, id trap.Id)

OpEnterTrapHandler must not generate over 16 bytes of code.

func (ISA) OpGetGlobal added in v0.3.0 

func (ISA) OpGetGlobal(code gen.RegCoder, t wasm.Type, offset int32) values.Operand

OpGetGlobal must not update CPU's condition flags.

func (ISA) OpGrowMemory added in v0.3.0 

func (ISA) OpGrowMemory(code gen.RegCoder, x values.Operand) values.Operand

func (ISA) OpInit added in v0.3.0 

func (ISA) OpInit(code gen.Buffer)

func (ISA) OpInitCall added in v0.3.0 

func (ISA) OpInitCall(code gen.Buffer) (retAddr int32)

func (ISA) OpLoadROIntIndex32ScaleDisp added in v0.3.0 

func (ISA) OpLoadROIntIndex32ScaleDisp(code gen.Coder, t wasm.Type, reg regs.R, regZeroExt bool, scale uint8, addr int32) (resultZeroExt bool)

OpLoadROIntIndex32ScaleDisp must not allocate registers.

func (ISA) OpMove added in v0.3.0 

func (ISA) OpMove(code gen.Coder, targetReg regs.R, x values.Operand, preserveFlags bool) (zeroExt bool)

OpMove must not update CPU's condition flags if preserveFlags is set.

func (ISA) OpMoveIntImm added in v0.3.0 

func (ISA) OpMoveIntImm(code gen.Buffer, reg regs.R, value uint64)

OpMoveIntImm may update CPU's condition flags.

func (ISA) OpMoveReg added in v0.3.0 

func (ISA) OpMoveReg(code gen.Buffer, t wasm.Type, targetReg, sourceReg regs.R)

OpMoveReg must not allocate registers.

func (ISA) OpPush added in v0.3.0 

func (ISA) OpPush(code gen.Coder, x values.Operand)

OpPush must not allocate registers, and must not update CPU's condition flags unless the operand is the condition flags.

func (ISA) OpReturn added in v0.3.0 

func (ISA) OpReturn(code gen.Buffer)

func (ISA) OpSelect added in v0.3.0 

func (ISA) OpSelect(code gen.RegCoder, a, b, condOperand values.Operand) values.Operand

func (ISA) OpSetGlobal added in v0.3.0 

func (ISA) OpSetGlobal(code gen.Coder, offset int32, x values.Operand)

OpSetGlobal must not update CPU's condition flags.

func (ISA) OpShiftRightLogical32Bits added in v0.3.0 

func (ISA) OpShiftRightLogical32Bits(code gen.Buffer, subject regs.R)

OpShiftRightLogical32Bits must not allocate registers.

func (ISA) OpStoreStack added in v0.3.0 

func (ISA) OpStoreStack(code gen.Coder, offset int32, x values.Operand)

OpStoreStack must not allocate registers.

func (ISA) OpStoreStackReg added in v0.3.0 

func (ISA) OpStoreStackReg(code gen.Buffer, t wasm.Type, offset int32, reg regs.R)

OpStoreStackReg must not allocate registers.

func (ISA) OpSwap added in v0.3.0 

func (ISA) OpSwap(code gen.Buffer, cat gen.RegCategory, a, b regs.R)

OpSwap must not allocate registers, or update CPU's condition flags.

func (ISA) OpTrapIfStackExhausted added in v0.3.0 

func (ISA) OpTrapIfStackExhausted(code gen.Coder) (stackCheckAddr int32)

func (ISA) ParamRegs added in v0.3.0 

func (ISA) ParamRegs() [2][]regs.R

func (ISA) PutUint32 added in v0.3.0 

func (ISA) PutUint32(b []byte, val uint32)

func (ISA) StoreOp added in v0.3.0 

func (ISA) StoreOp(code gen.RegCoder, oper uint16, index, x values.Operand, offset uint32)

StoreOp makes sure that index gets zero-extended if it's a VarReg operand.

func (ISA) UnaryOp added in v0.3.0 

func (ISA) UnaryOp(code gen.RegCoder, oper uint16, x values.Operand) values.Operand

func (ISA) UpdateBranches added in v0.3.0 

func (ISA) UpdateBranches(text []byte, l *links.L)

UpdateBranches modifies 32-bit relocations of Jmp and Jcc instructions.

func (ISA) UpdateCalls added in v0.3.0 

func (ISA) UpdateCalls(text []byte, l *links.L)

UpdateCalls modifies CallRel instructions, possibly while they are being executed.

func (ISA) UpdateStackCheck added in v0.3.0 

func (ISA) UpdateStackCheck(text []byte, addr, disp int32)

UpdateStackCheck modifies the 32-bit displacement of a Lea instruction.

Source Files

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