Documentation
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Overview ¶
Package ppc64 implements a PPC64 assembler that assembles Go asm into the corresponding PPC64 binary instructions as defined by the Power ISA. Since POWER8 is the minimum instruction set used by GOARCHes ppc64le and ppc64, refer to ISA 2.07B or later for details.
This document provides information on how to write code in Go assembler for PPC64, focusing on the differences between Go and PPC64 assembly language. It assumes some knowledge of PPC64 assembler. The original implementation of PPC64 in Go defined many opcodes that are different from PPC64 opcodes, but updates to the Go assembly language used mnemonics that are mostly similar if not identical to the PPC64 mneumonics, such as VMX and VSX instructions. Not all detail is included here; refer to the Power ISA document if interested in more detail.
In the examples below, the Go assembly is on the left, PPC64 assembly on the right.
1. Operand ordering
In Go asm, the last operand (right) is the target operand, but with PPC64 asm, the first operand (left) is the target. In general, the remaining operands are in the same order except in a few special cases, especially those with 4 operands. Example: ADD R3, R4, R5 <=> add r5, r3, r4
2. Constant operands
In Go asm, an operand that starts with '$' indicates a constant value. If the instruction using the constant has an immediate version of the opcode, then an immediate value is used with the opcode if possible. Example: ADD $1, R3, R4 <=> addi r4, r3, 1
3. Opcodes setting condition codes
In PPC64 asm, some instructions other than compares have variations that can set the condition code where meaningful. This is indicated by adding '.' to the end of the PPC64 instruction. In Go asm, these instructions have 'CC' at the end of the opcode. The possible settings of the condition code depend on the instruction. CR0 is the default for fixed-point instructions; CR1 for floating point; CR6 for vector instructions. Example: ANDCC R3, R4, R5 <=> and. r5, r3, r4 (set CR0)
4. Loads and stores from memory
In Go asm, opcodes starting with 'MOV' indicate a load or store. When the target
is a memory reference, then it is a store; when the target is a register and the
source is a memory reference, then it is a load.
MOV{B,H,W,D} variations identify the size as byte, halfword, word, doubleword.
Adding 'Z' to the opcode for a load indicates zero extend; if omitted it is sign extend.
Adding 'U' to a load or store indicates an update of the base register with the offset.
Adding 'BR' to an opcode indicates byte-reversed load or store, or the order opposite
of the expected endian order. If 'BR' is used then zero extend is assumed.
Memory references n(Ra) indicate the address in Ra + n. When used with an update form
of an opcode, the value in Ra is incremented by n.
Memory references (Ra+Rb) or (Ra)(Rb) indicate the address Ra + Rb, used by indexed
loads or stores. Both forms are accepted. When used with an update then the base register
is updated by the value in the index register.
Examples:
MOVD (R3), R4 <=> ld r4,0(r3)
MOVW (R3), R4 <=> lwa r4,0(r3)
MOVWZU 4(R3), R4 <=> lwzu r4,4(r3)
MOVWZ (R3+R5), R4 <=> lwzx r4,r3,r5
MOVHZ (R3), R4 <=> lhz r4,0(r3)
MOVHU 2(R3), R4 <=> lhau r4,2(r3)
MOVBZ (R3), R4 <=> lbz r4,0(r3)
MOVD R4,(R3) <=> std r4,0(r3)
MOVW R4,(R3) <=> stw r4,0(r3)
MOVW R4,(R3+R5) <=> stwx r4,r3,r5
MOVWU R4,4(R3) <=> stwu r4,4(r3)
MOVH R4,2(R3) <=> sth r4,2(r3)
MOVBU R4,(R3)(R5) <=> stbux r4,r3,r5
4. Compares
When an instruction does a compare or other operation that might result in a condition code, then the resulting condition is set in a field of the condition register. The condition register consists of 8 4-bit fields named CR0 - CR7. When a compare instruction identifies a CR then the resulting condition is set in that field to be read by a later branch or isel instruction. Within these fields, bits are set to indicate less than, greater than, or equal conditions. Once an instruction sets a condition, then a subsequent branch, isel or other instruction can read the condition field and operate based on the bit settings. Examples: CMP R3, R4 <=> cmp r3, r4 (CR0 assumed) CMP R3, R4, CR1 <=> cmp cr1, r3, r4 Note that the condition register is the target operand of compare opcodes, so the remaining operands are in the same order for Go asm and PPC64 asm. When CR0 is used then it is implicit and does not need to be specified.
5. Branches
Many branches are represented as a form of the BC instruction. There are
other extended opcodes to make it easier to see what type of branch is being
used.
The following is a brief description of the BC instruction and its commonly
used operands.
BC op1, op2, op3
op1: type of branch
16 -> bctr (branch on ctr)
12 -> bcr (branch if cr bit is set)
8 -> bcr+bctr (branch on ctr and cr values)
4 -> bcr != 0 (branch if specified cr bit is not set)
There are more combinations but these are the most common.
op2: condition register field and condition bit
This contains an immediate value indicating which condition field
to read and what bits to test. Each field is 4 bits long with CR0
at bit 0, CR1 at bit 4, etc. The value is computed as 4*CR+condition
with these condition values:
0 -> LT
1 -> GT
2 -> EQ
3 -> OVG
Thus 0 means test CR0 for LT, 5 means CR1 for GT, 30 means CR7 for EQ.
op3: branch target
Examples:
BC 12, 0, target <=> blt cr0, target
BC 12, 2, target <=> beq cr0, target
BC 12, 5, target <=> bgt cr1, target
BC 12, 30, target <=> beq cr7, target
BC 4, 6, target <=> bne cr1, target
BC 4, 1, target <=> ble cr1, target
The following extended opcodes are available for ease of use and readability:
BNE CR2, target <=> bne cr2, target
BEQ CR4, target <=> beq cr4, target
BLT target <=> blt target (cr0 default)
BGE CR7, target <=> bge cr7, target
Refer to the ISA for more information on additional values for the BC instruction,
how to handle OVG information, and much more.
5. Align directive
Starting with Go 1.12, Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned to the specified value. Currently 8 and 16 are the only supported values, and a maximum of 2 NOPs will be added to align the code. That means in the case where the code is aligned to 4 but PCALIGN $16 is at that location, the code will only be aligned to 8 to avoid adding 3 NOPs. The purpose of this directive is to improve performance for cases like loops where better alignment (8 or 16 instead of 4) might be helpful. This directive exists in PPC64 assembler and is frequently used by PPC64 assembler writers. PCALIGN $16 PCALIGN $8 Functions in Go are aligned to 16 bytes, as is the case in all other compilers for PPC64.
Register naming ¶
1. Special register usage in Go asm
The following registers should not be modified by user Go assembler code. R0: Go code expects this register to contain the value 0. R1: Stack pointer R2: TOC pointer when compiled with -shared or -dynlink (a.k.a position independent code) R13: TLS pointer R30: g (goroutine) Register names: Rn is used for general purpose registers. (0-31) Fn is used for floating point registers. (0-31) Vn is used for vector registers. Slot 0 of Vn overlaps with Fn. (0-31) VSn is used for vector-scalar registers. V0-V31 overlap with VS32-VS63. (0-63) CTR represents the count register. LR represents the link register.
Index ¶
- Constants
- Variables
- func AOP_DQ(op uint32, d uint32, a uint32, b uint32) uint32
- func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32
- func AOP_IR(op uint32, d uint32, simm uint32) uint32
- func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32
- func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32
- func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32
- func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32
- func AOP_RR(op uint32, d uint32, a uint32) uint32
- func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32
- func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
- func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
- func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32
- func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32
- func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32
- func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32
- func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
- func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
- func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
- func DRconv(a int) string
- func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32
- func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32
- func OP(o uint32, xo uint32) uint32
- func OPCC(o uint32, xo uint32, rc uint32) uint32
- func OPDQ(o uint32, xo uint32, oe uint32) uint32
- func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32
- func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32
- func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32
- func OPVXX1(o uint32, xo uint32, oe uint32) uint32
- func OPVXX2(o uint32, xo uint32, oe uint32) uint32
- func OPVXX3(o uint32, xo uint32, oe uint32) uint32
- func OPVXX4(o uint32, xo uint32, oe uint32) uint32
- func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32
- func OP_BCR(op uint32, bo uint32, bi uint32) uint32
- func OP_BR(op uint32, li uint32, aa uint32) uint32
- func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32
- type Optab
Constants ¶
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const ( NSNAME = 8 NSYM = 50 NREG = 32 /* number of general registers */ NFREG = 32 /* number of floating point registers */ )
* powerpc 64
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const ( /* RBasePPC64 = 4096 */ /* R0=4096 ... R31=4127 */ REG_R0 = obj.RBasePPC64 + iota REG_R1 REG_R2 REG_R3 REG_R4 REG_R5 REG_R6 REG_R7 REG_R8 REG_R9 REG_R10 REG_R11 REG_R12 REG_R13 REG_R14 REG_R15 REG_R16 REG_R17 REG_R18 REG_R19 REG_R20 REG_R21 REG_R22 REG_R23 REG_R24 REG_R25 REG_R26 REG_R27 REG_R28 REG_R29 REG_R30 REG_R31 /* F0=4128 ... F31=4159 */ REG_F0 REG_F1 REG_F2 REG_F3 REG_F4 REG_F5 REG_F6 REG_F7 REG_F8 REG_F9 REG_F10 REG_F11 REG_F12 REG_F13 REG_F14 REG_F15 REG_F16 REG_F17 REG_F18 REG_F19 REG_F20 REG_F21 REG_F22 REG_F23 REG_F24 REG_F25 REG_F26 REG_F27 REG_F28 REG_F29 REG_F30 REG_F31 /* V0=4160 ... V31=4191 */ REG_V0 REG_V1 REG_V2 REG_V3 REG_V4 REG_V5 REG_V6 REG_V7 REG_V8 REG_V9 REG_V10 REG_V11 REG_V12 REG_V13 REG_V14 REG_V15 REG_V16 REG_V17 REG_V18 REG_V19 REG_V20 REG_V21 REG_V22 REG_V23 REG_V24 REG_V25 REG_V26 REG_V27 REG_V28 REG_V29 REG_V30 REG_V31 /* VS0=4192 ... VS63=4255 */ REG_VS0 REG_VS1 REG_VS2 REG_VS3 REG_VS4 REG_VS5 REG_VS6 REG_VS7 REG_VS8 REG_VS9 REG_VS10 REG_VS11 REG_VS12 REG_VS13 REG_VS14 REG_VS15 REG_VS16 REG_VS17 REG_VS18 REG_VS19 REG_VS20 REG_VS21 REG_VS22 REG_VS23 REG_VS24 REG_VS25 REG_VS26 REG_VS27 REG_VS28 REG_VS29 REG_VS30 REG_VS31 REG_VS32 REG_VS33 REG_VS34 REG_VS35 REG_VS36 REG_VS37 REG_VS38 REG_VS39 REG_VS40 REG_VS41 REG_VS42 REG_VS43 REG_VS44 REG_VS45 REG_VS46 REG_VS47 REG_VS48 REG_VS49 REG_VS50 REG_VS51 REG_VS52 REG_VS53 REG_VS54 REG_VS55 REG_VS56 REG_VS57 REG_VS58 REG_VS59 REG_VS60 REG_VS61 REG_VS62 REG_VS63 REG_CR0 REG_CR1 REG_CR2 REG_CR3 REG_CR4 REG_CR5 REG_CR6 REG_CR7 REG_MSR REG_FPSCR REG_CR REG_SPECIAL = REG_CR0 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers REG_XER = REG_SPR0 + 1 REG_LR = REG_SPR0 + 8 REG_CTR = REG_SPR0 + 9 REGZERO = REG_R0 /* set to zero */ REGSP = REG_R1 REGSB = REG_R2 REGRET = REG_R3 REGARG = -1 /* -1 disables passing the first argument in register */ REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */ REGRT2 = REG_R4 /* reserved for runtime, duffcopy */ REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ REGCTXT = REG_R11 /* context for closures */ REGTLS = REG_R13 /* C ABI TLS base pointer */ REGMAX = REG_R27 REGEXT = REG_R30 /* external registers allocated from here down */ REGG = REG_R30 /* G */ REGTMP = REG_R31 /* used by the linker */ FREGRET = REG_F0 FREGMIN = REG_F17 /* first register variable */ FREGMAX = REG_F26 /* last register variable for 9g only */ FREGEXT = REG_F26 /* first external register */ )
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const ( /* mark flags */ LABEL = 1 << 0 LEAF = 1 << 1 FLOAT = 1 << 2 BRANCH = 1 << 3 LOAD = 1 << 4 FCMP = 1 << 5 SYNC = 1 << 6 LIST = 1 << 7 FOLL = 1 << 8 NOSCHED = 1 << 9 )
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const ( BI_CR0 = 0 BI_CR1 = 4 BI_CR2 = 8 BI_CR3 = 12 BI_CR4 = 16 BI_CR5 = 20 BI_CR6 = 24 BI_CR7 = 28 BI_LT = 0 BI_GT = 1 BI_EQ = 2 BI_OVF = 3 )
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const ( BO_BCTR = 16 // branch on ctr value BO_BCR = 12 // branch on cr value BO_BCRBCTR = 8 // branch on ctr and cr value BO_NOTBCR = 4 // branch on not cr value BO_UNLIKELY = 2 // value for unlikely BO_LIKELY = 3 // value for likely )
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const ( C_COND_LT = iota // 0 result is negative C_COND_GT // 1 result is positive C_COND_EQ // 2 result is zero C_COND_SO // 3 summary overflow or FP compare w/ NaN )
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const ( C_NONE = iota C_REG C_FREG C_VREG C_VSREG C_CREG C_SPR /* special processor register */ C_ZCON C_SCON /* 16 bit signed */ C_UCON /* 32 bit signed, low 16 bits 0 */ C_ADDCON /* -0x8000 <= v < 0 */ C_ANDCON /* 0 < v <= 0xFFFF */ C_LCON /* other 32 */ C_DCON /* other 64 (could subdivide further) */ C_SACON /* $n(REG) where n <= int16 */ C_SECON C_LACON /* $n(REG) where int16 < n <= int32 */ C_LECON C_DACON /* $n(REG) where int32 < n */ C_SBRA C_LBRA C_LBRAPIC C_SAUTO C_LAUTO C_SEXT C_LEXT C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG C_SOREG // register + signed offset C_LOREG C_FPSCR C_MSR C_XER C_LR C_CTR C_ANY C_GOK C_ADDR C_GOTADDR C_TOCADDR C_TLS_LE C_TLS_IE C_TEXTSIZE C_NCLASS /* must be the last */ )
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const ( AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota AADDCC AADDIS AADDV AADDVCC AADDC AADDCCC AADDCV AADDCVCC AADDME AADDMECC AADDMEVCC AADDMEV AADDE AADDECC AADDEVCC AADDEV AADDZE AADDZECC AADDZEVCC AADDZEV AADDEX AAND AANDCC AANDN AANDNCC AANDISCC ABC ABCL ABEQ ABGE // not LT = G/E/U ABGT ABLE // not GT = L/E/U ABLT ABNE // not EQ = L/G/U ABVC // Unordered-clear ABVS // Unordered-set ACMP ACMPU ACMPEQB ACNTLZW ACNTLZWCC ACRAND ACRANDN ACREQV ACRNAND ACRNOR ACROR ACRORN ACRXOR ADIVW ADIVWCC ADIVWVCC ADIVWV ADIVWU ADIVWUCC ADIVWUVCC ADIVWUV AEQV AEQVCC AEXTSB AEXTSBCC AEXTSH AEXTSHCC AFABS AFABSCC AFADD AFADDCC AFADDS AFADDSCC AFCMPO AFCMPU AFCTIW AFCTIWCC AFCTIWZ AFCTIWZCC AFDIV AFDIVCC AFDIVS AFDIVSCC AFMADD AFMADDCC AFMADDS AFMADDSCC AFMOVD AFMOVDCC AFMOVDU AFMOVS AFMOVSU AFMOVSX AFMOVSZ AFMSUB AFMSUBCC AFMSUBS AFMSUBSCC AFMUL AFMULCC AFMULS AFMULSCC AFNABS AFNABSCC AFNEG AFNEGCC AFNMADD AFNMADDCC AFNMADDS AFNMADDSCC AFNMSUB AFNMSUBCC AFNMSUBS AFNMSUBSCC AFRSP AFRSPCC AFSUB AFSUBCC AFSUBS AFSUBSCC AISEL AMOVMW ALBAR ALHAR ALSW ALWAR ALWSYNC AMOVDBR AMOVWBR AMOVB AMOVBU AMOVBZ AMOVBZU AMOVH AMOVHBR AMOVHU AMOVHZ AMOVHZU AMOVW AMOVWU AMOVFL AMOVCRFS AMTFSB0 AMTFSB0CC AMTFSB1 AMTFSB1CC AMULHW AMULHWCC AMULHWU AMULHWUCC AMULLW AMULLWCC AMULLWVCC AMULLWV ANAND ANANDCC ANEG ANEGCC ANEGVCC ANEGV ANOR ANORCC AOR AORCC AORN AORNCC AORIS AREM AREMCC AREMV AREMVCC AREMU AREMUCC AREMUV AREMUVCC ARFI ARLWMI ARLWMICC ARLWNM ARLWNMCC ASLW ASLWCC ASRW ASRAW ASRAWCC ASRWCC ASTBCCC ASTSW ASTWCCC ASUB ASUBCC ASUBVCC ASUBC ASUBCCC ASUBCV ASUBCVCC ASUBME ASUBMECC ASUBMEVCC ASUBMEV ASUBV ASUBE ASUBECC ASUBEV ASUBEVCC ASUBZE ASUBZECC ASUBZEVCC ASUBZEV ASYNC AXOR AXORCC AXORIS ADCBF ADCBI ADCBST ADCBT ADCBTST ADCBZ AECIWX AECOWX AEIEIO AICBI AISYNC APTESYNC ATLBIE ATLBIEL ATLBSYNC ATW ASYSCALL AWORD ARFCI AFCPSGN AFCPSGNCC /* optional on 32-bit */ AFRES AFRESCC AFRIM AFRIMCC AFRIP AFRIPCC AFRIZ AFRIZCC AFRIN AFRINCC AFRSQRTE AFRSQRTECC AFSEL AFSELCC AFSQRT AFSQRTCC AFSQRTS AFSQRTSCC ACNTLZD ACNTLZDCC ACMPW /* CMP with L=0 */ ACMPWU ACMPB AFTDIV AFTSQRT ADIVD ADIVDCC ADIVDE ADIVDECC ADIVDEU ADIVDEUCC ADIVDVCC ADIVDV ADIVDU ADIVDUCC ADIVDUVCC ADIVDUV AEXTSW AEXTSWCC /* AFCFIW; AFCFIWCC */ AFCFID AFCFIDCC AFCFIDU AFCFIDUCC AFCFIDS AFCFIDSCC AFCTID AFCTIDCC AFCTIDZ AFCTIDZCC ALDAR AMOVD AMOVDU AMOVWZ AMOVWZU AMULHD AMULHDCC AMULHDU AMULHDUCC AMULLD AMULLDCC AMULLDVCC AMULLDV ARFID ARLDMI ARLDMICC ARLDIMI ARLDIMICC ARLDC ARLDCCC ARLDCR ARLDCRCC ARLDICR ARLDICRCC ARLDCL ARLDCLCC ARLDICL ARLDICLCC AROTL AROTLW ASLBIA ASLBIE ASLBMFEE ASLBMFEV ASLBMTE ASLD ASLDCC ASRD ASRAD ASRADCC ASRDCC ASTDCCC ATD /* 64-bit pseudo operation */ ADWORD AREMD AREMDCC AREMDV AREMDVCC AREMDU AREMDUCC AREMDUV AREMDUVCC /* more 64-bit operations */ AHRFID APOPCNTD APOPCNTW APOPCNTB ACNTTZW ACNTTZWCC ACNTTZD ACNTTZDCC ACOPY APASTECC ADARN ALDMX AMADDHD AMADDHDU AMADDLD /* Vector */ ALV ALVEBX ALVEHX ALVEWX ALVX ALVXL ALVSL ALVSR ASTV ASTVEBX ASTVEHX ASTVEWX ASTVX ASTVXL AVAND AVANDC AVNAND AVOR AVORC AVNOR AVXOR AVEQV AVADDUM AVADDUBM AVADDUHM AVADDUWM AVADDUDM AVADDUQM AVADDCU AVADDCUQ AVADDCUW AVADDUS AVADDUBS AVADDUHS AVADDUWS AVADDSS AVADDSBS AVADDSHS AVADDSWS AVADDE AVADDEUQM AVADDECUQ AVSUBUM AVSUBUBM AVSUBUHM AVSUBUWM AVSUBUDM AVSUBUQM AVSUBCU AVSUBCUQ AVSUBCUW AVSUBUS AVSUBUBS AVSUBUHS AVSUBUWS AVSUBSS AVSUBSBS AVSUBSHS AVSUBSWS AVSUBE AVSUBEUQM AVSUBECUQ AVMULESB AVMULOSB AVMULEUB AVMULOUB AVMULESH AVMULOSH AVMULEUH AVMULOUH AVMULESW AVMULOSW AVMULEUW AVMULOUW AVMULUWM AVPMSUM AVPMSUMB AVPMSUMH AVPMSUMW AVPMSUMD AVMSUMUDM AVR AVRLB AVRLH AVRLW AVRLD AVS AVSLB AVSLH AVSLW AVSL AVSLO AVSRB AVSRH AVSRW AVSR AVSRO AVSLD AVSRD AVSA AVSRAB AVSRAH AVSRAW AVSRAD AVSOI AVSLDOI AVCLZ AVCLZB AVCLZH AVCLZW AVCLZD AVPOPCNT AVPOPCNTB AVPOPCNTH AVPOPCNTW AVPOPCNTD AVCMPEQ AVCMPEQUB AVCMPEQUBCC AVCMPEQUH AVCMPEQUHCC AVCMPEQUW AVCMPEQUWCC AVCMPEQUD AVCMPEQUDCC AVCMPGT AVCMPGTUB AVCMPGTUBCC AVCMPGTUH AVCMPGTUHCC AVCMPGTUW AVCMPGTUWCC AVCMPGTUD AVCMPGTUDCC AVCMPGTSB AVCMPGTSBCC AVCMPGTSH AVCMPGTSHCC AVCMPGTSW AVCMPGTSWCC AVCMPGTSD AVCMPGTSDCC AVCMPNEZB AVCMPNEZBCC AVPERM AVPERMXOR AVBPERMQ AVBPERMD AVSEL AVSPLT AVSPLTB AVSPLTH AVSPLTW AVSPLTI AVSPLTISB AVSPLTISH AVSPLTISW AVCIPH AVCIPHER AVCIPHERLAST AVNCIPH AVNCIPHER AVNCIPHERLAST AVSBOX AVSHASIGMA AVSHASIGMAW AVSHASIGMAD AVMRGEW AVMRGOW /* VSX */ ALXV ALXVD2X ALXVW4X ALXVH8X ALXVB16X ALXVDSX ASTXV ASTXVD2X ASTXVW4X ASTXVH8X ASTXVB16X ALXS ALXSDX ASTXS ASTXSDX ALXSI ALXSIWAX ALXSIWZX ASTXSI ASTXSIWX AMFVSR AMFVSRD AMFFPRD AMFVRD AMFVSRWZ AMFVSRLD AMTVSR AMTVSRD AMTFPRD AMTVRD AMTVSRWA AMTVSRWZ AMTVSRDD AMTVSRWS AXXLAND AXXLANDQ AXXLANDC AXXLEQV AXXLNAND AXXLOR AXXLORC AXXLNOR AXXLORQ AXXLXOR AXXSEL AXXMRG AXXMRGHW AXXMRGLW AXXSPLT AXXSPLTW AXXPERM AXXPERMDI AXXSI AXXSLDWI AXSCV AXSCVDPSP AXSCVSPDP AXSCVDPSPN AXSCVSPDPN AXVCV AXVCVDPSP AXVCVSPDP AXSCVX AXSCVDPSXDS AXSCVDPSXWS AXSCVDPUXDS AXSCVDPUXWS AXSCVXP AXSCVSXDDP AXSCVUXDDP AXSCVSXDSP AXSCVUXDSP AXVCVX AXVCVDPSXDS AXVCVDPSXWS AXVCVDPUXDS AXVCVDPUXWS AXVCVSPSXDS AXVCVSPSXWS AXVCVSPUXDS AXVCVSPUXWS AXVCVXP AXVCVSXDDP AXVCVSXWDP AXVCVUXDDP AXVCVUXWDP AXVCVSXDSP AXVCVSXWSP AXVCVUXDSP AXVCVUXWSP ALAST // aliases ABR = obj.AJMP ABL = obj.ACALL )
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const ( /* each rhs is OPVCC(_, _, _, _) */ OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 )
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const ( D_FORM = iota DS_FORM )
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const (
BIG = 32768 - 8
)
* GENERAL: * * compiler allocates R3 up as temps * compiler allocates register variables R7-R27 * compiler allocates external registers R30 down * * compiler allocates register variables F17-F26 * compiler allocates external registers F26 down
Variables ¶
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var Anames = []string{}/* 607 elements not displayed */
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var Linkppc64 = obj.LinkArch{ Arch: sys.ArchPPC64, Init: buildop, Preprocess: preprocess, Assemble: span9, Progedit: progedit, DWARFRegisters: PPC64DWARFRegisters, }
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var Linkppc64le = obj.LinkArch{ Arch: sys.ArchPPC64LE, Init: buildop, Preprocess: preprocess, Assemble: span9, Progedit: progedit, DWARFRegisters: PPC64DWARFRegisters, }
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var PPC64DWARFRegisters = map[int16]int16{}
OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
Functions ¶
Types ¶
Source Files
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