cpu

Documentation

Index

• type Bus
  • func NewBus(defaultManager ...PortManager) Bus
  • func NewWatchableBus(bus Bus) Bus
• type CPU
• type CPUTracer
• type DebuggerCallbacks
• type Dumpable
• type PortManager
• type PortMask
• type RAM
  • func NewRAM(bank []byte, mask uint16) RAM
• type ROM
  • func NewROM(bank []byte, mask uint16, write ...RomWrite) ROM
• type RegPair
  • func (reg *RegPair) Get() uint16
  • func (reg *RegPair) Set(hl uint16)
• type RomWrite

Types

type Bus

type Bus interface {
	Write(addr uint16, data uint8)
	Read(addr uint16) uint8
	RegisterPort(name string, mask PortMask, manager PortManager)
	DumpMap() string
	GetDumplables() map[string]Dumpable
}

func NewBus

func NewBus(defaultManager ...PortManager) Bus

func NewWatchableBus

func NewWatchableBus(bus Bus) Bus

type CPU

type CPU interface {
	Interrupt(bool) // TODO:move this to each CPU interface
	NMI(bool)
	Halt()
	Wait(bool)
	Reset()
	Tick()

	CurrentOP() string

	SetTracer(CPUTracer)
	SetDebugger(DebuggerCallbacks)
}

type CPUTracer

type CPUTracer interface {
	AppendLastOP(string)
	SetNextOP(string)
	SetDiss(pc uint16, getMemory func(pc, leng uint16) []byte)
}

type DebuggerCallbacks

type DebuggerCallbacks interface {
	Eval(pc uint16)
	EvalInterrupt()

	EvalLine() bool
	EvalFrame() bool
}

type Dumpable

type Dumpable interface {
	Memory() []byte
}

type PortManager

type PortManager interface {
	ReadPort(port uint16) (byte, bool)
	WritePort(port uint16, data byte)
}

type PortMask

type PortMask struct {
	Mask  uint16
	Value uint16
}

type RAM

type RAM interface {
	PortManager
	SetBank([]byte)
}

func NewRAM

func NewRAM(bank []byte, mask uint16) RAM

type ROM

type ROM interface {
	PortManager
	SetBank([]byte)
}

func NewROM

func NewROM(bank []byte, mask uint16, write ...RomWrite) ROM

type RegPair

type RegPair struct {
	H, L *byte
}

func (*RegPair) Get

func (reg *RegPair) Get() uint16

func (*RegPair) Set

func (reg *RegPair) Set(hl uint16)

type RomWrite

type RomWrite func(uint16, uint8)